An input segmented pipelined successive approximation analog-to-digital converter

Abstract

The present invention belongs to the field of integrated circuit technology, and specifically relates to an input segmented pipeline successive approximation analog-to-digital converter. The circuit of the present invention includes two symmetrical channels, each channel including: an input buffer, a two-stage successive approximation analog-to-digital converter, an adaptive digital selection logic circuit, and an open-loop margin amplifier. The input buffer amplifies the input signal and divides it into four segments of analog signals; four first-stage successive approximation analog-to-digital converters sample and quantize the four segments of analog signals respectively, thereby obtaining four groups of digital code values; the adaptive digital selection logic circuit is used to select the correct quantization result from the four groups of digital code values, and the corresponding analog margin is passed to the open-loop margin amplifier; the open-loop margin amplifier amplifies the analog margin signal, and the second-stage successive approximation analog-to-digital converter samples and quantizes it, and generates a second-stage digital code value. The present invention applies a low-voltage domain and low-power input buffer to a high-performance analog-to-digital converter.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a pipeline successive approximation analog-to-digital converter. Background Art

[0002] As data requirements increase, high-speed and high-resolution analog-to-digital converters are essential. Pipelined-SAR ADCs are more energy-efficient than traditional pipeline ADCs and offer significant advantages over SAR ADCs in terms of speed, resolution, and linearity.

[0003] For capacitive SAR ADCs using top-plate sampling, during the sampling cycle, the bottom plates of all capacitors are connected to a fixed DC voltage, while the top plates are connected to the sampling switch. Therefore, for the front-end analog circuitry driving the SAR ADC, its load is the total sampling capacitance. However, as ADC resolution increases, the total number of capacitors increases exponentially, placing high demands on the input buffer circuitry. This is especially true for high-speed ADC driver circuits, as driving such large capacitors in a short period of time while maintaining high linearity across a wide output swing (ideally reaching the ADC's full input swing) undoubtedly increases the design complexity.

[0004] The most common input buffer circuit uses a source follower structure. However, the source follower's linearization technique involves stacking multiple transistors from the power supply to ground. To achieve an output signal that meets the ADC's full-swing input, the buffer's voltage domain must be significantly higher than the ADC's voltage domain. Furthermore, driving a high-speed, high-precision ADC essentially requires charging the sampling capacitor in a sufficiently short time, which requires the driver circuit to have a sufficiently high slew rate and small-signal bandwidth. The small-signal bandwidth of a source follower is determined solely by its transconductance. Increasing both the slew rate and bandwidth increases the current, resulting in significant circuit power consumption. Currently, input buffer circuit power consumption is increasingly becoming the primary source of power consumption for high-performance ADCs.

[0005] Therefore, an input buffer with low power consumption and no voltage domain crossing is the key to designing a high-performance ADC. Summary of the Invention

[0006] The present invention aims to provide an input segmented pipelined successive approximation analog-to-digital converter that can reduce the power consumption and design complexity of an input buffer, thereby further improving circuit performance.

[0007] The design principle of the present invention is shown in Formula 1. When the signal power and noise power increase by M times at the same time, the signal-to-noise ratio does not change, while the sampling capacitor is reduced to 1 / M of the original. The reduction of the sampling capacitor can effectively improve the overall power consumption and area of the input buffer and analog-to-digital converter. 2 The SAR ADC structure can greatly reduce the power consumption and design complexity of the input buffer. In addition, the present invention adopts a symmetrical dual-channel structure to further improve the performance of the circuit.

[0008] (1).

[0009] The present invention proposes an input segmented pipeline successive approximation analog-to-digital converter, whose overall circuit consists of two symmetrical channels. Each channel circuit includes: 4 open-loop input buffers (InputBuffer) with different input reference voltages, 4 first-stage successive approximation analog-to-digital converters (SAR ADC), an adaptive digital selection logic circuit (MUX), an open-loop margin amplifier (RA) and a second-stage successive approximation analog-to-digital converter (SAR ADC); the present invention uses an input buffer to amplify the input signal and divide it into four different quantization intervals; uses four first-stage successive approximation analog-to-digital converters to convert the analog signals of these four intervals into digital code values respectively; uses an adaptive digital selection logic circuit to select the correct quantization result from the four groups of digital code values, and transmits its corresponding analog margin to the open-loop margin amplifier; the open-loop margin amplifier amplifies the analog margin signal, and the amplified signal is sampled and quantized by the second-stage successive approximation analog-to-digital converter to generate a second-stage quantized digital code. The front and back stages in each channel work in a pipeline manner, and the digital code values of the first and second stages are output after synchronous processing. Wherein:

[0010] The four open-loop input buffers with different input reference voltages compare the input signal with four different sets of input reference voltages to amplify the input signal to four different intervals;

[0011] The four first-stage SAR ADCs simultaneously perform top-plate sampling and quantization on the four groups of input signals after amplification and segmentation, and generate four groups of first-stage quantized digital codes and quantized analog residuals;

[0012] The adaptive MUX compares the four groups of first-level quantization digital codes to obtain a correct group of first-level quantization digital codes, and controls the transmission of the analog margin corresponding to the digital code;

[0013] The open loop RA amplifies the analog residual signal, and the amplified signal is sampled and quantized by the second stage SAR ADC to generate a second stage quantized digital code;

[0014] The two-stage SAR ADC works in a pipeline manner, and the digital code values of the first and second stages are synchronously processed and output.

[0015] In the present invention, the four open-loop input buffers with different input reference voltages are as follows: Figure 1 As shown, the circuit includes a first-stage four-input differential amplifier (101), a second-stage pseudo differential amplifier (102) and a common-mode feedback amplifier (103); wherein the first-stage four-input differential amplifier (101) performs a differential operation on the input analog signal and the input reference voltage; the second-stage pseudo differential amplifier (102) amplifies the differential signal; and the common-mode feedback amplifier (103) performs a differential operation on the output common-mode voltage and the ideal common-mode voltage and feeds the amplified voltage back to the first-stage four-input differential amplifier (101) to maintain the stability of the output common-mode voltage.

[0016] The first-stage four-input differential amplifier (101) comprises: six NMOS transistors N1, N2, N3, N4, N5, N6, four PMOS transistors P1, P2, P3, P4, and a Miller capacitor C C , where N5 and N6 are tail current sources, N1, N2, N3, and N4 are input differential pair transistors used to achieve the difference between the input signal and the input reference voltage, and P1, P2, P3, and P4 are load transistors. Among them, the gate terminals of N1 and N4 are connected to the input differential signal, the gate terminals of N2 and N3 are connected to the input reference voltage, the drain terminal of N1 is connected to the drain terminals of N3, P1, and P3 and outputs the single-ended output voltage of the first-stage amplifier, the drain terminal of N4 is connected to the drain terminals of N2, P2, and P4 and outputs the other end output voltage of the first-stage amplifier, and the gate terminals of P1 and P2 are connected to the bias voltage VBP, the gate terminals of P2 and P4 are connected to the feedback voltage VCMFB, the gate terminals of N5 and N6 are connected to the bias voltage VBN, the drain terminal of N5 is connected to the source terminals of N1 and N2, the drain terminal of N6 is connected to the source terminals of N3 and N4, and the Miller capacitor C C The two ends of are connected to the feedback voltage VCMFB and the output voltage of the first stage amplifier respectively.

[0017] The second-stage pseudo differential amplifier (102) comprises: two NMOS transistors N7 and N8, and two PMOS transistors P5 and P6; wherein N7 is connected to the gate end and drain end of P5, and outputs the single-ended output voltage of the second-stage amplifier; N8 is connected to the gate end and drain end of P6, and outputs the output voltage of the other end of the second-stage amplifier. N7 and P5 complete the inverting amplification of the signal at one end, and N8 and P6 complete the inverting amplification of the signal at the other end, thereby amplifying the output signal of the first-stage four-input differential amplifier.

[0018] The common-mode feedback amplifier (103) comprises three NMOS transistors N9, N10, and N11, two PMOS transistors P7 and P8, and resistors R1 and R2; wherein R1 and R2 are connected in series, the other end of R1 is connected to the single-ended output voltage of the second-stage amplifier, the other end of R2 is connected to the other-end output voltage of the second-stage amplifier, the gate end of N9 is connected to the common-mode reference voltage, the gate end of N10 is connected to the series connection point of the resistors R1 and R2, the gate end and drain end of P7 are connected, and are also connected to the gate end of P8 and the drain end of N9, P8 is connected to the drain end of N10, the gate end of N11 is connected to the bias voltage, and the drain end of N11 is connected to the source ends of N9 and N10. R1 and R2 detect the output signal, N11 is the tail current source, N9 and N10 are input differential pair tubes used to compare the output common-mode signal with the ideal common-mode signal, and P7 and P8 act as current mirror load tubes to convert the output signal from dual-ended to single-ended, thereby feeding back to the load tube gate of the first-stage four-input differential amplifier to maintain the stability of the output common-mode voltage.

[0019] In the present invention, the first-stage and second-stage SAR ADCs use the same circuit structure, including a gate voltage bootstrap circuit (201), a binary sampling capacitor array (202), a dynamic comparator circuit (203), and a successive approximation digital logic circuit (204), such as Figure 2 shown; wherein:

[0020] The gate voltage bootstrap circuit (201) samples the input signal; the signal sampled by the gate voltage bootstrap circuit is loaded on the sampling capacitor array (202); the dynamic comparator circuit (203) compares the sampled value with the reference voltage; the comparison result controls the operation of the successive approximation digital logic circuit (204), causing the reference voltage of the capacitor plate to change sequentially, and ultimately obtaining the first-level digital code output and analog margin. Specifically:

[0021] The input terminal of the gate voltage bootstrap sampling circuit (201) is connected to the input signal, the output terminal thereof is connected to the top plate of the binary sampling capacitor array (202), the bottom plate of the binary sampling capacitor array (202) is connected to the reference voltage VRP or VRN, the input terminal of the dynamic comparator circuit (203) is connected to the top plate of the sampling capacitor array (202), and the output terminal thereof is connected to the successive approximation digital logic circuit (204). The successive approximation digital logic circuit (204) controls the bottom plate of the sampling capacitor array (202) to change in sequence according to the output result of the dynamic comparator (203), and finally obtains a digital code output and an analog margin.

[0022] In the present invention, the adaptive MUX, such as Figure 3As shown, the circuit includes a digital code value updating circuit (301), a digital code value comparison circuit (302), a special mode selection circuit (303) and a correct code value output circuit (304). The purpose of the circuit is to select one channel whose output code value is closest to the middle value 10000 from the quantization results of the first-stage SAR ADC of the four channels, and output the correct quantization result of the channel, wherein the digital code value updating circuit (301) updates the next code value according to the comparison result of the current position; the digital code value comparison circuit (302) compares the current digital code value with the digital code value of the same position of other channels and obtains a comparison result, and the comparison result is used for the digital code value updating circuit (301); the special mode selection circuit (303) corrects the special situation of the gain generated by the input buffer being too high or too low, and finally obtains the channel where the correct quantization result is located by combining it with the digital code value comparison circuit; the correct code value output circuit (304) selects the correct quantization result according to the result obtained by the special mode selection circuit (303). Specifically:

[0023] The digital code value updating circuit (301) comprises an XOR gate, a selector and an AND gate, and updates the next bit code value according to the comparison result of the current bit.

[0024] The digital code value comparison circuit (302) comprises a NOT gate, an AND gate, an OR gate and a NAND gate, and compares the digital code value of the current bit with the digital code value of the corresponding bit in other channels to obtain a comparison result, and the comparison result is used for the digital code value updating circuit (301).

[0025] The special mode selection circuit (303) includes a selector, an AND gate, and a NOT gate, which corrects the special situation where the gain generated by the input buffer is too high or too low, and combines it with the digital code value comparison circuit (302) to finally obtain the path where the correct quantization result is located.

[0026] The correct code value output circuit (304) includes an OR gate and a selector, and selects the correct quantization result according to the result obtained by the special mode selection circuit (303).

[0027] In the present invention, the open-loop RA, such as Figure 4 As shown, it includes: a first-stage fully differential amplifier (401), a second-stage pseudo-differential amplifier (402), a common-mode feedback amplifier (403) (including two stages), and a bias circuit (404); wherein:

[0028] The first-stage fully differential amplifier (401) and the second-stage pseudo differential amplifier (402) are cascaded to achieve 16-fold amplification of the first-stage SAR ADC analog margin; the first-stage common-mode feedback amplifier (403) ( Figure 4In (a), three transmission gate common mode switches are added to the traditional resistive common mode feedback. During the amplification phase, the common mode switches are closed, the output VXP / VXN and the resistive voltage divider VCMC1 are reset, and the output common mode is maintained at VCM. During the amplification phase, the switches are opened, and the resistive common mode feedback amplifier feeds back the voltage to the first stage fully differential amplifier (401) (gates of P3 and P4), so that the output VXP / VXN of the first stage fully differential amplifier (401) is maintained at VCM. The second stage common mode feedback amplifier (403) ( Figure 4 (b) is a traditional resistive common-mode feedback circuit, which feeds back the voltage to the second-stage pseudo-differential amplifier (402) (gates of N2, N4, P2 and P4), so that the output VOP / VON of the second-stage pseudo-differential amplifier (402) is maintained at VCM; the first-stage fully differential amplifier (401), the second-stage pseudo-differential amplifier (402) and the common-mode feedback amplifier (403) share the same bias circuit (404).

[0029] The foregoing generally describes the features and technical advantages of the present invention. The following uses a 150MS / s sampling rate, 14-bit resolution input segmented pipelined-SAR ADC as an example to more clearly illustrate the concept of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the open-loop input buffer.

[0031] Figure 2 Schematic diagram of a successive approximation analog-to-digital converter (SAR ADC).

[0032] Figure 3 Schematic diagram of adaptive digital selection logic circuit (MUX).

[0033] Figure 4 Schematic diagram of the open-loop margin amplifier (RA).

[0034] Figure 5 The working diagram of the input segmented two-stage Pipelined-SAR ADC example with a sampling rate of 150MS / s and a resolution of 14 bits ( Figure 5 In the example, the specific structures of Input Buffer, SAR ADC, MUX and RA are as follows: Figure 1 、 2 , 3, and 4. ).

[0035] In the figure, the numbers 101 are the first-stage four-input differential amplifier module, 102 are the second-stage pseudo-differential amplifier module, 103 are the common-mode feedback amplifier module, 201 are the gate voltage bootstrap circuit, 202 are the sampling capacitor array, 203 are the dynamic comparator circuit, 204 are the successive approximation digital logic circuit, 301 are the digital code value update circuit, 302 are the digital code value comparison circuit, 303 are the special mode selection circuit, 304 are the correct code value output circuit, 401 are the first-stage fully differential amplifier, 402 are the second-stage pseudo-differential amplifier, 403 are the common-mode feedback amplifier, and 404 are the bias circuit. DETAILED DESCRIPTION

[0036] The following, in conjunction with the accompanying drawings, further describes the input-segmented pipelined successive approximation analog-to-digital converter designed by the present invention. It is worth noting that the pipelined successive approximation analog-to-digital converter provided by the present invention can be implemented in many different ways with different specifications and performances. The following examples only provide a typical implementation circuit for the present invention and are intended only to illustrate the formation and use of the present invention and are not intended to limit the present invention.

[0037] The present invention provides an input segmented pipeline successive approximation analog-to-digital converter and its internal module circuit. An embodiment is a dual-channel input segmented pipeline successive approximation analog-to-digital converter with a sampling rate of 150MS / s and a 14-bit resolution. The ADC consists of two symmetrical channels A and B, and the front and back stages work in a pipeline manner. The specific implementation method is as follows: Figure 5 In this example, the process is TSMC 28nm, the power supply voltage is 0.9V, and the reference voltages of the four input buffers are Vrefp1 = 720 mV, Vrefn1 = 660 mV; Vrefp2 = 780 mV, Vrefn2 = 600 mV; Vrefp3 = 840 mV, Vrefn3 = 540 mV; Vrefp4 = 900 mV, Vrefn4 = 480 mV; the reference voltages of the SAR ADC are VRP = 800 mV and VRN = 200 mV.

[0038] Since channels A and B work in exactly the same way and have identical circuit connections, the following explanation uses channel A as an example:

[0039] The input signal is compared with four different reference voltages, generating four different transfer curves through four input buffers. Each curve is quantized by a 5-bit SAR ADC to produce four 5-bit digital code values. The MUX selects the correct 5-bit quantization result and its corresponding path from these four digital code values.

[0040] After quantization by the first-stage ADC, the corresponding residual is generated with 5 bits of precision. This is amplified 16 times by the RA, creating one bit of inter-stage redundancy to reduce the ADC's bit error rate. The amplifier's output signal is sampled and quantized by the second-stage ADC, generating an 8-bit output code, which includes one bit of intra-stage redundancy to reduce bit errors.

[0041] The working timing relationship of a single channel is as follows Figure 5 As shown in (b), the Φ1 phase is the sampling phase of the first-stage SAR ADC, during which the first-stage SAR ADC samples the analog signal amplified by the input buffer. The ΦR phase is the reset phase of the RA, during which the RA output voltage is at the common-mode voltage. The Φ2 phase, opposite to the ΦR phase, is the sampling phase of the second-stage SAR ADC, during which the RA performs residual amplification and the second-stage SAR ADC performs sampling. Channels AB sample simultaneously and operate synchronously. Because the preceding and following stages within each channel operate in a pipelined manner, high speed is achieved.

[0042] Although the contents and advantages of the present invention have been disclosed in detail as above, it must be noted that the scope of the present invention is not limited to the specific embodiments such as the methods and steps described in the specification. Without departing from the spirit and scope of the present invention, any person skilled in the art can make many variations and modifications based on the contents disclosed by the present invention, which should also be regarded as the scope of protection of the present invention.

Claims

1. An input segmented pipeline successive approximation analog-to-digital converter, characterized in that: The overall circuit consists of two symmetrical channels, each of which includes four open-loop input buffers (InputBuffers) with different input reference voltages, four first-stage successive approximation analog-to-digital converters (SAR ADCs), an adaptive digital selection logic circuit (MUX), an open-loop margin amplifier (RA), and a second-stage successive approximation analog-to-digital converter (SAR ADC). The input buffers amplify the input signal and divide it into four different quantization intervals. Four first-stage successive approximation analog-to-digital converters are used to convert the analog signals of these four intervals into digital code values. The adaptive digital selection logic circuit (MUX) selects the correct quantization result from the four groups of digital code values and transmits the corresponding analog margin to the open-loop margin amplifier. The open-loop margin amplifier amplifies the analog margin signal, and the amplified signal is sampled and quantized by the second-stage successive approximation analog-to-digital converter to generate a second-stage quantized digital code. The two stages in each channel operate in a pipeline manner, and the digital code values of the first and second stages are synchronously processed and output. The four open-loop input buffers with different input reference voltages compare the input signal with four different sets of input reference voltages to amplify the input signal to four different intervals; The four first-stage SAR ADCs simultaneously perform top-plate sampling and quantization on the four groups of input signals after amplification and segmentation, and generate four groups of first-stage quantized digital codes and quantized analog residuals; The adaptive digital selection logic circuit (MUX) compares the four groups of first-level quantization digital codes to obtain a correct group of first-level quantization digital codes, and controls the transmission of the analog margin corresponding to the digital code; The open loop RA amplifies the analog residual signal, and the amplified signal is sampled and quantized by the second stage SAR ADC to generate a second stage quantized digital code; The two-stage SAR ADC works in a pipeline manner, and the digital code values of the first and second stages are synchronously processed and output.

2. The input segmented pipelined successive approximation analog-to-digital converter according to claim 1, wherein: The four open-loop input buffers with different input reference voltages have a circuit comprising a first-stage four-input differential amplifier (101), a second-stage pseudo-differential amplifier (102) and a common-mode feedback amplifier (103); wherein the first-stage four-input differential amplifier (101) performs a differential operation on an input analog signal and an input reference voltage; the second-stage pseudo-differential amplifier (102) amplifies the differential signal; and the common-mode feedback amplifier (103) performs a differential operation on an output common-mode voltage and an ideal common-mode voltage and feeds the amplified voltage back to the first-stage four-input differential amplifier (101) to maintain the stability of the output common-mode voltage.

3. The input segmented pipelined successive approximation analog-to-digital converter according to claim 2, wherein: The first-stage four-input differential amplifier (101) comprises: six NMOS transistors N1, N2, N3, N4, N5, N6, four PMOS transistors P1, P2, P3, P4, and a Miller capacitor C C , where N5 and N6 are tail current sources, N1, N2, N3, and N4 are input differential pair transistors used to achieve the difference between the input signal and the input reference voltage, and P1, P2, P3, and P4 are load transistors; where the gate terminals of N1 and N4 are connected to the input differential signal, the gate terminals of N2 and N3 are connected to the input reference voltage, the drain terminal of N1 is connected to the drain terminals of N3, P1, and P3 and outputs the single-ended output voltage of the first-stage amplifier, the drain terminal of N4 is connected to the drain terminals of N2, P2, and P4 and outputs the other end output voltage of the first-stage amplifier, and the gate terminals of P1 and P2 are connected to the bias voltage VBP, the gate terminals of P3 and P4 are connected to the feedback voltage VCMFB, the gate terminals of N5 and N6 are connected to the bias voltage VBN, the drain terminal of N5 is connected to the source terminals of N1 and N2, the drain terminal of N6 is connected to the source terminals of N3 and N4, and the Miller capacitor C C The two ends of are connected to the feedback voltage VCMFB and the output voltage of the first stage amplifier respectively.

4. The input segmented pipelined successive approximation analog-to-digital converter according to claim 2, wherein: The second-stage pseudo differential amplifier (102) comprises: two NMOS transistors N7 and N8, and two PMOS transistors P5 and P6; wherein N7 is connected to the gate end and the drain end of P5, and outputs the single-ended output voltage of the second-stage amplifier; N8 is connected to the gate end and the drain end of P6, and outputs the output voltage of the other end of the second-stage amplifier; N7 and P5 complete the inverting amplification of the signal at one end, and N8 and P6 complete the inverting amplification of the signal at the other end, thereby amplifying the output signal of the first-stage four-input differential amplifier.

5. The input segmented pipelined successive approximation analog-to-digital converter according to claim 2, wherein: The common-mode feedback amplifier (103) comprises three NMOS transistors N9, N10, and N11, two PMOS transistors P7 and P8, and resistors R1 and R2; wherein R1 and R2 are connected in series, the other end of R1 is connected to the single-ended output voltage of the second-stage amplifier, the other end of R2 is connected to the other end output voltage of the second-stage amplifier, the gate end of N9 is connected to the common-mode reference voltage, the gate end of N10 is connected to the series connection point of resistors R1 and R2, the gate end and drain end of P7 are connected, and are connected to the gate end of P8 and the drain end of N9. The drain terminals of P8 and N10 are connected, the gate terminal of N11 is connected to the bias voltage, and the drain terminal of N11 is connected to the source terminals of N9 and N10; R1 and R2 detect the output signal, N11 is a tail current source, N9 and N10 are input differential pair tubes used to realize the comparison between the output common-mode signal and the ideal common-mode signal, and P7 and P8 act as current mirror load tubes to convert the output signal from dual-ended to single-ended, thereby feeding back to the load tube gate of the first-stage four-input differential amplifier to maintain the stability of the output common-mode voltage.

6. The input segmented pipelined successive approximation analog-to-digital converter according to claim 1, wherein: The first-stage SAR ADC and the second-stage SAR ADC adopt the same circuit structure, including a gate voltage bootstrap circuit (201), a binary sampling capacitor array (202), a dynamic comparator circuit (203) and a successive approximation digital logic circuit (204), wherein: The gate voltage bootstrap circuit (201) samples the input signal; the signal sampled by the gate voltage bootstrap circuit is loaded on the sampling capacitor array (202); the dynamic comparator circuit (203) compares the sampled value with the reference voltage; the comparison result controls the operation of the successive approximation digital logic circuit (204), causing the reference voltage of the capacitor plate to change in sequence, and finally obtaining the first-level digital code output and analog margin; specifically: The input terminal of the gate voltage bootstrap sampling circuit (201) is connected to the input signal, the output terminal thereof is connected to the top plate of the binary sampling capacitor array (202), the bottom plate of the binary sampling capacitor array (202) is connected to the reference voltage VRP or VRN, the input terminal of the dynamic comparator circuit (203) is connected to the top plate of the sampling capacitor array (202), and the output terminal thereof is connected to the successive approximation digital logic circuit (204). The successive approximation digital logic circuit (204) controls the bottom plate of the sampling capacitor array (202) to change in sequence according to the output result of the dynamic comparator (203), and finally obtains a digital code output and an analog margin.

7. The input segmented pipelined successive approximation analog-to-digital converter according to claim 1, wherein: The adaptive digital selection logic circuit comprises a digital code value updating circuit (301), a digital code value comparison circuit (302), a special mode selection circuit (303) and a correct code value output circuit (304); the circuit selects one path whose output code value is closest to the middle value 10000 from the quantization results of the four first-stage SAR ADCs, and outputs the correct quantization result of the path; wherein the digital code value updating circuit (301) updates the next code value according to the comparison result of the current bit; the digital code value comparison circuit (302) compares the current digital code value with the digital code value of the same bit of other paths and obtains a comparison result, and the comparison result is used for the digital code value updating circuit (301); the special mode selection circuit (303) corrects the special situation of the gain generated by the input buffer being too high or too low, and finally obtains the path where the correct quantization result is located by combining the result with the digital code value comparison circuit; the correct code value output circuit (304) selects the correct quantization result according to the result obtained by the special mode selection circuit (303).

8. The input segmented pipelined successive approximation analog-to-digital converter according to claim 1, wherein: The open-loop margin amplifier comprises: a first-stage fully differential amplifier (401), a second-stage pseudo-differential amplifier (402), a two-stage common-mode feedback amplifier (403), and a bias circuit (404); wherein: The first-stage fully differential amplifier (401) and the second-stage pseudo differential amplifier (402) are cascaded to achieve 16-fold amplification of the first-stage SAR ADC analog margin; the first-stage common-mode feedback amplifier (403) adds three transmission gate common-mode switches on the basis of traditional resistive common-mode feedback, and the common-mode switches are closed outside the amplification phase to output VXP / VXN. The resistor voltage dividing point VCMC1 is reset, and the output common mode is maintained at VCM; in the amplification stage, the switch is disconnected, and the voltage is fed back to the first-stage fully differential amplifier (401) according to the resistor common mode feedback amplifier, so that the output VXP / VXN of the first-stage fully differential amplifier (401) is maintained at VCM; the second-stage common mode feedback amplifier (403) is a resistor common mode feedback circuit, which feeds back the voltage to the second-stage pseudo differential amplifier (402), so that the output VOP / VON of the second-stage pseudo differential amplifier (402) is maintained at VCM; the first-stage fully differential amplifier (401), the second-stage pseudo differential amplifier (402) and the common mode feedback amplifier (403) share the same bias circuit (404).

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