Transceiver and transceiver correction method

Abstract

A transceiver includes a correction signal generating unit, a transmitting unit, a receiving unit, and a control unit. The correction signal generating unit generates a test signal to the transmitting unit in a phase correction mode. The receiving unit generates a digital receive signal. The control unit calculates a phase difference between the digital receive signal and a known reference phase and selectively adjusts the transmitting unit or the receiving unit accordingly. A transceiver correction method is also disclosed.

Description

Technical Field

[0001] This application relates to communication devices, and more particularly to a transceiver and a transceiver calibration method. Background Technology

[0002] Wireless multi-input multi-output (MIMO) systems are becoming increasingly popular, and related applications are also increasing, such as indoor positioning systems and beamforming technology. The phase information of each transceiver plays an important role in these applications. Only by obtaining the correct phase difference between the transceivers can the correct channel information be estimated. Summary of the Invention

[0003] This application provides a transceiver, including: a correction signal generation unit, which generates a test signal to a transmission unit in phase correction mode; the transmission unit includes: a digital-to-analog converter, used to generate an analog test signal based on the test signal; a first IQ clock generator, used to generate a first clock and a second clock based on a reference clock, wherein the first clock and the second clock have the same frequency and a phase difference of 90 degrees; a fixed-phase divider, used to generate a third clock based on the reference clock, wherein the phase delay caused by the fixed-phase divider is fixed; and an upsampling unit, used to upscale the analog test signal into an upscaled signal based on the first clock or the third clock; and a receiving unit, in phase correction mode, the receiving unit transmits a signal to a transmission unit. The receiving unit is wired to the transmitting unit and includes: a second IQ clock generator for generating a fourth clock and a fifth clock based on the reference clock, wherein the fourth clock and the fifth clock have the same frequency and a phase difference of 90 degrees; a down-conversion unit for generating a down-conversion signal based on the up-conversion signal and the fourth clock; an analog-to-digital converter for generating a digital received signal based on the down-conversion signal; and a control unit for calculating the phase difference between the digital received signal and a known reference phase and selectively adjusting the first IQ clock generator to change the phase of the first clock and the second clock, or selectively adjusting the second IQ clock generator to change the phase of the fourth clock and the fifth clock.

[0004] This application provides a transceiver calibration method, comprising: generating a test signal in a phase correction mode; generating an analog test signal based on the test signal; generating a first clock and a second clock based on a reference clock, wherein the first clock and the second clock have the same frequency and a phase difference of 90 degrees; generating a third clock based on the reference clock using a fixed-phase divider, wherein the phase delay caused by the fixed-phase divider is fixed; upsampling the analog test signal into an up-frequency signal based on the first clock or the third clock; generating a fourth clock and a fifth clock based on the reference clock, wherein the fourth clock and the fifth clock have the same frequency and a phase difference of 90 degrees; generating a down-frequency signal based on the up-frequency signal and the fourth clock; generating a digital received signal based on the down-frequency signal; and calculating the phase difference between the digital received signal and a known reference phase and selectively changing the phase of the first clock and the second clock, or selectively changing the phase of the fourth clock and the fifth clock accordingly.

[0005] The transceiver and transceiver calibration method of this application are used to ensure that the phase state of each transceiver in the MIMO system remains consistent after each power-on or reset. Attached Figure Description

[0006] A comprehensive understanding of various aspects of this disclosure can be best achieved by reading the following embodiments and accompanying drawings. It should be noted that, in accordance with standard practice in the art, the various features in the figures are not drawn to scale. In fact, the dimensions of certain features may be intentionally enlarged or reduced for clarity of description.

[0007] Figure 1 This is a schematic diagram of an embodiment of the transceiver of this application.

[0008] Figure 2 This is a schematic diagram of an embodiment of an IQ clock generator.

[0009] Figure 3 This is the timing diagram for the IQ clock generator.

[0010] Figure 4 The timing diagram of the IQ clock generator when the clock gating unit is in operation. Detailed Implementation

[0011] Figure 1 This is a schematic diagram of an embodiment of the transceiver of this application. For simplicity, the transceiver 100 includes only a pair of transmitting units 111 and receiving units 115. Figure 1 Only the elements in the transmitting unit 111 and receiving unit 115 that are used to illustrate the phase correction process of this application are shown, such as... Figure 1The antennas of the transmitting unit 111 and the receiving unit 115 are not shown. The wireless MIMO system includes more than one transceiver 100. The transmitting unit 111 includes an IQ clock generator 104, which generates an in-phase clock I+ and a quadrature clock Q+ based on a reference clock CLK_REF in normal mode for the in-phase transmission path (including a digital-to-analog converter 1021 and an upsampling unit 1061) and the quadrature transmission path (including a digital-to-analog converter 1022 and an upsampling unit 1062), respectively. Similarly, the receiving unit 115 includes an IQ clock generator 116, which generates an in-phase clock I+ and a quadrature clock Q+ based on a reference clock CLK_REF in normal mode for the in-phase receiving path (including a downsampling unit 1141 and an analog-to-digital converter 1181) and the quadrature receiving path (including a downsampling unit 1142 and an analog-to-digital converter 1182), respectively.

[0012] The IQ clock generators 104 and 116 have the same construction. They are used to divide the reference clock CLK_REF by two and generate in-phase clocks I+ and Q+ with a frequency of 1 / 2 that is orthogonal to each other. Figure 2 The diagram illustrates an embodiment of the IQ clock generator 104 / 116 (but is not limited thereto). Figure 3 This is the timing diagram for the IQ clock generator 104 / 116. The IQ clock generator 104 / 116 includes flip-flops 202 and 204, both of which have an enable terminal E, a clock input terminal CLK, a positive input terminal D, and a negative input terminal. Positive output terminal Q and negative output terminal The IQ clock generator 104 / 116 also includes a clock gating unit 206 and an inverter 208. The clock gating unit 206 is used to selectively gate the reference clock CLK according to the control unit 120, and generate a gated clock GCLK_REF to the clock input CLK of the flip-flop 202. The inverter 208 is coupled between the clock gating unit 206 and the clock input CLK of the flip-flop 204. Figure 2 As shown, the output of the positive output terminal Q of flip-flop 202 serves as the in-phase clock I+, and the output of the positive output terminal Q of flip-flop 204 serves as the quadrature clock Q+ (these can be interchanged in other embodiments). The positive output terminal Q of flip-flop 204 is coupled to the negative input terminal of flip-flop 202. The negative output terminal of flip-flop 204 The positive input terminal D of flip-flop 202 is coupled to the positive input terminal D of flip-flop 204; the positive output terminal Q of flip-flop 202 is coupled to the positive input terminal D of flip-flop 204; the negative output terminal of flip-flop 202 is coupled to the positive input terminal D of flip-flop 204. Coupled to the negative input of flip-flop 204 The enable terminal E of flip-flops 202 and 204 is used to receive the enable signal EN.

[0013] When the clock gating unit 206 does not gate the reference clock CLK_REF, the enable signal EN will cause the IQ clock generator 104 / 116 to start operating each time the transceiver 100 is powered on or reset. Figure 3 As shown, due to the non-ideal reference clock CLK_REF having a certain degree of jitter, the signal EN may result in two startup states, 302 and 304. Consequently, the phase difference between the in-phase clock I+ in startup state 302 and the in-phase clock I+ in startup state 304 is 180 degrees, and the same applies to clocks I-, Q+, and Q-. In other words, in a MIMO system, after each power-on or reset, the in-phase clock I+ of the transmitting unit 111 and the receiving unit 115 in the same transceiver 100 may belong to startup state 302 or 304, respectively, and the in-phase clock I+ of the transmitting unit 111 and the receiving unit 115 in different transceivers 100 may also belong to startup state 302 or 304.

[0014] Therefore, after each power-on or reset, the transceiver 100 enters a phase correction mode before entering the normal mode, which sequentially includes a receiving unit correction stage and a transmitting unit correction stage. In phase correction mode, the transceiver 100 uses the correction signal generation unit 101 to generate a test signal St to the transmitting unit 111. After passing through the transmitting unit 111 and the receiving unit 115, the signal returns to the control unit 120. The control unit 120 then determines whether to adjust the clock gating unit 206 of the IQ clock generators 104 / 116 separately so that both IQ clock generators 104 and 116 are fixed in the startup state 302. It should be noted that both IQ clock generators 104 and 116 can also be fixed in the startup state 304.

[0015] The function of the clock gating unit 206 is explained below. Figure 4 When the signal S2 / S3 from the control unit 120 changes from low to high for one period T of the reference clock CLK_REF, the clock gating unit 206 will correspondingly gating the reference clock CLK_REF for one period T, so that the output gated clock GCLK remains at a low level for one period T. In this way, the phase of the in-phase clocks I+, I-, Q+, and Q- of the IQ clock generators 104 / 116 is delayed by 180 degrees.

[0016] Please return Figure 1In phase correction mode, only the in-phase transmission path and in-phase reception path are needed to correct the in-phase signal I+. Since the phase difference between the quadrature signal Q+ and the in-phase signal I+ is fixed at 90 degrees, correcting the in-phase signal I+ is essentially equivalent to correcting the quadrature signal Q+, therefore the quadrature transmission path and quadrature reception path are not used. In some embodiments, the operation can be reversed, that is, the quadrature transmission path and quadrature reception path are used to correct the quadrature signal Q+ without needing to correct the in-phase signal I+.

[0017] Since the phase delays of the clocks generated by IQ clock generators 104 and 116 are uncertain, in phase correction mode, the receiving unit correction stage is entered first. At this time, the upscalorie converter 1061 of the transmitting unit 111 uses the fixed-phase clock ckf of the fixed-phase divider 105 to replace the in-phase signal I+, so as to focus on correcting the IQ clock generator 116 of the receiving unit 115. The phase delay of the fixed-phase divider 105 is fixed. After the correction of the IQ clock generator 116 is completed, the transmitting unit correction stage is entered, and only then is the IQ clock generator 104 of the transmitting unit 111 corrected.

[0018] Specifically, both the fixed-phase divider 105 and the IQ clock generator 104 can generate a clock with a frequency half that of the reference clock CLK_REF. The difference is that the fixed-phase divider 105 is only used in phase correction mode, so its bandwidth does not need to be very wide; it only needs to be able to operate within a relatively narrow, specific frequency band. The key is to ensure that the fixed-phase divider 105 does not randomly output two clocks with opposite phases, unlike the IQ clock generator 104. In other words, the phase delay of the fixed-phase divider 105 is fixed. That is, in a MIMO system, although the fixed-phase dividers 105 of each transceiver 100 are independent, after each power-on or reset, the phase of the fixed-phase clock ckf generated by the fixed-phase dividers 105 of each transceiver 100 is the same. The fixed-phase divider 105 can be, for example, a Miller divider.

[0019] During the receiving unit calibration phase, the digital-to-analog converter 1021 generates an analog test signal Sa based on the test signal St. The control unit 120 uses signal S1 to control the multiplexer 103 to couple the reference signal CLK_REF to the input of the fixed-phase divider 105, and uses signal S1 to control the multiplexer 107 to couple the output of the fixed-phase divider 105 to the upscaler 1061, causing the upscaler 1061 to upscale the analog test signal Sa according to the fixed-phase clock ckf to generate the upscaled signal Su. At this time, the IQ clock generator 104 does not receive the reference signal CLK_REF, so the upscaler 1062 of the quadrature transmission path will not operate. Simultaneously, in phase correction mode, no input signal is given to the digital-to-analog converter 1022 of the quadrature path. Therefore, the combiner 108 generates a combined signal Sm based only on the upscaled signal Su. The combined signal Sm is amplified by amplifier 110 to generate an amplified signal SAP, which is then fed back to the gain unit 112 of the receiving unit 115 via a wired path and outputs a gain signal Sg. The wired path can be implemented either within the chip where the transceiver 100 is located, or it needs to pass through wires on a circuit board outside the chip.

[0020] The down-conversion unit 1141 reduces the gain signal Sg to the base frequency based on the in-phase clock I+ generated by the IQ clock generator 116, generating a down-conversion signal Sd. The analog-to-digital converter 1181 converts the down-conversion signal Sd from an analog signal to a digital received signal Sda and sends it to the control unit 120. The control unit 120 calculates the phase difference Pd1 between the digital received signal Sda and the known reference phase. Specifically, the control unit 120 performs a Fourier transform on the digital received signal Sda to obtain the real and imaginary parts of the digital received signal Sda, and compares them with the real and imaginary parts of the known reference phase to obtain the phase difference Pd1. The phase difference Pd1 between the digital received signal Sda and the known reference phase may have two values ​​that differ by 180 degrees due to the IQ clock generator 116. In this embodiment, for ease of phase comparison, the test signal St is a monotonic signal. If 0 degrees ≤ phase difference Pd1 < 180 degrees, the control unit 120 generates signal S3 to control the clock gating unit 206 of the IQ clock generator 116 to not gate the reference clock CLK_REF; if -180 degrees ≤ phase difference Pd1 < 0 degrees, the control unit 120 generates signal S3 to control the clock gating unit 206 of the IQ clock generator 116 to gate the reference clock CLK_REF for one period T, so that 0 degrees ≤ phase difference Pd1 < 180 degrees. The above process can also be modified by adjusting the phase difference Pd1 to -180 degrees ≤ phase difference Pd1 < 0 degrees, as long as the phase of the clock I+ generated by the IQ clock generator 116 of each transceiver 100 in the MIMO system is the same and known after each power-on or reset.

[0021] Next, the correction process moves from the receiving unit correction stage to the transmitting unit correction stage. The digital-to-analog converter 1021 generates an analog test signal Sa based on the test signal St. The control unit 120 uses signal S1 to control multiplexer 103 to couple the reference signal CLK_REF to the input of IQ clock generator 104, and uses signal S1 to control multiplexer 107 to couple the output of IQ clock generator 104 to upscaler 1061, causing upscaler 1061 to upscale the analog test signal Sa based on clock I+ to generate an upscaled signal Su. In phase correction mode, no input signal is provided to the digital-to-analog converter 1022 via a quadrature path; therefore, combiner 108 generates a combined signal Sm based solely on the upscaled signal Su. The combined signal Sm is amplified by amplifier 110 to generate an amplified signal SAP, which is then fed back to the gain unit 112 of receiving unit 115 via a wired path and outputs a gain signal Sg.

[0022] Down-converter 1141 reduces the gain signal Sg to the base frequency based on the in-phase clock I+ generated by IQ clock generator 116, generating a down-converted signal Sd. Analog-to-digital converter 1181 converts the down-converted signal Sd from an analog signal to a digital received signal Sda and sends it to control unit 120. Control unit 120 calculates the phase difference Pd2 between the digital received signal Sda and the known reference phase. Since the phase delay of IQ clock generator 116 has been corrected to a known value during the receiving unit correction stage, the uncertainty of phase difference Pd2 all originates from IQ clock generator 104. If 0 degrees ≤ phase difference Pd2 < 180 degrees, the control unit 120 generates signal S2 to control the clock gating unit 206 of the IQ clock generator 104 to not gate the reference clock CLK_REF; if -180 degrees ≤ phase difference Pd2 < 0 degrees, the control unit 120 generates signal S2 to control the clock gating unit 206 of the IQ clock generator 104 to gate the reference clock CLK_REF for one period T, so that 0 degrees ≤ phase difference Pd2 < 180 degrees. The above process can also be changed to adjust the phase difference Pd2 to 180 degrees ≤ phase difference Pd2 < 0 degrees, as long as the phase of the clock I+ generated by the IQ clock generator 116 of each transceiver 100 in the MIMO system is the same and known. At this time, the transmission unit correction stage is completed, and the transceiver 100 can leave the phase correction mode and enter the normal mode.

[0023] The foregoing description briefly outlines the features of certain embodiments of this application, enabling those skilled in the art to gain a more comprehensive understanding of the various aspects of this application. Those skilled in the art should understand that they can readily utilize this application as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments still fall within the spirit and scope of this application, and various changes, substitutions, and improvements can be made without departing from the spirit and scope of this application.

[0024] Explanation of reference numerals in the attached figures:

[0025] 100: Transceiver

[0026] 103, 107: Multiplexers

[0027] 104, 116: IQ clock generator:

[0028] 105: Fixed-phase frequency divider

[0029] 108: Combiner

[0030] 110: Amplifier

[0031] 111: Transmission Unit

[0032] 112: Gain Unit

[0033] 115: Receiving Unit

[0034] 120: Control Unit

[0035] 202, 204: Triggers

[0036] 206: Clock Gating Unit

[0037] 208: Inverter

[0038] 302, 304: Startup status

[0039] 1021, 1022: Digital-to-Analog Converters

[0040] 1061, 1062: Up-frequency converter

[0041] 1141, 1142: Frequency downconverter

[0042] 1181, 1182: Analog-to-digital converter

[0043] ckf: Fixed-phase clock

[0044] CLK_REF: Reference clock

[0045] EN: Enable signal

[0046] GCLK_REF: Gated clock

[0047] I-, Q+, Q-: Clock

[0048] I+: In-phase clock

[0049] Q+: Quadrature clock

[0050] S1, S2, S3: Signals

[0051] Sa: Simulated test signal

[0052] Sap: Amplified signal

[0053] Sd: Down-frequency signal

[0054] Sda: Digital signal reception

[0055] Sg: Gain signal

[0056] Sm: Combined signal

[0057] St: Test signal

[0058] Su: Up-frequency signal

Claims

1. A transceiver, comprising: The correction signal generation unit generates a test signal to the transmission unit in phase correction mode; The transmission unit includes: A digital-to-analog converter is used to generate an analog test signal based on the test signal; A first IQ clock generator is used to generate a first clock and a second clock based on a reference clock, wherein the first clock and the second clock have the same frequency and a phase difference of 90 degrees. A fixed-phase divider is used to generate a third clock based on the reference clock, and the phase delay caused by the fixed-phase divider is fixed. as well as A frequency upsampling unit is used to upsampling the analog test signal into an upsampling signal based on the first clock or the third clock. In the phase correction mode, the receiving unit is wired to the transmitting unit, and the receiving unit includes: The second IQ clock generator is used to generate a fourth clock and a fifth clock based on the reference clock, wherein the fourth clock and the fifth clock have the same frequency and a phase difference of 90 degrees. as well as A frequency reducer is used to generate a frequency reduction signal based on the frequency up signal and the fourth clock. An analog-to-digital converter is used to generate a digital received signal based on the down-frequency signal; as well as The control unit is configured to calculate the phase difference between the digital received signal and a known reference phase and accordingly selectively adjust the first IQ clock generator to change the phase of the first clock and the second clock, or selectively adjust the second IQ clock generator to change the phase of the fourth clock and the fifth clock.

2. The transceiver of claim 1, wherein the first IQ clock generator comprises: The first flip-flop has a first clock input, a first positive input, a first negative input, a first positive output, and a first negative output. The second flip-flop has a second clock input, a second positive input, a second negative input, a second positive output, and a second negative output, wherein the second positive input is coupled to the first positive output, the second negative input is coupled to the first negative output, the second positive output is coupled to the first positive input, and the second negative output is coupled to the first positive input. The first clock gating unit is used to selectively gating the reference clock according to the control of the control unit, and to generate a first gating clock to the first clock input terminal; as well as An inverter is coupled between the first clock gating unit and the second clock input. One of the first positive output terminal and the second positive output terminal outputs the first clock, and the other of the first positive output terminal and the second positive output terminal outputs the second clock.

3. The transceiver of claim 2, wherein the second IQ clock generator comprises: The third flip-flop has a third clock input, a third positive input, a third negative input, a third positive output, and a third negative output. The fourth flip-flop has a fourth clock input, a fourth positive input, a fourth negative input, a fourth positive output, and a fourth negative output, wherein the fourth positive input is coupled to the second positive output, the fourth negative input is coupled to the second negative output, the fourth positive output is coupled to the second positive input, and the fourth negative output is coupled to the second positive input. The second clock gating unit is used to selectively gating the reference clock according to the control of the control unit, and to generate a second gating clock to the third clock input terminal; as well as An inverter is coupled between the second clock gating unit and the fourth clock input. The third positive output terminal and the fourth positive output terminal output the fourth clock, and the other of the third positive output terminal and the fourth positive output terminal output the fifth clock.

4. The transceiver as claimed in claim 3, wherein the phase correction mode includes a receiving unit correction stage and a transmitting unit correction stage, wherein in the receiving unit correction stage, the control unit controls the upsampling unit to generate the upsampling signal according to the third clock, and performs a Fourier transform on the digital received signal to obtain the real part and imaginary part of the digital received signal, and calculates the phase difference between the digital received signal and the known reference phase based on the real part and imaginary part of the digital received signal.

5. The transceiver of claim 4, wherein during the receiving unit correction phase, when the phase difference between the digital received signal and the known reference phase is greater than or equal to 0 degrees and less than 180 degrees, the control unit controls the second clock gating unit of the second IQ clock generator not to gate the reference clock; and when the phase difference between the digital received signal and the known reference phase is greater than or equal to -180 degrees and less than 0 degrees, the control unit controls the second clock gating unit of the second IQ clock generator to gate the reference clock for one cycle of the reference clock, so that the phase difference between the digital received signal and the known reference phase becomes greater than or equal to 0 degrees and less than 180 degrees.

6. The transceiver of claim 5, wherein in the transmission unit correction phase following the receiving unit correction phase, the control unit controls the upsampling unit to generate the upsampling signal according to the first clock, and performs a Fourier transform on the digital received signal to obtain the real and imaginary parts of the digital received signal, and calculates the phase difference between the digital received signal and the known reference phase based on the real and imaginary parts of the digital received signal.

7. The transceiver of claim 6, wherein during the transmission unit correction phase, when the phase difference between the digital received signal and the known reference phase is greater than or equal to 0 degrees and less than 180 degrees, the control unit controls the first clock gating unit of the first IQ clock generator not to gate the reference clock; and when the phase difference between the digital received signal and the known reference phase is greater than or equal to -180 degrees and less than 0 degrees, the control unit controls the first clock gating unit of the first IQ clock generator to gate the reference clock for one cycle of the reference clock, so that the phase difference between the digital received signal and the known reference phase becomes greater than or equal to 0 degrees and less than 180 degrees.

8. The transceiver of claim 1, wherein the transmitting unit further comprises a selection switch, includes an input terminal, a first output terminal, and a second output terminal, the input terminal being used to receive the reference clock, the first output terminal being coupled to the fixed-phase divider, the second output terminal being coupled to the first IQ clock generator, wherein when the control unit controls the upscalorie to upscale the analog test signal to the upscaled signal according to the first clock, the input terminal is coupled to the second output terminal; and when the control unit controls the upscalorie to upscale the analog test signal to the upscaled signal according to the third clock, the input terminal is coupled to the first output terminal.

9. The transceiver of claim 1, wherein the fixed-phase divider is a Miller divider.

10. A transceiver calibration method, comprising: In phase correction mode, a test signal is generated; A simulated test signal is generated based on the test signal; A first clock and a second clock are generated based on a reference clock, wherein the first clock and the second clock have the same frequency and a phase difference of 90 degrees. A third clock is generated based on the reference clock using a fixed-phase divider, wherein the phase delay caused by the fixed-phase divider is fixed. The analog test signal is up-frequency converted into an up-frequency signal based on the first clock or the third clock. A fourth clock and a fifth clock are generated based on the reference clock, wherein the fourth clock and the fifth clock have the same frequency and a phase difference of 90 degrees. A down-frequency signal is generated based on the up-frequency signal and the fourth clock. A digital received signal is generated based on the down-frequency signal; as well as Calculate the phase difference between the digital received signal and a known reference phase, and accordingly selectively change the phases of the first clock and the second clock, or selectively change the phases of the fourth clock and the fifth clock.

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