Video decoder and video decoding method thereof

Abstract

A video decoder has a plurality of processing circuits, including a first processing circuit and a second processing circuit. The first processing circuit performs a first decoding process on a current coding block according to reconstructed neighboring samples, and has a local neighboring buffer for buffering the reconstructed neighboring samples used by the first decoding process. The second processing circuit applies a second decoding process to the current coding block according to at least a portion of the reconstructed neighboring samples obtained from the local neighboring buffer, wherein the second decoding process is different from the first decoding process.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to video decoder design, and more particularly, to a video decoder having hardware shared between different decoding circuits (e.g., intra prediction circuit and chroma scaling circuit) and a related video decoding method. BACKGROUND

[0002] The Versatile Video Coding (VVC) standard (also known as H.266 standard) is the latest video coding standard. Compared with the previous High Efficiency Video Coding (HEVC) standard (also known as H.265 standard), the main goal of the new VVC standard is to significantly improve the compression capability. At the same time, VVC includes design features that make it suitable for a wide range of video applications. Like the HEVC standard, the VVC standard includes intra prediction, inter prediction, reconstruction, loop filter, etc. Compared with the HEVC standard, the VVC standard introduces many new coding tools. For example, Luma mapping with chroma scaling (LMCS) is a new tool introduced in VVC, which performs both luma mapping of the luma prediction signal in inter prediction mode and chroma scaling of the inverse-transformed and inverse-quantized residual. In the traditional VVC / H.266 video decoder design, both the intra prediction circuit and the chroma scaling circuit obtain the required neighboring samples from an external frame-level buffer (e.g., off-chip Dynamic Random Access Memory (DRAM)), and each of the intra prediction circuit and the chroma scaling circuit has its own calculation function. Therefore, an innovative VVC / H.266 video decoder design is needed to share hardware between different decoding circuits (e.g., intra prediction circuit and chroma scaling circuit). SUMMARY

[0003] It is an object of the present disclosure to provide a video decoder having hardware shared between different decoding circuits (e.g., intra prediction circuit and chroma scaling circuit) and a related video decoding method.

[0004] According to a first aspect of the present application, an exemplary video decoder is disclosed. The exemplary video decoder has a plurality of processing circuits including a first processing circuit and a second processing circuit. The first processing circuit is arranged to apply a first decoding process to a current coding block according to reconstructed neighboring samples. The first processing circuit includes a local neighboring buffer arranged to buffer the reconstructed neighboring samples used by the first decoding process. The second processing circuit is arranged to apply a second decoding process to the current coding block according to at least a portion of the reconstructed neighboring samples obtained from the local neighboring buffer, wherein the second decoding process is different from the first decoding process.

[0005] According to a second aspect of the present application, an exemplary video decoding method is disclosed. The exemplary video decoding method includes performing a plurality of decoding processes including: performing a first decoding process on a current coding block according to reconstructed neighboring samples, wherein the first decoding process uses reconstructed neighboring samples obtained from a local neighboring buffer; obtaining at least a portion of the reconstructed neighboring samples from the local neighboring buffer, and applying a second decoding process to the current coding block according to at least the portion of the reconstructed neighboring samples, wherein the second decoding process is different from the first decoding process.

[0006] These and other objects of the present application will no doubt become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments, the accompanying drawings and the appended claims.

[0007] Other aspects and features of the present application will become apparent to those skilled in the art from a review of the following description of specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A block diagram showing a first video decoder architecture employing hardware sharing technique to reduce hardware cost according to an embodiment of the present application is shown.

[0009] Figure 2 A diagram showing a first video decoder according to an embodiment of the present application is shown.

[0010] Figure 3 A block diagram showing a second video decoder architecture employing hardware sharing technique to reduce hardware cost according to an embodiment of the present application is shown.

[0011] Figure 4 A diagram showing a second video decoder according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0012] Some terminology is used in the following description and claims that refer to particular components. As will be appreciated by one skilled in the art, electronics manufacturers can refer to the same component by different names. This document does not intend to distinguish between different names for the same component. In the following description and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to...." Also, the term "couple" is intended to mean either an indirect or direct electrical connection. Thus, if one device is coupled to another device, that connection can be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

[0013] Figure 1 A block diagram showing a first video decoder architecture employing hardware sharing techniques to reduce hardware cost according to an embodiment of the present application is shown. The video decoder 100 can be a VVC / H.266 decoder for decoding bitstreams conforming to the VVC / H.266 standard. That is, the decoding process performed by the video decoder 100 conforms to the VVC / H.266 standard. However, this is for illustrative purposes only and is not meant to limit the present application. In fact, any video decoder using the architecture proposed by the present application falls within the scope of the present application. The video decoder 100 comprises a plurality of processing circuits 102_1-102_N (N > 1) for performing specified decoding processes, respectively. As will be appreciated by one skilled in the art, the processing circuits 102_1-102_N can be implemented as hardware circuits, software modules, or a combination of both. For example, the processing circuits 102_1-102_N can be implemented as hardware circuits, software modules, or a combination of both. Figure 1As shown, one processing circuit 102_i (1≤i≤N) comprises a local neighboring buffer 104 and a direct current (DC) average calculation circuit 106. In the present embodiment, the local neighboring buffer 104 can be a Coding Tree Unit (CTU) level buffer (e.g. on-chip static random access memory (SRAM)) which is much smaller than a frame level buffer (e.g. off-chip DRAM). The local neighboring buffer 104 and the DC average calculation circuit 106 of the processing circuit 102_i are shared by the processing circuit 102_i and another processing circuit 102_j (1≤j≤N, j≠i). For example, the processing circuit 102_i is arranged to apply a first decoding process to a current coding block according to reconstructed neighboring samples. The coding block can be a coding unit (CU) which consists of one luma block and two chroma blocks. The local neighboring buffer 104 is arranged to buffer the reconstructed neighboring samples used by the first decoding process. The DC average calculation circuit 106 is used to calculate a first DC average according to the reconstructed neighboring samples fetched from the local neighboring buffer 104, wherein the first DC average is used by the first decoding process. The processing circuit 102_j is arranged to apply a second decoding process to the current coding block according to at least a portion (e.g. part or all) of the reconstructed neighboring samples fetched from the local neighboring buffer 104, wherein the second decoding process is different from the first decoding process. In the present embodiment, the DC average calculation circuit 106 is shared for calculating a second DC average according to at least a portion of the reconstructed neighboring samples fetched from the shared local neighboring buffer 104, wherein the second DC average is used by the second decoding process.

[0014] By way of example and not limitation, one of the processing circuits 102_i and 102_j can be an intra prediction circuit, and / or the other of the processing circuits 102_i and 102_j can be a chroma scaling circuit. Figure 2 A diagram of a first video decoder according to an embodiment of the present application is shown. The video decoder 200 employs the video decoder architecture shown, and thus has a plurality of processing circuits, including an entropy decoder (e.g. variable length decoder (VLD) 202), inverse scaling, quantization and transform circuit (labeled "inverse scaling / quantization / transform") 204, intra prediction circuit (labeled "intra prediction") 206, inter prediction circuit (labeled "inter prediction") 208, inter / intra mode selection circuit (labeled "inter / intra selection") 210, chroma scaling circuit (labeled "chroma scaling") 212, and reconstruction circuit (labeled "reconstruction") 214. Figure 1 The video decoder architecture shown, and thus has a plurality of processing circuits, including an entropy decoder (e.g. variable length decoder (VLD) 202), inverse scaling, quantization and transform circuit (labeled "inverse scaling / quantization / transform") 204, intra prediction circuit (labeled "intra prediction") 206, inter prediction circuit (labeled "inter prediction") 208, inter / intra mode selection circuit (labeled "inter / intra selection") 210, chroma scaling circuit (labeled "chroma scaling") 212, and reconstruction circuit (labeled "reconstruction") 214.

[0015] Inter prediction circuit 208 includes a motion estimation circuit (labeled "ME") 216 and a motion compensation circuit (labeled "MC") 218. In the present embodiment, Figure 1 The processing circuit 102_i shown in FIG. 2A can be implemented by the intra prediction circuit 206, while Figure 1 The processing circuit 102_j shown in FIG. 2A can be implemented by the chroma scaling circuit 212. Thus, the intra prediction circuit 206 includes a local neighboring buffer 222, a DC average calculation circuit 226 for processing the DC mode in intra prediction, and other intra mode processing circuit (labeled "other intra mode") 228. For brevity, some decoder components, including a loop filter, a decoded picture buffer (DPB), and the like, are not shown in FIG. 2A. Figure 2

[0016] The intra prediction circuit 206 is arranged to generate the intra prediction samples of the current coding block from the reconstructed neighboring samples belonging to one or more neighboring coding blocks. The intra prediction circuit 206 supports different intra prediction modes, including the DC mode. The DC mode is a traditional prediction mode in intra prediction. The concept of the DC mode is to predict each sample in the current coding block by the average of the reconstructed neighboring samples. For example, when the DC mode is selected for the intra prediction of the current luma block, each intra prediction sample of the current luma block is predicted by the reconstructed neighboring luma samples (e.g., the top reconstructed neighboring luma samples, or the left reconstructed neighboring luma samples, or the top and left reconstructed neighboring luma samples).

[0017] The chroma scaling circuit 212 is arranged to use luma-dependent chroma residual scaling to compensate for luma-chroma interaction caused by luma mapping. The luma-dependent chroma residual scaling applies a constant scaling factor CScaleInv to all chroma residual samples CResScale in the chroma block, and can be represented as CRes = CResScale * CScaleInv. The derivation of the constant scaling factor CScaleInv for the current chroma block depends on the average of the reconstructed neighboring samples (e.g., the top reconstructed neighboring luma samples, or the left reconstructed neighboring luma samples, or the top and left reconstructed neighboring luma samples). It is noted that the reconstructed neighboring samples used for the chroma samples of the current coding block can be the same as, or can be a subset of, the reconstructed neighboring samples used for the DC mode intra prediction of the current coding block.

[0018] ​Based on the above observation, the present application proposes to apply hardware sharing technique to the video decoder 200. Specifically, due to the algorithmic similarity between DC mode intra prediction and chroma scaling, the local neighboring buffer 222 and the DC average calculation circuit 226 are shared between the intra prediction circuit 206 and the chroma scaling circuit 212. In this way, the hardware cost can be reduced.

[0019] The DC average calculation circuit 106 / 226 is not a high cost hardware. Compared with the DC average calculation circuit 106 / 226, the local neighboring buffer 104 / 222 is more costly and needs more complicated control technique. In order to simplify the complexity of hardware control, the DC average calculation for DC mode intra prediction and the DC average calculation for chroma scaling can be independent of each other.

[0020] Figure 3 A block diagram showing a second video decoder architecture employing hardware sharing technique to reduce hardware cost according to an embodiment of the present application is shown. The video decoder 300 can be a VVC / H.266 decoder for decoding bitstream conforming to VVC / H.266 standard. That is, the decoding process performed by the video decoder 300 conforms to VVC / H.266 standard. However, this is for illustrative purpose only and does not mean to limit the present application. In fact, any video decoder using the architecture proposed by the present application falls within the scope of the present application. The video decoder 300 comprises a plurality of processing circuits 302_1-302_N (N>1) for processing designated decoding process respectively. As shown, one processing circuit 302_i (1≤i≤N) comprises a local neighboring buffer 304 and a DC average calculation circuit 306. In the present embodiment, the local neighboring buffer 304 can be a CTU level buffer (e.g. on-chip SRAM) which is much smaller than a frame level buffer (e.g. off-chip DRAM). The local neighboring buffer 304 owned by the processing circuit 302_i is shared by the processing circuit 302_i and another processing circuit 302_j (1≤j≤N, j≠i). Like the processing circuit 302_i, the processing circuit 302_j owns its own DC average calculation circuit 308. In other words, the DC average calculation circuits 304 and 306 are independent circuits, thus the DC average calculation circuit 306 owned by the processing circuit 302_i is not shared by the processing circuit 302_j. Figure 3

[0021] ​In this embodiment, processing circuit 302_i is arranged to apply a first decoding process to the current coding block based on reconstructed neighbor samples. For example, the coding block may be a CU consisting of one luma block and two chroma blocks. A local neighbor buffer 304 is used to buffer the reconstructed neighbor samples used by the first decoding process, and a DC average calculation circuit 106 is used to calculate a first DC average based on the reconstructed neighbor samples obtained from the local neighbor buffer 104, wherein the first DC average is used by the first decoding process. Processing circuit 302_j is arranged to apply a second decoding process to the current coding block based on at least a portion (e.g., partial or complete) of the reconstructed neighbor samples obtained from the local neighbor buffer 304, wherein the second decoding process differs from the first decoding process. A DC average calculation circuit 308 is used to calculate a second DC average based on at least a portion of the reconstructed neighbor samples obtained from the local neighbor buffer 304, wherein the second DC average is used for the second decoding process.

[0022] As an example and not a limitation, one of the processing circuits 302_i and 302_j can be an intra-frame prediction circuit, and / or the other of the processing circuits 302_i and 302_j can be a chroma scaling circuit. Figure 4 A diagram illustrating a second video decoder according to an embodiment of the present invention is shown. The video decoder 400 employs... Figure 3 The video decoder architecture is shown. In this embodiment, Figure 3 The processing circuit 302_i shown can be implemented by intra-frame prediction 406, and Figure 3 The processing circuit 302_j shown can be implemented by the chroma scaling circuit 412. For simplicity, some decoder components, including loop filters and the Decoded Picture Buffer (DPB), are not included. Figure 4 As shown in the diagram. The main difference between video decoders 200 and 400 lies in the design of the intra-frame prediction circuit 406 and the chroma scaling circuit 412. Regarding the intra-frame prediction 406, it includes a local neighbor buffer 422, a DC averaging circuit 426, and other intra-frame mode processing circuitry 228. The DC averaging circuit 426 processes the DC mode in intra-frame prediction, and the local neighbor buffer 422 is shared between the intra-frame prediction circuit 406 and the chroma scaling circuit 412 to buffer reconstructed neighbor samples used by DC mode intra-frame prediction and chroma. Regarding the chroma scaling circuit 412, it has a DC averaging circuit 428 independent of the DC averaging circuit 426 for processing chroma scaling.

[0023] In particular, the intra prediction circuit 406 is configured to generate the intra predicted samples of the current coding block based on reconstructed neighboring samples belonging to one or more neighboring coding blocks. When the DC mode is selected for the intra prediction, the DC average calculation circuit 426 obtains the reconstructed neighboring samples (e.g., the top reconstructed neighboring luma samples, or the left reconstructed neighboring luma samples, or the top and left reconstructed neighboring luma samples) from the local neighboring buffer 422, and calculates an average of the reconstructed neighboring samples, wherein each of the intra predicted samples of the current luma block is set by the calculated average of the reconstructed neighboring samples.

[0024] The chroma scaling circuit 412 is arranged to use luma-dependent chroma residual scaling to compensate for luma-chroma interaction caused by luma mapping. The DC average calculation circuit 428 obtains the reconstructed neighboring samples (e.g., the top reconstructed neighboring luma samples, or the left reconstructed neighboring luma samples, or the top and left reconstructed neighboring luma samples) from the local neighboring buffer 422, and calculates an average of the reconstructed neighboring samples, wherein a constant scaling factor CScaleInv applied to all chroma residual samples CResScale in the chroma block is derived from the calculated average of the reconstructed neighboring samples. It is noted that the reconstructed neighboring samples used for the chroma samples of the current coding block can be the same as, or a subset of, the reconstructed neighboring samples used for the DC mode intra prediction of the current coding block.

[0025] In short, since the DC average calculation for the DC mode intra prediction and the chroma scaling can employ the same / similar algorithm, one or both of the CTU-level neighboring buffer and the DC average calculation circuit can be shared between the DC mode intra prediction and the chroma scaling, thereby reducing the hardware cost of the video decoder.

[0026] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method can be made without departing from the teachings of the present application. Accordingly, the above disclosure is intended to be illustrative only and not limiting of the scope of the present application.

Claims

1. A video decoder comprising: a plurality of processing circuits comprising: a first processing circuit arranged to apply a first decoding process to a current coding block in dependence on a plurality of reconstructed neighboring samples, wherein the first processing circuit comprises: a local neighboring buffer arranged to buffer the plurality of reconstructed neighboring samples used by the first decoding process; and a second processing circuit arranged to apply a second decoding process to the current coding block in dependence on at least a portion of the plurality of reconstructed neighboring samples obtained from the local neighboring buffer, wherein the second decoding process is different from the first decoding process, wherein the first processing circuit further comprises a direct current average calculation circuit that is shared between the first processing circuit and the second processing circuit.

2. The video decoder of claim 1, wherein, The first processing circuit is an intra prediction circuit.

3. The video decoder of claim 2, wherein, The second processing circuit is a chroma scaling circuit.

4. The video decoder of claim 1, wherein, The second processing circuit is a chroma scaling circuit.

5. The video decoder of claim 1, wherein, The video decoder is a multi-function video coding decoder.

6. The video decoder of claim 1, wherein: the direct current average calculation circuit is arranged to calculate a first direct current average in dependence on the plurality of reconstructed neighboring samples, and to calculate a second direct current average in dependence on at least a portion of the plurality of reconstructed neighboring samples; wherein the first direct current average is used by the first decoding process, and the second direct current average is used by the second decoding process.

7. The video decoder of claim 6, wherein, The first processing circuit is an intra prediction circuit.

8. The video decoder of claim 7, wherein, The second processing circuit is a chroma scaling circuit.

9. The video decoder of claim 6, wherein, The second processing circuit is a chroma scaling circuit.

10. The video decoder of claim 6, wherein, The video decoder is a multi-function video coding decoder.

11. A video decoding method comprising: performing a plurality of decoding processes comprising: performing a first decoding process on a current coding block in dependence on a plurality of reconstructed neighboring samples, wherein the first decoding process obtains the plurality of reconstructed neighboring samples from a local neighboring buffer; and obtaining at least a portion of the plurality of reconstructed neighboring samples from the local neighboring buffer, and performing a second decoding process on the current coding block in dependence on at least a portion of the plurality of reconstructed neighboring samples, wherein the second decoding process is different from the first decoding process, and a direct current average calculation circuit is shared between the first decoding process and the second decoding process.

12. The video decoding method of claim 11, wherein, The first decoding process is an intra prediction process.

13. The video decoding method of claim 12, wherein, The second decoding process is a chroma scaling process.

14. The video decoding method of claim 11, wherein, The second decoding process is a chroma scaling process.

15. The video decoding method of claim 11, wherein, The plurality of decoding processes conform to a multi-function video coding standard.

16. The video decoding method of claim 11, wherein, performing the first decoding process on the current coding block in dependence on the plurality of reconstructed neighboring samples comprises: calculating, by a direct current average calculation circuit, a first direct current average in dependence on the plurality of reconstructed neighboring samples, wherein the first direct current average is used by the first decoding process; and performing the second decoding process on the current coding block in dependence on at least a portion of the plurality of reconstructed neighboring samples comprises: calculating, by a direct current average calculation circuit, a second direct current average in dependence on at least a portion of the plurality of reconstructed neighboring samples, wherein the second direct current average is used by the second decoding process.

17. The video decoding method of claim 16, wherein, The first decoding process is an intra prediction process.

18. The video decoding method of claim 17, wherein, The second decoding process is a chroma scaling process.

19. The video decoding method of claim 16, wherein, The second decoding process is a chroma scaling process.

20. The video decoding method of claim 16, wherein, The plurality of decoding processes conform to a multi-functional video coding standard.

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