A load transient detection circuit applied to a DC-DC converter

Abstract

The application belongs to the technical field of analog power management, and discloses a load transient detection circuit applied to a DC-DC converter. The load transient detection circuit comprises a duty cycle conversion module, a sample-and-hold module, a data selection module and a hysteresis comparator. A buffer is arranged between the duty cycle conversion module and the sample-and-hold module. Two output ends of the duty cycle module are respectively connected to positive and negative input ends of the buffer. An output end of the buffer is connected to an input end of the sample-and-hold module. An output end of the sample-and-hold module is connected to an input end of the data selection module. An output end of the data selection module is connected to the hysteresis comparator. For the DC-DC converter working in an environment with large load change, the load transient detection circuit can quickly detect and output a control signal when the load has a transient response, and has the characteristics of continuous monitoring, good accuracy, no interference to the work of other transient enhancement circuits and wide applicability.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of analog power management, and particularly relates to a load transient detection circuit applied to a DC-DC converter. BACKGROUND

[0002] Portable electronic products are various in types, complete in functions, changeable in use environment, and integrated with multiple functions in an all-in-one machine. The all-in-one machine can rapidly enter a load working state from a standby state, and the load in the working state can also change rapidly. Therefore, the output voltage of the voltage stabilizer power supply needs to have high stability and can rapidly recover to the stable value when the load jumps. The traditional current mode PWM modulation DC-DC converter cannot meet the requirements.

[0003] There are many kinds of researches based on the transient enhancement method, most of which are based on improving the bandwidth through complex compensation. A small capacitor is usually used to improve the bandwidth when the load has a transient state by using the capacitor multiplication technology, and a large capacitor is used to compensate the loop stability in the remaining steady state time. The transient enhancement circuit is added at a certain point in the loop after detecting the occurrence of the load transient, so that the loop can rapidly respond. No matter what method is used, the high-speed transient detection circuit cannot be avoided.

[0004] The traditional transient detection circuit usually detects the feedback voltage VFB. When the load has a transient response, the output voltage VOUT jumps, so that VFB also jumps in a small range. Therefore, the change of VFB can be detected to determine the occurrence of the load transient. The disadvantage of this method is that VFB usually has a ripple. First, a low-pass filter needs to be used to filter VFB, and the filtering process itself will inevitably cause a delay. Second, if the size of the output voltage is changed, this method is not applicable. SUMMARY

[0005] In order to solve the problems in the prior art, the application provides a load transient detection circuit applied to a DC-DC converter, which has the characteristics of continuous monitoring, good accuracy, no interference with the work of other transient enhancement circuits, and wide applicability.

[0006] In order to achieve the above technical scheme, the application provides the following technical scheme.

[0007] A load transient detection circuit applied to a DC-DC converter, comprising a duty cycle conversion module, a sample-and-hold module, a data selection module, and a hysteresis comparator.

[0008] A buffer is arranged between the duty cycle conversion module and the sample-and-hold module.

[0009] The two outputs of the duty cycle module are connected to the positive input and the negative input of the buffer respectively; the output of the buffer is connected to the input of the sample and hold module;

[0010] The output of the sample and hold module is connected to the input of the data selection module;

[0011] The output of the data selection module is connected to the hysteresis comparator.

[0012] Further, the duty cycle conversion module comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a first sampling transistor M5 and a second sampling transistor M6;

[0013] The gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor and the source of the third MOS transistor, and the source is connected to the source of the second MOS transistor M2;

[0014] The drain of the second MOS transistor M2 is connected to the source of the fourth MOS transistor M4;

[0015] The drain of the third MOS transistor M3 is connected to the input of the current source and the gate of the fourth MOS transistor M4;

[0016] The drain of the fourth MOS transistor M4 is connected to the drain of the first sampling transistor M5;

[0017] The source of the first sampling transistor M5 is connected to the drain of the second sampling transistor M6 and the upper plate of the capacitor C D ; the gate is connected to the input of the duty cycle D signal;

[0018] The drain of the second sampling transistor M6 is connected to the upper plate of the capacitor C D , and the source is connected to the 500mV reference voltage source;

[0019] The upper plate of the capacitor C D is connected to the positive input of the buffer, and the lower plate is connected to the 500mV reference voltage source.

[0020] Further, the sample and hold module comprises two first frequency dividers, two first AND circuits and two first XOR circuits;

[0021] The two first frequency dividers, the two first AND circuits and the two first XOR circuits are distributed side by side to form a first parallel branch and a second parallel branch respectively;

[0022] The input end of the first frequency divider of the first branch and the second branch is connected to the output end of the comparator, the output end of the first frequency divider is connected to the input end of the first AND gate circuit, the output end of the first AND gate circuit is connected to the input end of the first AND OR gate circuit, and the output end of the first AND OR gate circuit is connected to the input end of the data selection module.

[0023] Further, a first node VA and a second node VB are arranged on the circuit where the first frequency divider and the data selection module are located and the circuit where the second frequency divider and the data selection module are located respectively, and a capacitor is connected to one end of the first node VA and the second node VB respectively, and the other end of the capacitor is grounded.

[0024] Further, the data selection module comprises a fifth MOS tube M7, a sixth MOS tube M8, and a third branch and a fourth branch connected to the output end of the first branch and the output end of the second branch.

[0025] The third branch and the fourth branch each comprise a second frequency divider, a second AND gate circuit and a second XOR gate circuit connected to the output end of the first branch and the output end of the second branch.

[0026] The output end of the first branch and the output end of the second branch are respectively provided with two second frequency dividers arranged side by side, two second AND gate circuits and two second XOR gate circuits.

[0027] The input end of the two second frequency dividers of the third branch and the fourth branch is connected to the output end of the second AND OR gate circuit, the output end of the second frequency divider is connected to the input end of the second AND gate circuit, the output end of the second AND gate circuit is connected to the input end of the second AND OR gate circuit, and the output end of the second AND OR gate circuit of the third branch and the fourth branch is connected to each other, and the lead wire after connection is connected to the input end of the hysteresis comparator.

[0028] A third node VC is arranged on the line connected to the hysteresis comparator on the third branch, the gate of the fifth MOS tube M7 is connected to the third node VC, and the source is grounded.

[0029] A fourth node VD is arranged on the line connected to the hysteresis comparator on the fourth branch, the gate of the sixth MOS tube M8 is connected to the fourth node VD, the source is grounded, and the drain is connected to the drain of the fifth MOS tube M7.

[0030] Further, the hysteresis comparator comprises a first comparator COM1 and a second comparator COM2,

[0031] The positive input pin of the first comparator COM1 is connected to the output end of the third branch, and is connected to the positive pin of the second comparator COM2, the negative input pin is connected to the negative input pin of the second comparator COM2, and the output pin is the output end;

[0032] The positive input pin of the second comparator COM2 is connected to the line connecting the two negative pins of the first comparator COM1 and the second comparator COM2, and the output pin is the output end.

[0033] Further, the first comparator COM1 and the second comparator COM2 in the hysteresis comparator are distributed side by side.

[0034] Further, the output end of the current source is grounded.

[0035] Further, the voltage of the capacitor CD is: ;

[0036] Wherein, 0 is a lower limit of a cycle time, TON is an upper limit of a cycle time, IOSC represents an oscillator charging current, and C represents the size of the capacitor value. D

[0037] Further, the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, and the fourth MOS tube M4 are P-type MOS tubes, and the fifth MOS tube M7 and the sixth MOS tube M8 are N-type MOS tubes.

[0038] Compared with the prior art, the application has the following advantages:

[0039] The application relates to a load transient detection circuit applied to a DC-DC converter, which comprises a duty cycle conversion module, a sample-and-hold module, a data selection module and a hysteresis comparator. The duty cycle conversion circuit transmits the output current of an oscillator through an input signal, and the sample-and-hold circuit can alternately sample and store the duty cycle information; the hysteresis comparator inputs the sampled duty cycle information to the positive and negative ends through the data selection circuit, the data selection circuit always inputs the duty cycle information of the latest cycle to the positive end of the comparator, and inputs the duty cycle of the last cycle to the negative end of the comparator, so that the comparator always compares the size of the duty cycles of the current cycle and the last cycle, thereby judging whether the load has a transient response. For the DC-DC converter working in an environment with large load change, the load transient response can be quickly detected and a control signal can be outputted, compared with directly sampling and detecting VFB, the application has the advantages of high speed and small PVT influence; the application has the advantages of continuous monitoring, good accuracy, no interference to the work of other transient enhancement circuits and wide applicability. DRAWINGS

[0040] ​The accompanying drawings, which form a part of this specification, are included to provide a further understanding of the application and are incorporated herein in

[0041] Figure 1 A circuit diagram of a load transient detection circuit applied to a DC-DC converter according to the present application;

[0042] Figure 2 A digital logic circuit schematic of a load transient detection circuit applied to a DC-DC converter according to the present application;

[0043] Figure 3 A schematic of a first comparator COM1 and a second comparator COM2 of a load transient detection circuit applied to a DC-DC converter according to the present application, which can output a pulse voltage; DETAILED DESCRIPTION

[0044] The present application will be described in detail below with reference to the accompanying drawings and embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0045] The following detailed description is exemplary in nature and is intended to provide further description of the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used herein is for the purpose of describing the exemplary embodiments only and is not intended to limit the scope of the present application.

[0046] The application discloses a load transient detection circuit applied to a DC-DC converter, which can rapidly detect the occurrence of load transient by the change of duty cycle during the load transient, and comprises a duty cycle sampling circuit and two hysteresis comparators. The duty cycle sampling circuit is composed of a duty cycle conversion circuit, a high-speed buffer, a digital logic circuit capable of realizing period switching, a sample-and-hold circuit and a data selection circuit. The duty cycle conversion circuit inputs the output current IOSC of an oscillator to a charging capacitor through a NMOS tube with an input signal as a DC-DC main switch tube gate signal, and the output voltage on the charging capacitor is related to IOSC and the on-time of the NMOS, that is, the duty cycle. The voltage on the charging capacitor is input to two sample-and-hold circuits through a high-speed analog buffer, and the digital logic circuit divides the main switch tube gate signal into two square wave signals with a frequency of half of the original frequency as the control signals of the sample-and-hold circuits, so that the sample-and-hold circuits can alternately sample and store the information of the duty cycle. The hysteresis comparators input the sampled duty cycle information to the positive and negative ends through the data selection circuit, the data selection circuit always inputs the duty cycle information of the latest period to the positive end of the comparator and the duty cycle information of the last period to the negative end of the comparator, so that the comparator always compares the duty cycles of the current period and the last period, thereby judging whether the load has a transient response.

[0047] A load transient detection circuit applied to a DC-DC converter, as shown in the accompanying drawings, comprises a duty cycle conversion module, a sample-and-hold module, a data selection module and a hysteresis comparator. Figure 1 The buffer is connected between the duty cycle conversion module and the sample-and-hold module, the two output ends of the duty cycle conversion module are connected to the positive input end and the negative input end of the buffer respectively, the output end of the buffer is connected to the input end of the sample-and-hold module, the output end of the sample-and-hold module is connected to the input end of the data selection module, and the output end of the data selection module is connected to the hysteresis comparator.

[0048] Specifically, the duty cycle sampling circuit is composed of a duty cycle conversion circuit, a high-speed buffer, a digital logic circuit capable of realizing period switching, and a sample-and-hold circuit. The duty cycle conversion circuit takes the oscillator charging current as input, and then selects the current to the charging capacitor through a NMOS with the main switch tube gate signal as the gate as a switch. According to the current size and the on time, the voltage on the capacitor can be determined, which is linearly related to the size of the duty cycle. The digital logic circuit generates the logic control of the sample-and-hold circuit and the data selection circuit, and the required signal can be obtained by dividing the main switch tube gate signal and the clock signal, performing XOR processing, etc. The sample-and-hold circuit can sample the voltage values related to the duty cycle in the current period and the last period respectively through the control signal generated by the digital logic circuit, and input the voltage values to the positive and negative terminals of the comparator through the data selection circuit. The purpose of the hysteresis comparator is to eliminate sampling errors and errors caused by changes in duty cycle in the steady state of the system. Negative feedback is also introduced, which can quickly pull the output back to the output logic level in the steady state when the comparator output jumps, so as to convert the output of the comparator into pulse output.

[0049] Specifically, as shown in Figure 1 , the duty cycle conversion module includes a first MOS tube M1, the gate of which is connected to the gate of a second MOS tube and the source of a third MOS tube, and the source is connected to the source of a second MOS tube M2; the drain of the second MOS tube M2 is connected to the source of a fourth MOS tube M4; the drain of the third MOS tube M3 is connected to the input end of a current source and the gate of the fourth MOS tube M4; the drain of the fourth MOS tube M4 is connected to the drain of a first sampling tube M5; the source of the first sampling tube M5 is connected to the drain of a second sampling tube M6 and the upper plate of a capacitor C D ; the gate is connected to the input of a duty cycle D signal; the drain of the second sampling tube M6 is connected to the upper plate of a capacitor C D , and the source is connected to a 500mV reference voltage source; the upper plate of the capacitor C D is connected to the positive input end of a buffer, and the lower plate is connected to a 500mV reference voltage source.

[0050] Specifically, the output end of the current source is grounded.

[0051] Specifically, as shown in Figure 1 and Figure 2As shown, the sample and hold module includes two first frequency dividers, two first AND gate circuits and two first XOR gate circuits; the two first frequency dividers, the two first AND gate circuits and the two first XOR gate circuits are distributed side by side to form a first side-by-side branch and a second side-by-side branch respectively; the input ends of the first frequency dividers of the first branch and the second branch are connected to the output end of the comparator, the output ends of the first frequency dividers are connected to the input ends of the first AND gate circuits, the output ends of the first AND gate circuits are connected to the input ends of the first AND OR gate circuits, and the output ends of the first AND OR gate circuits are connected to the input ends of the data selection module respectively.

[0052] Specifically, the first node VA and the second node VB are arranged on the circuit where the first frequency divider and the data selection module are located and the circuit where the second frequency divider and the data selection module are located respectively, and a capacitor is connected to one end of the first node VA and the second node VB respectively, and the other end of the capacitor is grounded.

[0053] Specifically, the data selection module includes a fifth MOS tube M7, a sixth MOS tube M8, and a third branch and a fourth branch connected to the output ends of the first branch and the second branch; the third branch and the fourth branch each include a second frequency divider, a second AND gate circuit and a second XOR gate circuit connected to the output ends of the first branch and the second branch; the output ends of the first branch and the second branch are provided with two second frequency dividers distributed side by side, two second AND gate circuits and two second XOR gate circuits; the input ends of the two second frequency dividers of the third branch and the fourth branch are connected to the output ends of the first AND OR gate circuits, the output ends of the second frequency dividers are connected to the input ends of the second AND gate circuits, the output ends of the second AND gate circuits are connected to the input ends of the second AND OR gate circuits, the output ends of the second AND OR gate circuits of the third branch and the fourth branch are connected to each other, and the lead wires after connection are connected to the input ends of the hysteresis comparator; a third node VC is arranged on the lead wire connected to the hysteresis comparator on the third branch, the gate of the fifth MOS tube M7 is connected to the third node VC, and the source is grounded; a fourth node VD is arranged on the lead wire connected to the hysteresis comparator on the fourth branch, the gate of the sixth MOS tube M8 is connected to the fourth node VD, the source is grounded, and the drain is connected to the drain of the fifth MOS tube M7.

[0054] Specifically, as shown in FIG. 4, the data selection module includes a fifth MOS tube M7, a sixth MOS tube M8, and a third branch and a fourth branch connected to the output ends of the first branch and the second branch; the third branch and the fourth branch each include a second frequency divider, a second AND gate circuit and a second XOR gate circuit connected to the output ends of the first branch and the second branch; the output ends of the first branch and the second branch are provided with two second frequency dividers distributed side by side, two second AND gate circuits and two second XOR gate circuits; the input ends of the two second frequency dividers of the third branch and the fourth branch are connected to the output ends of the first AND OR gate circuits, the output ends of the second frequency dividers are connected to the input ends of the second AND gate circuits, the output ends of the second AND gate circuits are connected to the input ends of the second AND OR gate circuits, the output ends of the second AND OR gate circuits of the third branch and the fourth branch are connected to each other, and the lead wires after connection are connected to the input ends of the hysteresis comparator; a third node VC is arranged on the lead wire connected to the hysteresis comparator on the third branch, the gate of the fifth MOS tube M7 is connected to the third node VC, and the source is grounded; a fourth node VD is arranged on the lead wire connected to the hysteresis comparator on the fourth branch, the gate of the sixth MOS tube M8 is connected to the fourth node VD, the source is grounded, and the drain is connected to the drain of the fifth MOS tube M7. Figure 1 and Figure 3As shown, the hysteresis comparator comprises a first comparator COM1 and a second comparator COM2, the positive input pin of the first comparator COM1 is connected to the output end of the third branch, and is connected to the positive input pin of the second comparator COM2, the negative input pin is connected to the negative input pin of the second comparator COM2, and the output pin is the output end; the positive input pin of the second comparator COM2 is connected to the line connecting the two negative pins of the first comparator COM1 and the second comparator COM2, and the output pin is the output end. Preferably, the first comparator COM1 and the second comparator COM2 in the hysteresis comparator are distributed side by side.

[0055] Preferably, all MOS tubes in the application are N-type MOS tubes.

[0056] Specifically, the transient detection circuit is not affected by the output voltage VOUT and the feedback voltage VFB, and is less affected by PVT. It is suitable for DC-DC converters with different output voltages. Figure 1 As shown, it is a specific principle diagram of a load transient detection circuit applied to a DC-DC converter according to the application, which comprises a duty cycle conversion module, a sample and hold module, a data selection module and a hysteresis comparator.

[0057] Wherein M1~M4 provide a bias current IOSC same as the oscillator charging current, M5 and M6 are sampling tubes, the gate signal of M5 is the gate signal D of the main switch tube, and the gate signal of M6 is the inverse 1-D of the gate signal of the main switch tube. When the main switch tube is turned on, M5 is turned on, IOSC charges the CD capacitor through M5, and the voltage on CD can be obtained as: Therefore, it can be concluded that, , , .

[0058] From the above formula, it can be seen that the sampling voltage VCD of the CD capacitor in one period is positively correlated with the duty cycle D, that is, the size of the sampling voltage VCD can reflect the size of the duty cycle. M6 tube clears the voltage on the CD capacitor after one period of sampling, and repeats the above sampling process in the next period.

[0059] At the same time of sampling, VCD transmits the voltage to the sample and hold module through a high-speed buffer, and two sample and hold circuits sample the size of the duty cycle in the current period and the last period respectively. The logic control signal of TG1~TG2 is generated by Figure 2 Circuit, the duty cycle signal D is obtained through a frequency divider to obtain D- signal, D and D- signal are subjected to AND logic to obtain D_1 signal, and D and D_1 signal are subjected to XOR logic to obtain D_2 signal, and Figure 2 It can be seen that the D_2 signal is always one period later than the D_1 signal.

[0060] After sampling, the stored voltage VA, VB is transmitted to the positive and negative terminals of the first comparator COM1 and the second comparator COM2 through the data selection circuit. The logic signals of TG3~TG6 are generated by the same method, except that the input signal is the CLK clock signal. When the duty cycle of the current period is VA, TG3 and TG6 are turned on, and VA is input to the positive terminal of the two comparators, and VB is input to the negative terminal of the two comparators; when the duty cycle of the current period is VB, TG4 and TG5 are turned on, and VB is input to the positive terminal of the two comparators, and VA is input to the negative terminal of the two comparators. It can be seen that the positive terminal of the comparator always inputs the current period sampling voltage, and the negative terminal always inputs the last period sampling voltage. M7 and M8 are discharge NMOS tubes, which clear the VC, VD storage voltage after the comparison of the comparator is completed, and the control signal thereof is generated by two-phase non-overlapping clock signals to generate a signal that does not overlap with the CLK signal.

[0061] As shown in Figure 3 In order to prevent the inherent imbalance of VC, VD due to clock feedthrough and charge injection, and the fluctuation of the duty cycle within a certain range caused by the output voltage ripple, a hysteresis comparator is used to prevent the logic signal from being falsely flipped in the steady state. When the load is heavy to light, the first comparator COM1 is used for comparison, and the role of M4 is to make VS1 output a pulse voltage. The principle is that when the load is heavy to light, the duty cycle decreases to reduce the charging current of the inductance current to the load capacitor, at this time V+ should be less than V- to cause VOUT to be pulled down to low level, at this time VCT is also low to cause M4 to be turned off, and VOUT is restored to high level to make VS1 generate a pulse output. M14 uses an inverse ratio tube to reduce the discharge speed of the M19 MOS capacitor to control the pulse width of VS1. Similarly, for COM2, when the load is light to heavy, V+ should be greater than V- to cause VOUT to be pulled up to high level, at this time VCT is low to make M3 be turned off, and VOUT is restored to low level.

[0062] Specifically, in the first comparator COM1 and the second comparator COM2 in the application, the gate of the MOS tube M1 is connected to the VD end of the data selection module, the source of the MOS tube M1 is connected to the output end of the reference current source with the source of the MOS tube M2, the drain of the MOS tube M1 is connected to the drain of the MOS tube M3, the drain of the MOS tube M2 is connected to the drain of the MOS tube M4, the gate of the MOS tube M3 is connected to the AVIN wire, the gates of the first sampling tube M5, the second sampling tube M6 and the MOS tube M9 are connected, the drain of the first sampling tube M5 is connected to the drain of the MOS tube M7 and the source of the MOS tube M3, the sources of the first sampling tube M5, the second sampling tube M6, the MOS tube M7 and the MOS tube M8 are grounded, the drain of the second sampling tube M6 is connected to the drain of the MOS tube M8 and the drain of the MOS tube M4, and the gate of the MOS tube M7 is connected to the gate of the MOS tube M8 and the gate of the MOS tube M10.

[0063] Specifically, such as Figure 3 As shown, the first comparator COM1 and the second comparator COM2 in this invention also have multiple parallel branches, and each branch has two MOSFETs. On the first parallel branch, MOSFETs M13 and M14 are provided; on the second parallel branch, MOSFETs M15 and M16 are provided; and on the third parallel branch, MOSFETs M17 and M18 are provided. The drains and gates of MOSFETs M13 and M14 are connected, and the gates are connected via wires. The drains and gates of MOSFETs M15 and M16 are connected to each other, and their gates are connected to the drains of MOSFETs M13 and M14. The drains and gates of MOSFETs M17 and M18 are connected to each other, and their gates are connected to the drains of MOSFETs M15 and M16. The sources of MOSFETs M13, M15, and M17 are connected to the AVIN wires in the first comparator COM1 and the second comparator COM2. MOSFETs M14 and M16 are connected to the Vout wires in the first comparator COM1 and the second comparator COM2. The sources of transistors M16 and M18 are connected to the GND wire in the first comparator COM1 and the second comparator COM2. A MOSFET M19 is positioned between MOSFETs M13, M14, M15, and M16. The gate of MOSFET M19 is connected to the wire connecting the drains of MOSFETs M13 and M14 and the wire connecting the gates of MOSFETs M15 and M16. The source and drain of MOSFET M19 are connected, and grounded on the wire connecting the source and drain. A connecting line is provided on the wires between the drains of MOSFETs M15 and M16 and the gates of MOSFETs M17 and M18. One end of the connecting line is connected to a wire, and the other end is connected to the gate of M4 connected to the cable detection unit vct. A wire is also provided on the wire connecting the drains of MOSFETs M17 and M18, and the other end of the wire is connected to VS1 or VS2. This configuration enables the first comparator COM1 and the second comparator COM2 to output pulse signals.

[0064] Specifically, when applying this invention to perform transient detection on a circuit, adjustments can be made according to the specific needs of the circuit: the hysteresis value of the hysteresis comparator and the oscillator charging current value in the duty cycle conversion module can be modified and adjusted according to the actual situation.

[0065] The application can quickly detect the occurrence of the transient state in different transient processes, and can achieve the characteristics of rapidness and stability by setting the hysteresis value of the comparator to cope with the change of PVT.

[0066] The working principle of the application is as follows: for the DC-DC converter with sudden mutation of load current, the output voltage has sudden uprush or downrush, so as to cause the change of feedback voltage VFB, the change of VFB is amplified by an error amplifier and converted into a digital square wave signal through a series of circuits to control the turn-on and turn-off of the main switch tube, the application judges the switching from heavy load to light load or from light load to heavy load and quickly generates a control signal as an opening signal of the subsequent transient enhancement circuit by sampling the change of duty cycle of the current period and the last period.

[0067] It is to be understood by those skilled in the art that the application can be realized by other embodiments without departing from the spirit or essential characteristics thereof. Therefore, the above disclosed embodiments are merely illustrative in all aspects and are not the only ones. All changes within the scope of the application or within the scope equivalent to the application are intended to be included in the application.

[0068] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the application and not to limit it, although the application has been described in detail with reference to the above examples, those skilled in the art should understand that: the specific embodiments of the application can still be modified or replaced equivalently without departing from the spirit and scope of the application, any modification or equivalent replacement without departing from the spirit and scope of the application should be covered in the protection scope of the claims of the application.

Claims

1. A load transient detection circuit applied to a DC-DC converter, characterized in that, It includes a duty cycle conversion module, a sample-and-hold module, a data selection module, and a hysteresis comparator; A buffer is provided between the duty cycle conversion module and the sample-and-hold module; The two outputs of the duty cycle conversion module are connected to the positive and negative inputs of the buffer, respectively; the output of the buffer is connected to the input of the sample-and-hold module. The output of the sample-and-hold module is connected to the input of the data selection module; The output of the data selection module is connected to the hysteresis comparator.

2. A load transient detection circuit for a DC-DC converter according to claim 1, characterized in that, The duty cycle conversion module includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a first sampling transistor M5, and a second sampling transistor M6; The gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor and the source of the third MOS transistor, and its source is connected to the source of the second MOS transistor M2. The drain of the second MOSFET M2 is connected to the source of the fourth MOSFET M4; The drain of the third MOS transistor M3 is connected to the input terminal of the current source and the gate of the fourth MOS transistor M4. The drain of the fourth MOS transistor M4 is connected to the drain of the first sampling transistor M5; The source of the first sampling tube M5 is connected to the drain of the second sampling tube M6 and C. D The upper electrode plate; The gate is connected to the input of the duty cycle D signal; The drain of the second sampling tube M6 is connected to capacitor C. D The upper plate and the source are connected to the reference voltage source; Capacitor C D The upper plate is connected to the positive input terminal of the buffer, and the lower plate is connected to the reference voltage source.

3. A load transient detection circuit for a DC-DC converter according to claim 1, characterized in that, The sample-and-hold module includes two first frequency dividers, two first AND gates, and two first XOR gates. Two first frequency dividers, two first AND gate circuits, and two first XOR gate circuits are arranged in parallel to form the first parallel branch and the second parallel branch, respectively; The input terminals of the first frequency dividers of the first parallel branch and the second parallel branch are respectively connected to the duty cycle D signal and the clock CLK signal. The output terminal of the first frequency divider is connected to the input terminal of the first AND gate circuit. The output terminal of the first AND gate circuit is connected to the input terminal of the first XOR gate circuit. The output terminal of the first XOR gate circuit is respectively connected to the logic control terminal of the transmission gate in the data selection module.

4. A load transient detection circuit for a DC-DC converter according to claim 3, characterized in that, The data selection module includes a fifth MOSFET M7, a sixth MOSFET M8, and a third and fourth branch connected to the output terminals of the first and second branches. Both the third branch and the fourth branch include a second frequency divider, a second AND gate circuit, and a second XOR gate circuit connected to the output terminals of the first branch and the second branch. The output terminals of the first branch and the second branch are respectively provided with two parallel second frequency dividers, two second AND gate circuits and two second XOR gate circuits; The input terminals of the two second frequency dividers in the third and fourth branches are connected to the output terminal of the first AND-OR gate circuit. The output terminal of the second frequency divider is connected to the input terminal of the second AND gate circuit. The output terminal of the second AND gate circuit is connected to the input terminal of the second AND-OR gate circuit. The output terminals of the second AND-OR gate circuits in the third and fourth branches are connected in pairs. After connection, the wires are respectively connected to the input terminal of the hysteresis comparator. A third node VC is provided on the line connected to the hysteresis comparator on the third branch. The drain of the fifth MOS transistor M7 is connected to the third node VC, and the source is grounded. A fourth node VD is provided on the line connected to the hysteresis comparator on the fourth branch. The drain of the sixth MOS transistor M8 is connected to the fourth node VD, the source is grounded, and the gate is connected to the drain of the fifth MOS transistor M7.

5. A load transient detection circuit for a DC-DC converter according to claim 4, characterized in that, A first node VA and a second node VB are respectively set on the circuit where the first frequency divider and the data selection module are located, and on the circuit where the second frequency divider and the data selection module are located. A capacitor is connected to one end of the first node VA and the second node VB, and the other end of the capacitor is grounded.

6. A load transient detection circuit for a DC-DC converter according to claim 1, characterized in that, The hysteresis comparator includes a first comparator COM1 and a second comparator COM2 that are distributed in parallel. The positive input pin of the first comparator COM1 is connected to the output of the third branch and is also connected to the positive pin of the second comparator COM2. The negative input pin is connected to the negative input pin of the second comparator COM2, and the output pin is the output terminal. The positive input pin of the second comparator COM2 is connected to the line connecting the two negative pins of the first comparator COM1 and the second comparator COM2, and the output pin is the output terminal.

7. A load transient detection circuit for a DC-DC converter according to claim 2, characterized in that, The output terminal of the current source is grounded.

8. A load transient detection circuit for a DC-DC converter according to claim 2, characterized in that, The voltage of the capacitor CD is: ; Where 0 represents the lower limit of a cycle time, TON represents the upper limit of a cycle time, IOSC represents the oscillator charging current, and C represents Cc. D Capacity value.

9. A load transient detection circuit for a DC-DC converter according to claim 2, characterized in that, The first MOSFET M1, the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 are P-type MOSFETs, while the fifth MOSFET M7 and the sixth MOSFET M8 are N-type MOSFETs.

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