Method, apparatus and electronic device for performing instruction extraction

Abstract

The present disclosure provides an extraction method, device and electronic equipment for executing instructions, relating to the technical field of computers. The specific implementation scheme is: obtaining a first extraction request, the first extraction request containing the address of the execution instruction; detecting the hit condition of the address in the instruction cache and the prefetch module; extracting the execution instruction according to the hit condition. According to the technical scheme of the present disclosure, the execution instruction and the related prefetch instruction can be stored in the prefetch module space, the hit condition of the execution instruction address can be detected in the instruction cache and the prefetch module at the same time, and the execution instruction can be extracted according to the hit condition, which is different from the conventional prefetch hit access only to the instruction cache, improves the cache access efficiency, reduces the power consumption, and can send the instructions in the prefetch module to the instruction flow in advance, improving the flow performance.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and particularly relates to an execution instruction extraction method and device and electronic equipment. BACKGROUND

[0002] In a computer system, a cache memory (Cache) as a part of hierarchical storage undertakes the task of caching instructions and data. The first-level cache includes an instruction cache (I-Cache) and a data cache (D-Cache). In an instruction fetch pipeline, the hit rate of the I-Cache has a decisive influence on the performance of the pipeline. How to improve the hit rate of the instruction fetch pipeline has become a problem to be solved in the prior art. SUMMARY

[0003] The present disclosure provides an execution instruction extraction method, device and electronic equipment.

[0004] According to an aspect of the present disclosure, an execution instruction extraction method is provided, comprising:

[0005] obtaining a first extraction request, the first extraction request containing an address of an execution instruction;

[0006] detecting a hit condition of the address in an instruction cache and a prefetch module;

[0007] extracting the execution instruction according to the hit condition.

[0008] In an embodiment, extracting the execution instruction according to the hit condition comprises:

[0009] in response to detecting that a miss event is triggered in the instruction cache and a hit event is triggered in the prefetch module, extracting the execution instruction from the prefetch module.

[0010] In an embodiment, extracting the execution instruction according to the hit condition further comprises:

[0011] controlling the prefetch module to backfill the execution instruction to the instruction cache, and deleting the execution instruction in the prefetch module after the backfilling is completed.

[0012] In an embodiment, extracting the execution instruction according to the hit condition further comprises:

[0013] in response to detecting that a hit event is triggered in the instruction cache and a hit event is triggered in the prefetch module, extracting the execution instruction from the instruction cache.

[0014] In an embodiment, extracting the execution instruction according to the hit condition further comprises:

[0015] deleting the execution instruction in the prefetch module.

[0016] In one embodiment, extracting the execution instruction according to the hit condition further comprises:

[0017] extracting the execution instruction from the instruction cache in response to detecting that a hit event is triggered in the instruction cache and a miss event is triggered in the prefetch module.

[0018] In one embodiment, extracting the execution instruction according to the hit condition further comprises:

[0019] controlling the prefetch module to send a second extraction request to the secondary cache in response to detecting that a miss event is triggered in the instruction cache and a miss event is triggered in the prefetch module, the second extraction request containing addresses of the execution instruction and the related prefetch instruction;

[0020] backfilling the execution instruction and the related prefetch instruction to the prefetch module according to a hit condition of the addresses in the secondary cache.

[0021] extracting the execution instruction from the prefetch module.

[0022] In one embodiment, backfilling the execution instruction and the related prefetch instruction to the prefetch module according to the hit condition of the addresses in the secondary cache comprises:

[0023] controlling the secondary cache to backfill the execution instruction and the related prefetch instruction to the prefetch module in response to detecting that the addresses of the execution instruction and the related prefetch instruction all trigger a hit event in the secondary cache.

[0024] In one embodiment, backfilling the execution instruction and the related prefetch instruction to the prefetch module according to the hit condition of the addresses in the secondary cache further comprises:

[0025] controlling the secondary cache to backfill the execution instruction and the related prefetch instruction to the prefetch module in response to detecting that the address of the execution instruction triggers a hit event in the secondary cache and the addresses of the related prefetch instruction of the execution instruction do not all trigger a hit event in the secondary cache;

[0026] obtaining instructions of the related prefetch instruction that do not trigger a hit event from the primary instruction cache and backfilling the instructions to the prefetch module.

[0027] In one embodiment, backfilling the execution instruction and the related prefetch instruction to the prefetch module according to the hit condition of the addresses in the secondary cache further comprises:

[0028] controlling the primary instruction cache to backfill instructions of the related prefetch instruction that do not trigger a hit event to the secondary cache.

[0029] In one implementation, based on the address hit in the L2 cache, the execution instructions and their associated prefetch instructions are backfilled to the prefetch module, further comprising:

[0030] In response to the detection that the address of the instruction to be executed is in the L2 cache and triggers a miss event, the instruction to be executed and its related prefetch instructions are retrieved from the main instruction cache and backfilled into the prefetch module.

[0031] In one implementation, based on the address hit in the L2 cache, the execution instructions and their associated prefetch instructions are backfilled to the prefetch module, further comprising:

[0032] The main instruction cache is used to backfill the executed instructions and their associated prefetched instructions into the secondary cache.

[0033] In one implementation, after retrieving the execution instructions from the prefetch module, the method further includes:

[0034] The execution instructions are backfilled into the instruction buffer, and the execution instructions in the prefetch module are deleted after the backfilling is complete.

[0035] According to one aspect of this disclosure, an instruction extraction apparatus is provided, comprising:

[0036] The prefetch module is used to obtain the instructions backfilled from the secondary cache and backfill the instructions to the instruction cache, and is connected to the instruction fetch module through the first bypass;

[0037] The prefetch module is also used to obtain the instruction fetching request from the instruction fetch module, so that the instruction fetch module can fetch the instruction from the prefetch module through the first bypass.

[0038] In one implementation, the prefetch module is connected to the main instruction cache via a second bypass, and the prefetch module is also used to obtain the execution instructions and their related prefetch instructions in the main instruction cache via the second bypass.

[0039] According to another aspect of this disclosure, an electronic device for executing instruction extraction is provided, comprising:

[0040] At least one processor; and

[0041] The memory is communicatively connected to the at least one processor; wherein,

[0042] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the methods in any embodiment of this disclosure.

[0043] According to the technology disclosed herein, by using the prefetch module space to store the execution instructions and related prefetch instructions, the hit status of the execution instruction address can be detected simultaneously in the fetch cache and the prefetch module, and the execution instructions can be extracted based on the hit status. This is different from the conventional prefetch hit access that only performs prefetch hits on the fetch cache, which improves cache access efficiency, reduces power consumption, and allows the instructions in the prefetch module to be sent to the fetch pipeline in advance, thereby improving pipeline performance.

[0044] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0045] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0046] Figure 1 This is a flowchart illustrating a method for extracting execution instructions according to an embodiment of the present disclosure. Figure 1 ;

[0047] Figure 2 This is a flowchart illustrating a method for extracting execution instructions according to an embodiment of the present disclosure. Figure 2 ;

[0048] Figure 3 This is a schematic diagram of the structure of an execution instruction extraction device according to an embodiment of the present disclosure;

[0049] Figure 4 This is a block diagram of an electronic device used to implement the method for extracting execution instructions according to embodiments of the present disclosure. Detailed Implementation

[0050] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0051] Instruction prefetching can effectively reduce the waiting and refilling time when I-Cache instructions are missing, thereby improving the speed of front-end instruction fetching.

[0052] One implementation of instruction prefetching involves the instruction fetch module, also known as the instruction fetch pipeline, which is a working unit within the Central Processing Unit (CPU). The I-Cache stores data with high recent demand from the instruction fetch pipeline. The L2 Cache, with a larger storage capacity than the I-Cache, stores data with less recent demand. The Prefetch module, with a smaller storage space than the I-Cache, is used to generate the prefetch address sequence. The Bus Interface Unit (BIU) connects the CPU's main memory and the hard disk, storing all the data required by the CPU. The execution steps are as follows:

[0053] 1) The instruction fetch pipeline sends an access request carrying the address of the instruction to be executed to the I-Cache. If the instruction to be executed is hit in the I-Cache, the instruction to be executed is directly fetched and a new access request for the instruction to be executed is sent. If the instruction to be executed is not hit in the I-Cache, the address of the instruction to be executed is sent to the L2 Cache and the prefetch module.

[0054] 2) The prefetch module generates a prefetch address queue based on the addresses of missed execution instructions sent by the I-Cache. The prefetch address queue includes the addresses of prefetch instructions related to the missed execution instructions. At the same time, in order to avoid storing related prefetch instructions in the I-Cache, the prefetch module needs to access the I-Cache in reverse after generating the prefetch address queue. It removes the addresses of related prefetch instructions already stored in the I-Cache from the prefetch address queue to avoid duplicate storage. Then, it sends a prefetch request to the L2Cache based on the prefetch address queue.

[0055] 3) Upon receiving an address where an instruction was missed and a prefetch request, the L2 Cache, if it finds a match in its own memory, directly returns the corresponding instruction to the I-Cache / prefetch module. If the address is missed, it sends an access request to the BIU to search for the corresponding instruction in the CPU's main memory. Then, the L2 Cache refills the instruction to the I-Cache and refills the prefetch address queue with the corresponding instruction.

[0056] 4) After receiving the backfill execution instruction, the prefetch module returns prefetch data to the I-Cache, and the instruction fetch pipeline retrieves the execution instruction from the I-Cache and sends an access request for the new execution instruction.

[0057] For the above execution steps, since the prefetched instruction addresses related to the executed instructions need to be hit-checked in the I-Cache, the idle period or idle channel of the I-Cache needs to be used for access and judgment. When the I-Cache is a single channel, the instruction fetch pipeline also needs to be blocked to perform the instruction hit-check, which will affect the accuracy of the data after the block is released. When the I-Cache is multi-channel, it will increase the area and power consumption of the underlying implementation. At the same time, the existing instruction prefetching schemes all send the hit instruction to the I-Cache first and then pass it to the instruction fetch pipeline, which reduces the instruction fetching efficiency.

[0058] Based on this, this disclosure provides a method for extracting execution instructions that differs from traditional prefetching schemes. Figure 1 This is a flowchart illustrating a method for extracting execution instructions according to an embodiment of the present disclosure, including:

[0059] S110, Obtain the first extraction request, the first extraction request containing the address of the execution instruction;

[0060] S120, detects address hits in the instruction cache and prefetch module;

[0061] S130, extract and execute instructions based on the hit status.

[0062] For example, the instruction cache, serving as the fetch cache for the instruction fetch pipeline, can be an I-Cache. The first fetch request is an instruction retrieval request sent by the instruction fetch pipeline, containing the address of the instruction to be executed. In step S120, a hit detection for the executed instruction is performed in both the I-Cache and the prefetch module based on the address of the executed instruction. Subsequently, in step S130, the executed instruction can be retrieved according to the hit result; that is, as long as the executed instruction is stored in either the I-Cache or the prefetch module, it can be directly retrieved and used by the instruction fetch pipeline.

[0063] The PreFetch Buffer is implemented using a fully associative Entry Table, and an aging algorithm is used to select, use, and replace entries. Each entry can store I-Cache misses, prefetch instruction data, and cache instruction-related operations, such as the Prefetch.i instruction and data in RISC-V.

[0064] The method described in the above embodiments utilizes the space of the prefetch module to store the execution instructions and related prefetch instructions. There is no need to refill the prefetch instructions into the I-Cache. The hit status of the execution instruction address can be detected simultaneously in the instruction cache and the prefetch module, and the execution instructions can be extracted based on the hit status. This is different from the conventional prefetch hit access that only performs prefetch hits on the instruction fetch cache. It improves cache access efficiency, reduces power consumption, and can send the instructions in the prefetch module to the instruction fetch pipeline in advance, thereby improving pipeline performance.

[0065] In one implementation, step S130 includes:

[0066] In response to the detection of a miss event in the instruction buffer and a hit event in the prefetch module, the execution instruction is retrieved from the prefetch module.

[0067] Understandably, if the instruction cache, i.e., the I-Cache, does not detect the instruction to be executed, but the prefetch module does, the instruction fetch pipeline can bypass the I-Cache and directly fetch the instruction to be executed from the prefetch module, thereby reducing the waiting time of the instruction fetch pipeline and improving access efficiency.

[0068] More preferably, if a miss event is triggered in the instruction register and a hit event is triggered in the prefetch module, step S130 further includes:

[0069] The control prefetch module backfills the execution instructions into the instruction buffer and deletes the execution instructions from the prefetch module after the backfilling is complete.

[0070] It is understandable that, since the prefetch module itself has a small storage space, in order to avoid the instruction fetch pipeline from reusing the same execution instruction, but the storage space of the prefetch module has already replaced it with the instruction corresponding to the new prefetch address queue, in addition to allowing the instruction fetch pipeline to directly fetch the execution instruction, the execution instruction can be backfilled into the I-Cache, and the execution instruction in the prefetch module can be deleted after the backfilling is completed to save storage space.

[0071] In one implementation, step S130 further includes:

[0072] In response to the detection of a hit event in both the instruction cache and the prefetch module, the instruction to be executed is retrieved from the instruction cache.

[0073] It is understandable that if both the I-Cache and the prefetch module detect the execution instruction, the I-Cache, as the instruction fetch cache, obviously has higher data transfer efficiency, so the execution instruction is fetched from the I-Cache.

[0074] More preferably, if a hit event is triggered in both the instruction register and the prefetch module, step S130 further includes:

[0075] Delete the execution instructions in the prefetch module.

[0076] Since the I-Cache already stores the execution instructions, duplicate instructions in the prefetch module can be deleted to save storage space, making it easier to directly call the instructions in the I-Cache when the execution instructions are retrieved next time.

[0077] In one implementation, step S130 further includes:

[0078] In response to the detection of a hit event in the instruction cache and a miss event in the prefetch module, the instruction to be executed is retrieved from the instruction cache.

[0079] Understandably, if an execution instruction is detected in the I-Cache but not in the prefetch module, the execution instruction can be directly retrieved from the I-Cache using the regular instruction prefetching mode, without requiring any other operations on the prefetch module.

[0080] In one implementation, such as Figure 2 As shown, step S130 further includes:

[0081] S201, in response to detecting a miss event in the instruction cache and a miss event in the prefetch module, the prefetch module is controlled to send a second fetch request to the secondary cache, the second fetch request containing the address of the execution instruction and its related prefetch instructions;

[0082] S202, based on the address hit in the L2 cache, fill the execution instructions and their related prefetch instructions back into the prefetch module;

[0083] S203, extract the execution instructions from the prefetch module.

[0084] For example, the prefetch instructions associated with the execution instruction represent instructions that the instruction fetch pipeline may use in the near future, and the addresses of the execution instructions and their associated prefetch instructions are the prefetch address queue calculated by the prefetch module. The secondary cache can be an L2 cache, which has a larger storage capacity than the I-Cache, and the instructions stored therein are less needed by the instruction fetch pipeline than those in the I-Cache. If no execution instruction is detected in either the I-Cache or the prefetch module, the prefetch module needs to send a second fetch request to the L2 cache containing the addresses of the execution instruction and its associated prefetch instructions. Based on the address hits detected in the L2 cache, the execution instruction and its associated prefetch instructions are then backfilled to the prefetch module so that the instruction fetch pipeline can retrieve the execution instruction or the next possible prefetch instruction from the prefetch module.

[0085] Using the method described in the above embodiments, when no execution instruction is detected in either the I-Cache or the prefetch module, the prefetch module can send a prefetch request to the L2 Cache. After the prefetch module obtains the execution instruction, it is directly fetched by the instruction fetch pipeline without needing to fill it back into the I-Cache and perform a hit check again, thus improving pipeline performance. Simultaneously, when generating the prefetch address queue, the prefetch module does not need to check whether certain addresses exist in the I-Cache, preventing blockage of pipelines containing addresses in the I-Cache and affecting normal instruction fetch pipeline efficiency. Furthermore, since the prefetch module does not need to fill the prefetched instruction back into the I-Cache, operations in the prefetch instruction flow are reduced; the prefetched instruction can be directly stored in the prefetch module. Based on the fact that the instruction fetch pipeline of this application accesses both the instruction cache and the prefetch module simultaneously, it does not affect the fetching operation of subsequent instructions that may contain prefetched instructions.

[0086] If the relevant prefetch instructions already exist in the aforementioned prefetch module, there is no need to generate the prefetch addresses of the existing relevant prefetch instructions.

[0087] In one implementation, step S202 includes:

[0088] In response to the detection that the addresses of the executed instructions and their associated prefetch instructions have all triggered a hit event in the L2 cache, the L2 cache is controlled to backfill the executed instructions and their associated prefetch instructions into the prefetch module.

[0089] Understandably, if the execution instruction and its related prefetch instructions are both detected as hits in the L2 Cache, the L2 Cache will be directly controlled to fill all the detected instructions back into the prefetch module for instruction pipeline retrieval.

[0090] In one implementation, step S202 further includes:

[0091] In response to the detection that the address of the executed instruction triggers a hit event in the L2 cache, and that the addresses of the related prefetch instructions of the executed instruction have not all triggered hit events in the L2 cache, the L2 cache is controlled to backfill the executed instruction and the instructions that have triggered hit events in the related prefetch instructions to the prefetch module;

[0092] Retrieve instructions from the main instruction cache that did not trigger a hit event from the relevant prefetch instructions and populate them back into the prefetch module.

[0093] For example, the main instruction cache can be the CPU main memory connected to the BIU. If an execution instruction is detected in the L2 Cache, but some related prefetch instructions are not detected, the L2 Cache can be controlled to first fill the execution instruction and the detected related prefetch instructions into the prefetch module so that the instruction fetch pipeline can fetch the execution instruction as soon as possible. At the same time, the BIU can obtain the undetected related prefetch instructions from the main instruction cache and fill them into the prefetch module so that the instruction fetch pipeline can use its related prefetch instructions after obtaining the execution instruction.

[0094] It is understandable that the addresses of the relevant prefetch instructions for the executed instructions may all be missed in the L2 cache. In this case, the L2 cache can be controlled to first backfill the executed instructions to the prefetch module, and the relevant prefetch instructions can be obtained from the main instruction cache through the BIU and backfilled to the prefetch module. This will not be elaborated here.

[0095] More preferably, if no relevant prefetch instruction for the executed instruction is detected in the L2 cache, or if only a partial detection of the relevant prefetch instruction is made, step S202 further includes:

[0096] The control master instruction cache will backfill instructions that did not trigger a hit event from the relevant prefetch instructions to the second-level cache.

[0097] Understandably, given the limited storage space of the prefetch module, prefetch instructions backed up to the prefetch module that are not fetched and used within a short period are likely to be overwritten by subsequent instructions. Therefore, controlling the BIU to backfill relevant prefetch instructions not detected in the L2 Cache to the L2 Cache can prevent situations where subsequent instruction fetch pipelines need to use relevant prefetch instructions, but the relevant prefetch instructions in the prefetch module have been replaced, thus requiring re-fetching from the CPU's main memory via the BIU. This reduces the waiting time for instruction fetch pipelines and improves instruction fetch efficiency.

[0098] In one implementation, step S202 further includes:

[0099] In response to the detection that the address of the instruction to be executed is in the L2 cache and triggers a miss event, the instruction to be executed and its related prefetch instructions are retrieved from the main instruction cache and backfilled into the prefetch module.

[0100] Understandably, if the execution instruction is not detected in the L2 Cache, it is necessary to obtain the execution instruction through the BIU and backfill it into the prefetch module.

[0101] More preferably, if no execution instruction is detected in the L2 cache, step S202 further includes:

[0102] The main instruction cache is used to backfill the executed instructions and their associated prefetched instructions into the secondary cache.

[0103] It is understandable that, similar to the aforementioned prefetch instruction backfilling to the L2 Cache, if the execution instruction is not stored in the L2 Cache, in addition to backfilling the execution instruction to the prefetch module, the execution instruction can also be backfilled to the L2 Cache at the same time. This is to avoid the subsequent instruction fetch pipeline reusing the same execution instruction, but the execution instruction in the prefetch module has been replaced, so it needs to be fetched again through the BIU. This can reduce the waiting time of the instruction fetch pipeline and improve the instruction fetch efficiency.

[0104] In one implementation, after step S203, the method further includes:

[0105] The execution instructions are backfilled into the instruction buffer, and the execution instructions in the prefetch module are deleted after the backfilling is complete.

[0106] It is understandable that after the execution instruction is backfilled into the prefetch module, similar to the situation where the execution instruction is not detected in the I-Cache but is detected in the prefetch module, in order to avoid the instruction fetch pipeline from reusing the execution instruction in the future, but the storage space of the prefetch module has replaced it with the instruction corresponding to the new prefetch address queue, the execution instruction can be backfilled into the I-Cache in addition to being directly fetched by the instruction fetch pipeline, and the execution instruction in the prefetch module can be deleted after the backfilling is completed to save storage space.

[0107] In another implementation, after step S203, the method further includes:

[0108] The execution instructions and their associated prefetch instructions are backfilled into the instruction buffer, and after backfilling is complete, the execution instructions and their associated prefetch instructions are deleted from the prefetch module.

[0109] Understandably, designers can calculate the prefetch queue rules based on their prefetch module design, evaluate the likelihood of related prefetch instructions being pipelined within a short period, and if the likelihood is high, backfill the related instructions along with the executed instructions to the I-Cache. Conversely, if the likelihood is low, there is no need to backfill the related prefetch instructions to the I-Cache; only the related prefetch instructions are stored in the L2 Cache. The specific range of backfilled instructions can be configured according to actual conditions and is not limited thereto.

[0110] Figure 3 This is a schematic diagram of an execution instruction extraction device according to an embodiment of the present disclosure, the device comprising:

[0111] The prefetch module is used to fetch instructions back to the L2 cache and back to the instruction cache (I-Cache), and is connected to the instruction fetch module through the first bypass;

[0112] The prefetch module is also used to obtain the instruction fetching request from the instruction fetch module, so that the instruction fetch module can fetch the instruction from the prefetch module through the first bypass.

[0113] The prefetch module is also connected to the main instruction cache via a second bypass. The prefetch module can also be used to retrieve the execution instructions and their related prefetch instructions from the main instruction cache via the second bypass.

[0114] More specifically, such as Figure 3 As shown, the prefetch module is connected to the BIU via a second bypass. When the prefetch address queue calculated by the prefetch module is not found in the L2 Cache, the prefetch module can directly obtain the instruction (including the execution instruction and its related prefetch instructions) corresponding to the prefetch address queue from the main instruction cache through the BIU.

[0115] In one implementation, such as Figure 3 As shown, the device may also include an I-Cache, an L2 Cache, a BIU, and an instruction fetch module. The functions of these modules are similar to those in the previous embodiments, and will not be described again here.

[0116] The execution steps of the instruction extraction device disclosed herein are as follows:

[0117] 1) The instruction fetch pipeline sends access requests carrying the addresses of the instructions to be executed to both the I-Cache and the prefetch module. If an instruction is hit in either of them, the method for fetching the instruction is determined based on the hit result:

[0118] a. If an instruction is hit in the I-Cache, the instruction is directly retrieved from the I-Cache. If the instruction is not hit in the prefetch module in this case, no action is required. If the instruction is hit in the prefetch module, the instruction is deleted from the prefetch module.

[0119] b. If the instruction to be executed is not hit in the I-Cache but is hit in the prefetch module, the instruction fetch pipeline retrieves the instruction to be executed from the prefetch module, and at the same time controls the prefetch module to backfill the instruction to the I-Cache. After the backfill is completed, the instruction to be executed is deleted from the prefetch module.

[0120] 2.1) If no instruction is found in either the I-Cache or the prefetch module, the control prefetch module generates a prefetch address queue based on the address of the missed instruction. This queue includes the address of the missed instruction and the addresses of related prefetch instructions. Then, a prefetch request is sent to the L2 Cache based on the prefetch address queue, and the instruction fetching method is determined according to the L2 Cache's hit rate in the prefetch address queue.

[0121] a. If the prefetch address queue is fully hit in the L2 Cache, then control the L2 Cache to backfill the executed instructions and their related prefetch instructions to the prefetch module;

[0122] b. If the prefetch address queue is not fully hit in the L2 Cache, the L2 Cache can be controlled to backfill the hit instructions to the prefetch module. At the same time, the BIU can search for the missing instructions in the main instruction cache and control the BIU to directly backfill the missing instructions to the prefetch module. Additionally, the BIU can be controlled to backfill the missing instructions to the L2 Cache.

[0123] 2.2) After the execution instructions and their related prefetch instructions are backfilled into the prefetch module, the instruction fetch pipeline extracts the execution instructions from the prefetch module. At the same time, the prefetch module can be controlled to backfill the execution instructions into the I-Cache and delete the execution instructions in the prefetch module after the backfilling is completed.

[0124] 3) After successfully fetching the instruction to be executed, the instruction fetch pipeline sends access requests for the new instruction to the I-Cache and the prefetch module.

[0125] The specific settings and implementation methods of the embodiments of this application have been described above from different perspectives. The following beneficial effects can be achieved by using the methods provided in the above embodiments:

[0126] (1) It can detect the hit status of the execution instruction address in both the fetch cache and the prefetch module at the same time, and extract the execution instruction based on the hit status. Unlike the traditional method of only being able to obtain the execution instruction through the fetch cache or filling the execution instruction back into the fetch cache, it makes full use of the storage space of the prefetch module, improves the cache access efficiency, reduces power consumption, and can send the instructions in the prefetch module to the fetch pipeline in advance, thus improving the pipeline performance.

[0127] (2) The instructions required by the prefetch module can be obtained directly from the main instruction cache through the BIU. There is no need for the BIU to first fill the L2 Cache and then the L2 Cache to fill the prefetch module. This can further improve the speed of instruction fetching and execution in the pipeline and improve the transmission efficiency of the entire pipeline.

[0128] (3) Since the instruction fetch cache and the prefetch module can be accessed simultaneously and duplicate parts between them can be removed, the prefetch module does not need to visit the I-Cache to check the address when generating the prefetch address queue. Therefore, it does not block the operation of the instruction fetch pipeline, nor does it require a larger area or higher power consumption to implement the multi-channel I-Cache operation.

[0129] Figure 4 A structural block diagram of an electronic device according to an embodiment of this application is shown. Figure 4As shown, the electronic device includes a memory 410 and a processor 420, wherein the memory 410 stores instructions executable on the processor 420. When the processor 420 executes these instructions, it implements the method for identifying lane edges as described in the above embodiments. The number of memories 410 and processors 420 can be one or more. This electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present application described and / or claimed herein.

[0130] The electronic device may also include a communication interface 430 for communicating with external devices and exchanging data. The devices are interconnected using different buses and can be mounted on a common motherboard or otherwise as needed. The processor 420 can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In other embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). The bus can be divided into address buses, data buses, control buses, etc. For ease of illustration, Figure 4 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0131] Optionally, in a specific implementation, if the memory 410, processor 420 and communication interface 430 are integrated on a single chip, the memory 410, processor 420 and communication interface 430 can communicate with each other through an internal interface.

[0132] It should be understood that the aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. General-purpose processors can be microprocessors or any conventional processor. It is worth noting that the processor can be a processor supporting Advanced Reduced Instruction Set Machines (ARM) architecture.

[0133] This application provides a computer-readable storage medium (such as the memory 410 described above) that stores computer instructions, which, when executed by a processor, implement the method provided in this application.

[0134] Optionally, memory 410 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device for recognizing lane edges, etc. Furthermore, memory 410 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory 410 may optionally include memory remotely generated relative to processor 420, which can be connected to the electronic device for recognizing lane edges via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0135] Computer-readable media include both permanent and non-permanent, removable and non-removable media that can store information by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other physical classes of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage media, or any other non-transferable media that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include non-transitory computer-readable media, such as modulated data signals and carrier waves.

[0136] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0137] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of performing an instruction fetch, the method comprising: The method comprises: acquiring a first fetch request sent by a fetch pipeline, the first fetch request containing an address of an execution instruction; detecting a hit condition of the address in an instruction cache and a prefetch module, the instruction cache being a fetch cache of the fetch pipeline, and the prefetch module storing the execution instruction; in response to detecting a miss event triggered in the instruction cache and a hit event triggered in the prefetch module, fetching the execution instruction from the prefetch module so that the fetch pipeline directly acquires and uses the execution instruction.

2. The method of claim 1, wherein, The method of fetching the execution instruction according to the hit condition further comprises: controlling the prefetch module to backfill the execution instruction to the instruction cache and deleting the execution instruction in the prefetch module after the backfilling is completed.

3. The method of claim 1, wherein, The method of fetching the execution instruction according to the hit condition further comprises: in response to detecting a hit event triggered in the instruction cache and a hit event triggered in the prefetch module, fetching the execution instruction from the instruction cache.

4. The method of claim 3, wherein, The method of fetching the execution instruction according to the hit condition further comprises: deleting the execution instruction in the prefetch module.

5. The method of claim 1, wherein, The method of fetching the execution instruction according to the hit condition further comprises: in response to detecting a hit event triggered in the instruction cache and a miss event triggered in the prefetch module, fetching the execution instruction from the instruction cache.

6. The method of claim 1, wherein, The method of fetching the execution instruction according to the hit condition further comprises: in response to detecting a miss event triggered in the instruction cache and a miss event triggered in the prefetch module, controlling the prefetch module to send a second fetch request to a secondary cache, the second fetch request containing an address of the execution instruction and a related prefetch instruction of the execution instruction; backfilling the execution instruction and the related prefetch instruction to the prefetch module according to a hit condition of the address in the secondary cache; fetching the execution instruction from the prefetch module.

7. The method of claim 6, wherein, The method of backfilling the execution instruction and the related prefetch instruction to the prefetch module according to the hit condition of the address in the secondary cache further comprises: in response to detecting that the address of the execution instruction and the related prefetch instruction all trigger hit events in the secondary cache, controlling the secondary cache to backfill the execution instruction and the related prefetch instruction to the prefetch module.

8. The method of claim 6, wherein, The method of backfilling the execution instruction and the related prefetch instruction to the prefetch module according to the hit condition of the address in the secondary cache further comprises: in response to detecting that the address of the execution instruction triggers a hit event in the secondary cache and the address of the related prefetch instruction of the execution instruction does not all trigger hit events in the secondary cache, controlling the secondary cache to backfill the execution instruction and the related prefetch instruction that trigger hit events to the prefetch module; acquiring the instructions of the related prefetch instruction that do not trigger hit events from a main instruction cache and backfilling the instructions to the prefetch module.

9. The method of claim 8, wherein, The backfilling the execution instruction and the related prefetch instruction into the prefetch module according to the hit of the address in the secondary cache further comprises: controlling the backfilling of the execution instruction and the related prefetch instruction into the secondary cache in the main instruction cache.

10. The method of claim 6, wherein, The backfilling the execution instruction and the related prefetch instruction into the prefetch module according to the hit of the address in the secondary cache further comprises: in response to detecting that the address of the execution instruction triggers a miss event in the secondary cache, fetching the execution instruction and the related prefetch instruction from the main instruction cache and backfilling them into the prefetch module.

11. The method of claim 10, wherein, The backfilling the execution instruction and the related prefetch instruction into the prefetch module according to the hit of the address in the secondary cache further comprises: controlling the backfilling of the execution instruction and the related prefetch instruction into the secondary cache in the main instruction cache.

12. The method according to any one of claims 6-11, characterized in that, After the extracting the execution instruction from the prefetch module, further comprising: backfilling the execution instruction into the instruction cache and deleting the execution instruction in the prefetch module after completing the backfilling.

13. An apparatus for performing an extraction of instructions, characterized by: comprising: a prefetch module for fetching instructions backfilled from a secondary cache and backfilling instructions into an instruction cache, and connected with a fetch module through a first bypass; the prefetch module stores an execution instruction; the instruction cache is a fetch cache of a fetch pipeline, the prefetch module is further configured to fetch an execution instruction extraction request of the fetch module, so that the fetch module extracts the execution instruction from the prefetch module in response to detecting that a miss event is triggered in the instruction cache and a hit event is triggered in the prefetch module through the first bypass, so that the fetch pipeline directly fetches and uses the execution instruction.

14. The apparatus of claim 13, wherein, The prefetch module is connected with a main instruction cache through a second bypass, and the prefetch module is further configured to: fetch the execution instruction and the related prefetch instruction in the main instruction cache through the second bypass.

15. An electronic device for performing instruction fetch, the electronic device comprising: comprising: at least one processor; and a memory connected in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-12.

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