Layout optimization methods, apparatus, equipment and computer-readable storage media

Abstract

This application provides a layout optimization method, apparatus, device, and computer-readable storage medium. The method includes: determining a multi-port cell to be optimized in the layout; the multi-port cell to be optimized is a multi-port cell with at least one timing violation path; the timing violation path is a timing path that violates timing requirements; splitting the multi-port cell to be optimized into multiple cells, and finding a target layout for the multiple cells in the layout; the target layout is a layout where all timing paths within and between the multiple cells satisfy the timing requirements; and outputting a layout with the target layout. This application can solve the timing problem of multi-port cells without disabling the multi-port cell in the layout, thereby reducing the number of multi-port cells that need to be split and reducing the number of cells and area overhead required during layout optimization.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a layout optimization method, apparatus, device, and computer-readable storage medium. Background Technology

[0002] In very large-scale integrated circuits, cells and metal lines account for the largest proportion.

[0003] For individual cells, during the physical design phase of a chip, various required cells can be retrieved from a pre-provided standard cell library and laid out to form the chip design layout. However, during the actual design process, if a certain type of cell in the layout is found to have excessive latency affecting timing, that cell will be disabled. Disabled cells are not allowed to be used in the layout design. In the designed layout, for some multi-port type cells (e.g., cells with multiple inputs and one output, cells with one input and multiple outputs, or cells with multiple inputs and multiple outputs), after being disabled, they are replaced by equivalent cells with fewer ports (i.e., splitting a multi-port type cell into multiple cells with fewer ports) to meet the logic requirements. However, this increases the number of cells and area overhead, and may even cause new congestion problems.

[0004] For metal traces, in practical design applications, the fan-out type is divided into single-fan-out and multi-fan-out. Among them, multi-fan-out metal traces have more associated timing paths, and therefore are more prone to timing problems compared to single-fan-out metal traces. Therefore, there is an urgent need to propose a scheme to optimize the timing of multi-fan-out metal traces while meeting design constraints. Summary of the Invention

[0005] The purpose of this application is to provide a layout optimization method, apparatus, device, and computer-readable storage medium to solve at least one of the problems mentioned above.

[0006] To address the problems existing in the cell disabling method in the background art, this application provides a layout optimization method, including: determining a multi-port cell to be optimized in the layout; the multi-port cell to be optimized is a multi-port cell with at least one timing violation path; the timing violation path is a timing path that violates timing requirements; splitting the multi-port cell to be optimized into multiple cells, and finding the target layout of the multiple cells in the layout; the target layout is a layout where all timing paths within and between the multiple cells satisfy the timing requirements; and outputting a layout with the target layout.

[0007] In the above implementation, instead of directly disabling multi-port cells with at least one timing violation path, the optimized layout is obtained by splitting multi-port cells with at least one timing violation path. Then, a target layout is found that ensures all timing paths within and between the split cells meet timing requirements. This way, for a given layout, it's not necessary to split all target type cells (target type refers to the type of multi-port cell to be optimized) in the layout; only multi-port cells with at least one timing violation path need to be split. This reduces the number of multi-port cells that need to be split, thereby reducing the number of cells and area overhead required during layout optimization, and thus reducing the risk of new congestion problems. For example, suppose a layout uses 100 A cells, and timing analysis reveals that 10 of these A cells have at least one timing violation path. In existing implementations, these A cells would be disabled, requiring all 100 A cells in the layout to be split. According to the solution in this application, only the 10 A cells with timing violation paths need to be split, which can effectively reduce the number of cells and area overhead required during the layout optimization process, thereby reducing the risk of causing new congestion problems.

[0008] Furthermore, any one of the plurality of units has only a first port or a second port; wherein, the first port is the port involved in the timing violation path; and the second port is the port other than the first port in the multi-port unit to be optimized.

[0009] In the above implementation process, when splitting the unit, the port involved in the timing violation path (i.e., the first port) and the port not involved in the timing violation path (i.e., the second port) will not exist in the same unit after splitting. This allows the unit with the first port to be adjusted mainly during the search for the target layout, while the unit with the second port does not need to be modified too much. This reduces the difficulty of finding the target layout and improves the search efficiency.

[0010] Further, the multi-port unit to be optimized is split into multiple units, and the target layout of the multiple units in the layout is found, including: splitting the multi-port unit to be optimized into multiple units according to the currently selected splitting method, and polling the different placements of the multiple units under the preset placement constraints until the current polled placement satisfies the target layout or reaches the preset polling termination condition; when the preset polling termination condition is reached, the next splitting method is taken as the new currently selected splitting method, and the above process is repeated; wherein, the combination of multiple units obtained by splitting with different splitting methods is different.

[0011] In the above implementation process, by polling various placement situations under different splitting methods, the target layout that makes all timing paths meet the timing requirements can be found, thereby quickly solving the timing problems of the multi-port units to be optimized in the layout, achieving the purpose of timing optimization and layout optimization.

[0012] Furthermore, in the different placements of the plurality of units, the timing violation path is a straight line and has the shortest distance among all timing paths.

[0013] In the above implementation process, by arranging the original timing violation paths as straight lines and minimizing their distance among all timing paths within and between the split units, the timing of the original timing violation paths can be regulated first. For other timing paths, since there were no timing violations originally, it indicates that these timing paths may still have some margin. Therefore, by adjusting the placement of units to adjust the situation of other timing paths, a target layout can be found that makes other timing paths compliant while ensuring that the original timing violations are resolved.

[0014] Furthermore, in different placement configurations of the plurality of units, at least one buffer is provided between two target units; wherein, the two target units are two units among the plurality of units that are connected and have insufficient signal driving force.

[0015] In the above implementation process, by adding at least one buffer between two connected units that have insufficient signal driving force, the signal driving force between the two target units can be improved, thereby ensuring that the signal driving capability between units in the obtained target layout can also meet the requirements.

[0016] Furthermore, in any placement scenario: if there are multiple buffer configurations that can meet the signal driving force design requirements between the two target units, then the buffer configuration that minimizes the total delay between the two target units shall be used for placement.

[0017] It is understandable that while buffers can enhance signal driving force, they introduce additional latency. In the above implementation, when there are multiple buffer configurations that can meet the signal driving force design requirements between two target units, using the buffer configuration that minimizes the total latency between the two target units can reduce the timing impact of buffer configurations and increase the probability of finding a target layout that meets the design requirements for all timing paths.

[0018] Furthermore, in any placement case: if there are multiple buffer configurations that minimize the total delay between the two target units, then the buffer configuration that minimizes the power consumption or area between the two target units shall be used for placement.

[0019] In the above implementation process, when there are multiple buffer settings that minimize the total delay between two target units, the buffer setting that minimizes the power consumption or area between the two target units can be used to minimize the power consumption and area of ​​the integrated circuit in the layout.

[0020] This application embodiment also provides a layout optimization apparatus, comprising: a determining module, configured to determine a multi-port unit to be optimized in the layout; the multi-port unit to be optimized is a multi-port unit with at least one timing violation path; the timing violation path is a timing path that violates timing requirements; a first processing module, configured to split the multi-port unit to be optimized into multiple units and find a target layout for the multiple units in the layout; the target layout is a layout in which all timing paths within and between the multiple units satisfy the timing requirements; and a first output module, configured to output a layout having the target layout.

[0021] To address the timing issues caused by multiple fan-out metal lines described in the background art, this application provides another layout optimization method for processing these issues. This layout optimization method includes:

[0022] The algorithm polls different reconfiguration methods for the multi-fan-out metal lines to be optimized until a target reconfiguration method is obtained that makes all timing paths of the multi-fan-out metal lines meet preset requirements. The reconfiguration method includes connecting the starting point of the multi-fan-out metal lines to at least two ending points of the multi-fan-out metal lines through at least one buffer. The timing path is the path from the starting point of the multi-fan-out metal lines to the ending points of the multi-fan-out metal lines. The algorithm outputs the layout after reconfiguring the multi-fan-out metal lines according to the target reconfiguration method.

[0023] In the above implementation process, different reconfiguration methods of the multi-fanout metal line to be optimized are polled. Each reconfiguration method includes connecting the starting point of the multi-fanout metal line to at least two ending points through at least one buffer. In this way, each reconfiguration method can reduce the load on the starting point of the multi-fanout metal line through the buffer. As the load on the starting point of the multi-fanout metal line is reduced, the delay between the starting point of the multi-fanout metal line and the original loads will also change accordingly (the delay to each load will be smaller, but by a smaller margin). Based on this, by polling the different reconfiguration methods of the multi-fanout metal line to be optimized, it may be possible to find a situation where all timing paths of the multi-fanout metal line meet the preset requirements. At this point, the timing problem caused by the multi-fanout metal line is solved.

[0024] Furthermore, among the different reconfiguration methods of the multiple fan-out metal lines: timing paths that violate timing requirements are not reconfigured, while timing paths that do not violate timing requirements are reconfigured.

[0025] In the above implementation process, after reorganizing the timing paths that do not violate the timing requirements, the delay of each timing path of the entire multi-fan-out metal line can be changed. It may be possible to find a target reorganization method that makes all timing paths of the multi-fan-out metal line meet the preset requirements, thereby solving the timing problems caused by the multi-fan-out metal line.

[0026] Furthermore, among the different reconfiguration methods of the multiple fan-out metal lines: timing paths that violate timing requirements are reconfigured, while timing paths that do not violate timing requirements are not reconfigured.

[0027] In the above implementation process, after reorganizing the timing paths that violate timing requirements, the timing problems of the timing paths that violate timing requirements can be effectively improved. Thus, it is highly likely that a target reorganization method can be found that makes all timing paths of the multi-fan-out metal lines meet the preset requirements, thereby solving the timing problems caused by the multi-fan-out metal lines.

[0028] Furthermore, in the different recombination methods of the multiple fan-out metal lines: recombination between any two or more timing paths.

[0029] In the above implementation process, after recombining any two or more timing paths, the delay of each timing path of the entire multi-fan-out metal line can be changed. It may be possible to find a target recombination method that makes all timing paths of the multi-fan-out metal line meet the preset requirements, thereby solving the timing problem caused by the multi-fan-out metal line.

[0030] Furthermore, among the different reassembly methods of the multiple fan-out metal lines: reassembly between timing paths that violate timing requirements, and reassembly between timing paths that do not violate timing requirements.

[0031] In the above implementation process, timing paths that violate timing requirements are reassembled, and timing paths that do not violate timing requirements are reassembled. That is, different types of timing paths are not reassembled with each other. This can reduce the risk that the path from the buffer to the end point of different timing paths will still have timing violations after timing paths that violate timing requirements and timing paths that do not violate timing requirements are reassembled together.

[0032] Furthermore, in any of the aforementioned reorganization methods, the buffer is positioned in a blank space of the layout.

[0033] In the above implementation process, by setting the buffer in an empty space on the layout, the impact on other parts of the layout can be reduced, avoiding the risk of causing other parts of the layout to have problems such as timing violations.

[0034] This application embodiment also provides a layout optimization device, including: a second processing module, configured to poll different reorganization methods of a multi-fan-out metal line to be optimized until a target reorganization method is obtained that makes all timing paths of the multi-fan-out metal line meet preset requirements; wherein, the reorganization method includes: connecting the starting point of the multi-fan-out metal line to at least two ending points of the multi-fan-out metal line through at least one buffer; the timing path is the path from the starting point of the multi-fan-out metal line to the ending point of the multi-fan-out metal line; and a second output module, configured to output the layout after reorganizing the multi-fan-out metal line according to the target reorganization method.

[0035] This application also provides an electronic device, including a processor and a memory; the processor is used to execute one or more programs stored in the memory to implement any of the above-described layout optimization methods.

[0036] This application also provides a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement any of the above-described layout optimization methods. Attached Figure Description

[0037] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A schematic flowchart illustrating a layout optimization method provided in an embodiment of this application;

[0039] Figure 2 This is a schematic diagram of the structure of a multi-port unit provided in an embodiment of this application;

[0040] Figure 3 A schematic diagram of the split structure of a multi-port unit provided in an embodiment of this application;

[0041] Figure 4 A flowchart illustrating a method for finding a target layout is provided in an embodiment of this application;

[0042] Figure 5 A flowchart illustrating another layout optimization method provided in this application embodiment;

[0043] Figure 6 A schematic diagram of a circuit structure with multiple fan-out metal lines provided in this application embodiment;

[0044] Figure 7 A schematic diagram of the structure of the first layout optimization device provided in the embodiments of this application;

[0045] Figure 8 A schematic diagram of the structure of the second layout optimization device provided in the embodiments of this application;

[0046] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0047] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0048] Example 1:

[0049] To address the issue that in actual design processes, when a certain type of multi-port unit in the layout is found to have excessive latency affecting timing, disabling that type of multi-port unit would require splitting and re-layouting all such multi-port units in the layout, increasing the number of units and area overhead, and potentially causing new congestion problems, this application provides a layout optimization method.

[0050] See also Figure 1 As shown, Figure 1 This is a flowchart illustrating the layout optimization method provided in the embodiments of this application, including:

[0051] S101: Identify the multi-port units to be optimized in the layout.

[0052] In this embodiment, the multi-port unit to be optimized refers to a multi-port unit with at least one timing violation path. The timing violation path refers to a timing path that violates timing requirements. In this embodiment, the multi-port unit refers to a unit with multiple input ports or multiple output ports, for example... Figure 2 The unit shown.

[0053] For example, with Figure 2 Taking the multi-port unit structure shown as an example, it has 8 input ports: A1, A2, B1, B2, C1, C2, D1, and D2, and an output port: ZN. There are 8 timing paths: A1 to ZN, A2 to ZN, B1 to ZN, B2 to ZN, C1 to ZN, C2 to ZN, D1 to ZN, and D2 to ZN. If timing path B1 to ZN violates timing requirements, then this multi-port unit is identified as a multi-port unit to be optimized, and timing path B1 to ZN is the timing violation path.

[0054] In this application embodiment, the designed layout can be analyzed using existing layout design or layout analysis tools to identify units in the published layout that have timing violations (i.e., violate timing requirements), and the multi-port units therein can be identified as multi-port units to be optimized.

[0055] S102: Split the multi-port unit to be optimized into multiple units and find the target layout of the multiple units in the layout.

[0056] It is understandable that replacement elements for multiport elements can be found in the standard element library, thus enabling the splitting of multiport elements. Figure 2 Taking the multi-port unit shown as an example, it can be split into four 2-input AND gate units and one 4-input NOR gate unit, or it can be split into three 2-input AND gate units and one multi-port unit consisting of a 2-input AND gate and a 4-input NOR gate, etc. There are many different ways to split a multi-port unit, as long as the corresponding unit exists in the standard unit library.

[0057] In this embodiment, when splitting multi-port units, the principle of minimizing the presence of ports involved in timing violation paths (denoted as the first port) and ports not involved in timing violation paths (denoted as the second port) in the split unit can be followed. This ensures that during the target layout search, since a unit will not simultaneously possess both the first and second ports, adjusting the position of a single unit will not simultaneously affect both the original timing violation path and the normal timing path, thus allowing for better control of timing impacts. Furthermore, since a unit will not simultaneously possess both the first and second ports, the search for the target layout can primarily focus on adjusting units with the first port, while units with the second port can be placed with minimal positional changes, thereby reducing the difficulty of finding the target layout and improving search efficiency.

[0058] In particular, in practical applications, there may be situations where, regardless of how the cells are split, both the first port and the second port must exist simultaneously. For example, for... Figure 2 As shown in the cell example, assuming timing paths B1 to ZN are timing violation paths, while B2 to ZN are normal timing paths, then regardless of how B1 and B2 are split, they must both exist in the same cell. In this case, the second port, which is indivisible from the first port, can also be considered the first port, and thus split according to the above principle. That is, for the previous example, B2 can also be considered the first port, thus splitting into multi-port cells.

[0059] It is understood that the target layout described in the embodiments of this application refers to a layout that ensures that the timing paths within each of the split units, as well as all timing paths between the split units, meet the timing requirements. Figure 3 For example, the unit is split into three 2-input AND gate units Q and one multi-port unit K consisting of a 2-input AND gate and a 4-input NOR gate. The output of each AND gate unit Q is connected to one input of the NOR gate in K; these connection paths are the timing paths between units. Furthermore, each split unit may also have timing paths within itself; for example, the path between the AND gate and the NOR gate in unit K is a timing path within that unit. In this embodiment, by finding a target layout that ensures all timing paths within and between the split units meet timing requirements, the timing violation problem in the original multi-port unit to be optimized can be solved.

[0060] In order to find the target layout of multiple units in the layout, in an optional embodiment of this application, one can refer to... Figure 4 As shown, the target layout is located through the following process:

[0061] S401: Divide the multi-port unit to be optimized into multiple units according to the currently selected splitting method, and poll the different placement of multiple units under the preset placement constraints until the current polled placement satisfies the target layout or reaches the preset polling termination condition.

[0062] In the embodiments of this application, different splitting methods can be defined. For example, based on the principle that the first port and the second port will not exist in the same unit after splitting, different splitting methods can be defined, either in descending order of splitting granularity or in ascending order of splitting granularity. For example... Figure 3 The granularity of the split shown is greater than splitting the unit into four 2-input AND gate units and one 4-input NOR gate unit.

[0063] In this embodiment, the preset placement constraints may include signal delay design requirements between units and the load size that a unit can connect to, as set in the layout design. In this embodiment, by writing unit position change programs and placement constraint judgment programs, the allowed placement positions of each unit in the layout can be automatically found, resulting in different placement scenarios. In this embodiment, after placement in one scenario, timing analysis software can be used to analyze the timing of the entire layout or the network containing the split units to determine whether the placement meets the target layout. If it does, proceed to step S402. If it does not, determine whether the preset polling termination condition has been met; if it has, proceed to step S403. If not, find the next placement scenario and repeat the above judgment.

[0064] It is understood that the preset polling termination conditions may include, but are not limited to, at least one of the following conditions: the number of polled placements reaches a preset threshold, or no new placement is found after a preset time.

[0065] S402: When the target layout is obtained through polling, proceed to step S103.

[0066] S403: When the preset polling termination condition is met, the next splitting method is taken as the new currently selected splitting method, and the process returns to step S401.

[0067] It is understandable that when the preset polling termination condition is reached, it means that the target layout could not be found under the currently selected splitting method. Therefore, the next splitting method can be used as the new currently selected splitting method to re-split the multi-port unit to be optimized, and then polling for different unit placement situations can be performed again.

[0068] It is understood that, in an optional embodiment of this application, during each placement of units based on preset placement constraints to form different placement situations, the original timing violation path can be fixed as a straight line with the shortest distance among all timing paths. For example, for... Figure 3 The decomposition method shown assumes that timing paths B1 to ZN are timing violation paths. First, timing paths B1 to ZN can be arranged as a straight line (i.e., cell K is arranged as a straight line), ensuring that its distance is the shortest among all timing paths. Then, cell Q is placed in different positions based on preset placement constraints. In this way, by arranging the original timing violation paths as straight lines and minimizing their distance among all timing paths within and between the decomposed cells, the timing within the original timing violation paths can be prioritized for standardization. For other timing paths, since there were no original timing violations, these paths may still have some margin. Therefore, by adjusting the cell placement, the situation of other timing paths can be adjusted. This allows for finding a target layout that ensures compliance for other timing paths while resolving the original timing violations.

[0069] Of course, in this embodiment, the original timing violation path may not be fixed as a straight line with the shortest distance among all timing paths. Instead, all units may be placed based on preset placement constraints to form different placement situations.

[0070] It is understandable that during the process of arranging cells in different positions, the distance between two cells may become too great due to changes in cell position, resulting in insufficient signal driving force between the two cells. Therefore, in this embodiment, at least one buffer can be set between two target cells to improve the signal driving force between the two target cells, thereby ensuring that the signal driving capability between cells in the obtained target layout also meets the requirements. The two target cells are: two cells among a plurality of cells that are connected and have insufficient signal driving force.

[0071] It is understood that, in the embodiments of this application, the methods for setting the buffer may include, but are not limited to:

[0072] Add a buffer at the midpoint between the two target units. If the signal driving force still does not meet the set requirements after adding one buffer, add two buffers at the third division point between the two target units. If the signal driving force still does not meet the set requirements after adding two buffers, add three buffers at the fourth division point between the two target units. And so on, adding n buffers at the (n+1)th division point between the two target units.

[0073] Alternatively, a buffer can be added at the midpoint between the two target units. If the signal driving force still does not meet the set requirements after adding a buffer, analyze whether the signal driving force of the path from the preceding target unit to the buffer meets the set requirements, and analyze whether the signal driving force of the path from the buffer to the following target unit meets the set requirements. If the signal driving force of a certain segment does not meet the set requirements, add another buffer at the midpoint of that segment, and re-analyze whether the signal driving force of each segment between the unit and the buffer, as well as between buffers, meets the set requirements.

[0074] It is understood that the above two methods of setting buffers are merely two feasible implementation methods exemplified in the embodiments of this application, and are not intended to limit this application.

[0075] In this embodiment, multiple buffer configuration methods can be used simultaneously to obtain various buffer configuration methods that meet the signal driving force design requirements. In this case, the buffer configuration method that minimizes the total delay between the two target units can be used, thereby reducing the timing impact of the buffer configuration and increasing the probability of finding a target layout that satisfies the design requirements for all timing paths.

[0076] If there are multiple buffer configurations that minimize the total delay between two target units, the buffer configuration that minimizes the power consumption or area between the two target units can be used to minimize the power consumption and area of ​​the integrated circuit in the layout.

[0077] It should be noted that in this embodiment, timing analysis of the current placement is performed only after the buffer is set up to determine whether the current polled placement meets the target layout, so as to take into account the impact of the buffer on timing.

[0078] It is understood that in the embodiments of this application, when changing the placement of units or adding buffers, blank areas in the layout are preferred for placement or addition in order to reduce the impact on other components in the layout.

[0079] S103: Output a layout with the target layout.

[0080] Once the target layout is found, a layout with the target layout can be output, thus optimizing the layout.

[0081] To facilitate understanding of the solutions in the embodiments of this application, the following will be used as examples. Figure 2 The unit shown illustrates an example scheme:

[0082] Assumption Figure 2If C1-ZN in the unit is a timing violation path, then the basic units involved in the timing violation path include C, E (OR gate), and F (NOT gate). Then all ports of C1, C2, E, and all ports of F are the first ports, and can be decomposed in the following way:

[0083] (1) C, E, F, A, B, D (6 independent units)

[0084] (2) C, E, F, A+B, D (A and B are combined into one unit)

[0085] (3) C, E, F, A, B+D (B and D are combined into one unit)

[0086] (4) C, E, F, A+D, B (A and D are combined into one unit)

[0087] (5) C, E, F, A+B+D (A, B and D are combined into one unit)

[0088] (6) C+E, F, A, B, D (C and E are combined into one unit)

[0089] (7) C+E, F, A+B, D (C and E are combined into one unit, and A and B are combined into one unit)

[0090] (8) C+E, F, A, B+D (C and E are combined into one unit, and B and D are combined into one unit)

[0091] (9) C+E, F, A+D, B (C and E are combined into one unit, and A and D are combined into one unit)

[0092] (10) C+E, F, A+B+D (C and E are combined into one unit, and A, B and D are combined into one unit)

[0093] (11) C+E+F, A, B, D (C, E, and F are combined into one unit)

[0094] (12) C+E+F, A+B, D (C, E, and F are combined into one unit, and A and B are combined into one unit)

[0095] (13) C+E+F, A, B+D (C, E, and F are combined into one unit, and B and D are combined into one unit)

[0096] (14) C+E+F, A+D, B (C, E, and F are combined into one unit, and A and D are combined into one unit)

[0097] (15) C+E+F, A+B+D (C, E, and F are combined into one unit, and A, B, and D are combined into one unit)

[0098] At this point, based on the first splitting method, keep C, E, and F on a straight line, and adjust the placement of A, B, and D under the preset placement constraints. For each adjustment, analyze the entire layout or the timing of the network containing the split units using timing analysis software to determine whether the placement satisfies the target layout. If satisfied, output the current layout. If not satisfied, determine whether the preset polling termination condition has been met. If not, adjust the next placement and then re-evaluate. If satisfied, based on the second splitting method, keep C, E, and F on a straight line, and adjust the placement of A+B and D under the preset placement constraints.

[0099] Repeat this process until the target layout is found, or until all splitting methods fail to find the target layout.

[0100] It is understandable that the order of selection of the above splitting methods can be set as needed, for example, from (1) to (15) or from (15) to (1).

[0101] It can also be understood that, in the embodiments of this application, the multi-port unit to be optimized can be any multi-port unit. Figure 2 The units shown are not intended to be limiting.

[0102] The layout optimization method provided in this application splits multi-port cells with at least one timing violation path, rather than directly disabling them. Then, it searches for a target layout that ensures all timing paths within and between the split cells meet timing requirements, resulting in an optimized layout. This approach addresses the timing issues of multi-port cells without requiring the splitting of all target-type cells (the type of the multi-port cell to be optimized). By splitting only multi-port cells with at least one timing violation path, the number of split multi-port cells is reduced, thereby decreasing the number of cells and area overhead required for layout optimization and reducing the risk of new congestion problems.

[0103] Example 2:

[0104] To address timing issues caused by multiple fan-out metal lines, this application provides a layout optimization method. See also... Figure 5 As shown, Figure 5 This is a flowchart illustrating the layout optimization method provided in the embodiments of this application, including:

[0105] S501: Poll the different recombination methods of the multi-fan-out metal lines to be optimized until the target recombination method is obtained so that all timing paths of the multi-fan-out metal lines meet the preset requirements.

[0106] In this application embodiment, the designed layout can be analyzed using existing layout design or layout analysis tools to identify multi-fanout metal lines in the published layout that have timing violations (i.e., violate timing requirements). These multi-fanout metal lines are the multi-fanout metal lines to be optimized.

[0107] In this embodiment of the application, the reassembly method includes: connecting the starting point of the multi-fan-out metal line to at least two ending points of the multi-fan-out metal line through at least one buffer. The timing path is the path from the starting point to the ending point of the multi-fan-out metal line.

[0108] For example, with Figure 6 Taking the circuit structure diagram shown as an example, there is a multi-fan-out line in the selected area. The starting point a corresponds to 6 output endpoints b, c, d, e, f, and g. Therefore, the timing paths are: path1: a->b, path2: a->c, path3: a->d, path4: a->e, path5: a->f, and path6: a->g.

[0109] In this embodiment, different reconfiguration methods of the multi-fanout metal line to be optimized are polled. Each reconfiguration method includes connecting the starting point of the multi-fanout metal line to at least two ending points through at least one buffer. In this way, each reconfiguration method can reduce the load on the starting point of the multi-fanout metal line through the buffer. As the load on the starting point of the multi-fanout metal line decreases, the delay between the starting point and the original loads will also change accordingly (the delay to each load will decrease, but by a smaller margin). Based on this, by polling the different reconfiguration methods of the multi-fanout metal line to be optimized, it may be possible to find a situation where all timing paths of the multi-fanout metal line meet preset requirements. This achieves the solution to the timing problems caused by the multi-fanout metal line.

[0110] For example, with Figure 6 For example, Figure 6In the given path, 'a' has loads of b, c, d, e, f, and g. Assuming a buffer E is connected between 'a' and b and c, and 'a' is connected to both b and c via E (i.e., to path1 and path2), then the load on 'a' becomes E, d, e, f, and g, while b and c become the load on E. This reduces the load on 'a', strengthens its signal driving capability, and allows for faster signal transmission from 'a'. The delays from 'a' to 'b', 'c', 'd', 'e', ​​'f', and 'g' are reduced to varying degrees, thus altering the timing of each timing path. Therefore, by using different reconfiguration methods with varying round-robin sequences, it may be possible to obtain a target reconfiguration method that ensures all timing paths of the multi-fanout metal line meet preset requirements, resolving the timing issues caused by the multi-fanout metal line.

[0111] In one alternative embodiment, among the different reconfiguration methods of the multi-fan-out metal lines: timing paths that violate timing requirements are not reconfigured, while timing paths that do not violate timing requirements are reconfigured.

[0112] For example, suppose Figure 6 If path2 and path5 violate the timing requirements, the following reassembly methods are possible:

[0113] (1) path2, path5, path1+path3, path4, path6 (path1 and path3 are recombined)

[0114] (2) path2, path5, path1+path4, path3, path6 (path1 and path4 are recombined)

[0115] (3) path2, path5, path1+path6, path3, path4 (path1 and path6 are recombined)

[0116] (4) path2, path5, path3+path4, path1, path6 (path3 and path4 are recombined)

[0117] (5) path2, path5, path3+path6, path1, path4 (path3 and path6 are recombined)

[0118] (6) path2, path5, path4+path6, path3, path4 (path4 and path6 are recombined)

[0119] (7) path2, path5, path1+path3+path4, path6 (recombination of path1, path3 and path4)

[0120] (8) path2, path5, path1+path3+path6, path4 (recombination of path1, path3 and path6)

[0121] (9) path2, path5, path1+path4+path6, path3 (recombination of path1, path4 and path6)

[0122] (10) path2, path5, path3+path4+path6, path1 (recombination of path3, path4 and path6)

[0123] (11) path2, path5, path1+path3+path4+path6 (recombination of path1, path3, path4 and path6)

[0124] Since timing paths that do not violate timing requirements are generally considered to have a certain timing margin, after reorganizing timing paths that do not violate timing requirements, the delay of each timing path of the entire multi-fan-out metal line can be changed without introducing new timing violations as much as possible. Thus, it may be possible to find a target reorganization method that makes all timing paths of the multi-fan-out metal line meet the preset requirements, thereby solving the timing problems caused by the multi-fan-out metal line.

[0125] In another alternative embodiment, among the different reconfiguration methods of the multi-fan-out metal lines: timing paths that violate timing requirements are reconfigured, while timing paths that do not violate timing requirements are not reconfigured.

[0126] For example, suppose Figure 6 If path2, path3, and path5 violate the timing requirements, the following reassembly methods are possible:

[0127] path2+path3, path5, path1, path4, path6;

[0128] path2+path5, path3, path1, path4, path6;

[0129] path3+path5, path2, path1, path4, path6;

[0130] path2+path3+path5, path1, path4, path6.

[0131] In this way, after reassembling the timing paths that violate timing requirements, the timing problems of the timing paths that violate timing requirements can be effectively improved. Thus, it is highly likely that a target reassembly method can be found that makes all timing paths of multi-fan-out metal lines meet the preset requirements, thereby solving the timing problems caused by multi-fan-out metal lines.

[0132] In another alternative embodiment, among the different reconfiguration methods of the multi-fan-out metal lines: timing paths that violate timing requirements can be reconfigured, and timing paths that do not violate timing requirements can be reconfigured.

[0133] For example, suppose Figure 6 If path2 and path5 violate the timing requirements, the following reassembly methods are possible:

[0134] path2+path5, path1+path3, path4, path6;

[0135] path2+path5, path1+path4, path3, path6;

[0136] path2+path5, path1+path6, path3, path4;

[0137] path2+path5, path3+path4, path1, path6;

[0138] path2+path5, path3+path6, path1, path4;

[0139] path2+path5, path4+path6, path3, path1;

[0140] path2+path5, path1+path3+path4, path6;

[0141] path2+path5, path1+path3+path6, path4;

[0142] path2+path5, path1+path4+path6, path3;

[0143] path2+path5, path3+path4+path6, path1;

[0144] path2+path5, path1+path3+path4+path6.

[0145] Timing paths that violate timing requirements are reassembled, while timing paths that do not violate timing requirements are reassembled. In other words, different types of timing paths are not reassembled with each other. This can reduce the risk that the path from the buffer to the end point of different timing paths may still have timing violations after timing paths that violate timing requirements and timing paths that do not violate timing requirements are reassembled together.

[0146] In another alternative embodiment, the reorganization methods of the three alternative embodiments described above can be used simultaneously for polling in order to obtain the target reorganization method.

[0147] In another alternative embodiment, among the different reconfiguration methods of the multi-fan-out metal lines: reconfiguration can be performed between any two or more timing paths. That is, in addition to the reconfiguration methods described above, timing paths that violate timing requirements and timing paths that do not violate timing requirements can also be reconfigured.

[0148] In this embodiment of the application, when reorganizing, the buffer can be set in a blank position of the layout to reduce the impact on other parts of the layout and avoid the risk of causing other parts of the layout to have problems such as timing violations.

[0149] S502: Outputs the layout after reorganizing the multi-fan-out metal lines according to the target reorganization method.

[0150] Once the target reorganization method is found, the layout after reorganizing the multi-fan-out metal lines according to the target reorganization method can be output, thereby optimizing the layout.

[0151] It is understood that the solutions in this application are applicable to all types of circuit structures with multiple fan-out metal lines, and are not limited to... Figure 6 The circuit structure shown is shown.

[0152] The above solution reduces the load at the starting point of the multi-fan-out metal line by reorganizing the timing paths in the multi-fan-out metal line, thereby changing the delay between the starting point of the multi-fan-out metal line and the original loads, thus achieving the adjustment of the timing problem of the multi-fan-out metal line.

[0153] Example 3:

[0154] Based on the same inventive concept, this application also provides a layout optimization device 700 and a layout optimization device 800. Please refer to... Figure 7 and Figure 8 As shown, Figure 7 It shows the use of Figure 1 The layout optimization apparatus of the method shown Figure 8 It shows the use of Figure 5The illustrated method is a layout optimization apparatus. It should be understood that the specific functions of apparatus 700 and 800 are described above; to avoid repetition, detailed descriptions are omitted here. Apparatus 700 and 800 include at least one software function module that can be stored in memory or embedded in the operating system of apparatus 700 or 800 in the form of software or firmware. Specifically:

[0155] See Figure 7 As shown, the device 700 includes: a determining module 701, a first processing module 702, and a first output module 703. Wherein:

[0156] The determining module 701 is used to determine the multi-port unit to be optimized in the layout; the multi-port unit to be optimized is: a multi-port unit with at least one timing violation path; the timing violation path is: a timing path that violates timing requirements;

[0157] The first processing module 702 is used to split the multi-port unit to be optimized into multiple units and find the target layout of the multiple units in the layout; the target layout is: the layout in which all timing paths within and between the multiple units meet the timing requirements.

[0158] The first output module 703 is used to output a layout having the target layout.

[0159] In one feasible embodiment of this application, any one of the plurality of units has only a first port or a second port; wherein, the first port is the port involved in the timing violation path; and the second port is the port other than the first port in the multi-port unit to be optimized.

[0160] In one feasible embodiment of this application, the first processing module 702 is specifically used to: split the multi-port unit to be optimized into multiple units according to the currently selected splitting method, and poll the different placement situations of the multiple units under the preset placement constraints until the current polled placement situation satisfies the target layout or reaches the preset polling termination condition; when the preset polling termination condition is reached, the next splitting method is taken as the new currently selected splitting method, and the above process is repeated; wherein, the combination of multiple units obtained by different splitting methods is different.

[0161] In the above feasible implementation, among the different placements of the plurality of units, the timing violation path is a straight line and has the shortest distance among all timing paths.

[0162] In the above feasible embodiments, in different placements of the plurality of units, at least one buffer is provided between two target units; wherein, the two target units are: two units among the plurality of units that are connected and have insufficient signal driving force.

[0163] In the above feasible implementation, in any placement case: if there are multiple buffer setting methods that can meet the signal driving force design requirements between the two target units, then the buffer setting method that minimizes the total time delay between the two target units shall be adopted for placement.

[0164] In the above feasible implementation, in any placement case: if there are multiple buffer settings that minimize the total delay between the two target units, then the buffer setting that minimizes the power consumption or area between the two target units is adopted.

[0165] See Figure 8 As shown, the device 800 includes: a second processing module and a second output module. Wherein:

[0166] The second processing module is used to poll different reconfiguration methods of the multi-fan-out metal line to be optimized until a target reconfiguration method is obtained that makes all timing paths of the multi-fan-out metal line meet preset requirements; wherein, the reconfiguration method includes: connecting the starting point of the multi-fan-out metal line to at least two ending points of the multi-fan-out metal line through at least one buffer; the timing path is the path from the starting point of the multi-fan-out metal line to the ending point of the multi-fan-out metal line;

[0167] The second output module is used to output the layout after the multi-fan-out metal lines are reorganized according to the target reorganization method.

[0168] In one optional embodiment of this application, among the different reconfiguration methods of the multiple fan-out metal lines: timing paths that violate timing requirements are not reconfigured, while timing paths that do not violate timing requirements are reconfigured.

[0169] In one optional embodiment of this application, among the different reconfiguration methods of the multiple fan-out metal lines: timing paths that violate timing requirements are reconfigured, while timing paths that do not violate timing requirements are not reconfigured.

[0170] In one optional embodiment of this application, among the different recombination methods of the multiple fan-out metal lines, recombination occurs between any two or more timing paths.

[0171] In one optional embodiment of this application, among the different reconfiguration methods of the multiple fan-out metal lines: reconfiguration between timing paths that violate timing requirements, and reconfiguration between timing paths that do not violate timing requirements.

[0172] In any of the reorganization methods described in this application, the buffer is disposed in a blank position of the layout.

[0173] It should be understood that, for the sake of brevity, some of the content described in Embodiment 1 and Embodiment 2 will not be repeated in this embodiment.

[0174] Example 4:

[0175] This embodiment provides an electronic device, see [link / reference] Figure 9 As shown, it includes a processor 901 and a memory 902. Wherein:

[0176] The processor 901 is used to execute one or more programs stored in the memory 902 to implement the layout optimization method in Embodiment 1 or Embodiment 2 described above.

[0177] Understandable. Figure 9 The structure shown is for illustrative purposes only; the electronic device may also include components that are more advanced than those shown. Figure 9 The more or fewer components shown, or having the same Figure 9 Different configurations are shown. For example, the electronic device may also include a communication bus for communication between the processor 901 and the memory 902. As another example, the electronic device may also include information input ports, such as USB ports, network ports, etc.

[0178] In the embodiments of this application, the electronic device may be a device with data processing capabilities, such as a server or a computer, but this is not a limitation.

[0179] This embodiment also provides a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc., in which one or more programs implementing the above steps are stored. These one or more programs can be executed by one or more processors to implement the layout optimization method in Embodiment 1 or Embodiment 2. Further details will not be elaborated here.

[0180] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0181] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0182] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0183] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0184] In this article, "multiple" refers to two or more.

[0185] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method of layout optimization, comprising: The method comprises: determining a multi-port unit to be optimized in the layout; the multi-port unit to be optimized is a multi-port unit having at least one timing violation path; the timing violation path is a timing path violating a timing requirement; splitting the multi-port unit to be optimized into a plurality of units and searching for a target layout of the plurality of units in the layout; the target layout is a layout in which all timing paths within and between the plurality of units meet the timing requirement; outputting the layout having the target layout.

2. The layout-optimization method of claim 1, wherein, Any unit in the plurality of units has only a first port or a second port; wherein the first port is a port involved in the timing violation path; and the second port is a port other than the first port in the multi-port unit to be optimized.

3. The layout arrangement optimization method according to claim 1 or 2, wherein Splitting the multi-port unit to be optimized into a plurality of units and searching for a target layout of the plurality of units in the layout comprises: splitting the multi-port unit to be optimized into a plurality of units according to a currently selected splitting mode, and polling different placement situations of the plurality of units under preset placement constraint conditions until the currently polled placement situation meets the target layout or a preset polling termination condition is reached; when the preset polling termination condition is reached, taking a next splitting mode as a new currently selected splitting mode and repeating the above process; wherein the plurality of units obtained by different splitting modes are different in combination.

4. The layout-optimization method of claim 3, wherein, In different placement situations of the plurality of units, the timing violation path is a straight line and is the shortest in all timing paths.

5. The layout-optimization method of claim 3, wherein, In different placement situations of the plurality of units, at least one buffer is arranged between two target units; wherein the two target units are two units in the plurality of units having a connection relationship and insufficient signal driving force.

6. The layout-optimization method of claim 5, wherein, In any placement situation: if there are multiple buffer arrangement modes that can meet the signal driving force design requirement between the two target units, the buffer arrangement mode that minimizes the total delay between the two target units is adopted for placement.

7. The layout-optimization method of claim 6, wherein, In any placement situation: if there are multiple buffer arrangement modes that minimize the total delay between the two target units, the buffer arrangement mode that minimizes the power consumption or the area between the two target units is adopted for placement.

8. A layout arrangement optimization apparatus characterized by comprising: comprise: a determining module configured to determine a multi-port unit to be optimized in the layout; the multi-port unit to be optimized is a multi-port unit having at least one timing violation path; the timing violation path is a timing path violating a timing requirement; a first processing module configured to split the multi-port unit to be optimized into a plurality of units and search for a target layout of the plurality of units in the layout; the target layout is a layout in which all timing paths within and between the plurality of units meet the timing requirement; a first output module configured to output the layout having the target layout.

9. A method of layout optimization, characterized by, comprise: The different recombination manners of the multi-fan-out metal line to be optimized are polled until a target recombination manner is obtained, in which all timing paths of the multi-fan-out metal line meet preset requirements; each of the different recombination manners comprises connecting a start point of the multi-fan-out metal line to at least two end points of the multi-fan-out metal line through at least one buffer; and the timing path is a path from the start point of the multi-fan-out metal line to the end point of the multi-fan-out metal line. Output a layout in which the multi-fan-out metal line is recombined according to the target recombination manner.

10. The layout-optimization method of claim 9, wherein, In the different recombination manners of the multi-fan-out metal line: Timing paths that violate timing requirements are not recombined, and timing paths that do not violate timing requirements are recombined.

11. The layout-optimization method of claim 9, wherein, In the different recombination manners of the multi-fan-out metal line: Timing paths that violate timing requirements are recombined, and timing paths that do not violate timing requirements are not recombined.

12. The layout-optimization method of claim 9, wherein, In the different recombination manners of the multi-fan-out metal line: Any two or more timing paths are recombined.

13. The layout-optimization method of claim 12, wherein, In the different recombination manners of the multi-fan-out metal line: Timing paths that violate timing requirements are recombined, and timing paths that do not violate timing requirements are recombined.

14. The layout-optimization method of any one of claims 9-13, wherein, In any of the recombination manners, the buffer is arranged at a blank position of the layout.

15. A layout arrangement optimization apparatus characterized by comprising: Comprise: A second processing module is configured to poll different recombination manners of a multi-fan-out metal line to be optimized until a target recombination manner is obtained, in which all timing paths of the multi-fan-out metal line meet preset requirements; each of the different recombination manners comprises connecting a start point of the multi-fan-out metal line to at least two end points of the multi-fan-out metal line through at least one buffer; and the timing path is a path from the start point of the multi-fan-out metal line to the end point of the multi-fan-out metal line. A second output module is configured to output a layout in which the multi-fan-out metal line is recombined according to the target recombination manner.

16. An electronic device, comprising: Comprise: A processor and a memory; The processor is configured to execute one or more programs stored in the memory to implement the method in any one of claims 1-7, 9-14.

17. A computer-readable storage medium, characterized in that, The computer readable storage medium stores one or more programs, which can be executed by one or more processors to implement the method in any one of claims 1-7, 9-14.

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