Integrated circuit elements in a stacked quantum computing device

Abstract

A stacked quantum computing device includes: a first chip including superconducting qubits, wherein the superconducting qubits include a superconducting quantum interference device (SQUID) region, a control region, and a readout region; and a second chip bonded to the first chip, wherein the second chip includes a first control element overlapping the SQUID region, a second control element laterally shifted from the control region and not overlapping the control region, and a readout device overlapping the readout region.

Description

[0001] This application is a divisional application of the invention patent application filed on December 12, 2017, with application number 201780088359.0 and title "Integrated Circuit Elements in Stacked Quantum Computing Devices". Technical Field

[0002] This disclosure relates to integrated circuit elements in a stacked quantum computing device. Background Technology

[0003] Quantum computing is a relatively new method of computation that utilizes quantum effects such as the superposition of fundamental states and entanglement to perform certain computations more efficiently than classical digital computers. Unlike digital computers, which store and manipulate information in bits (e.g., "1" or "0"), quantum computing systems can manipulate information using qubits. A qubit can refer to a quantum device that enables a superposition of multiple states (e.g., data in both "0" and "1" states) and / or to a superposition of the data itself in multiple states. In conventional terminology, a superposition of "0" and "1" states in a quantum system can be represented, for example, as α|0> + β|1>. The "0" and "1" states of a digital computer are analogous to the |0> and |1> fundamental states of a qubit, respectively. 2 represents the probability that a qubit is in the |0> state, while the value |β| represents the probability that the qubit is in the |0> state. 2 This represents the probability that a qubit is in the |1> fundamental state. Summary of the Invention

[0004] Generally, in some aspects, this disclosure relates to one or more devices, the devices including a first chip and a second chip, the first chip including a superconducting quantum bit, wherein the superconducting quantum bit includes a superconducting quantum interference device (SQUID) region, a control region and a readout region, and the second chip is bonded to the first chip, wherein the second chip includes a first control element overlapping the SQUID region, a second control element laterally shifted from the control region and not overlapping the control region, and a readout device overlapping the readout region.

[0005] Implementations of the device may include one or more of the following features. For example, in some implementations, the readout device includes a resonator element and a pad element, wherein the resonator element is electrically coupled to the pad element, and the pad element overlaps with the readout region, while the resonator does not overlap with the readout region.

[0006] In some implementations, the pad elements are symmetrically aligned with the readout area.

[0007] In some implementations, the surface area of ​​the readout region facing the second chip and overlapping with the pad elements is smaller than the surface area of ​​the pad elements facing the first chip.

[0008] In some implementations, the pad elements are operable to be capacitively coupled to the readout region.

[0009] In some implementations, the first chip includes a superconducting ground plane whose edge is aligned with the control region of the superconducting qubit, such that the edge includes a recessed region in which a portion of the superconducting ground plane is removed, and the control element is aligned above the recessed region.

[0010] In some implementations, the surface area of ​​the second control element facing the first chip is smaller than the surface area of ​​the recessed region facing the second chip.

[0011] In some implementations, the second control element is operable to be capacitively coupled to the control region.

[0012] In some implementations, the second element can be operated to excite the superconducting quantum bit.

[0013] In some embodiments, the first control element includes a bias coil, wherein the bias coil includes a layer of superconducting material arranged in a ring, and wherein the SQUID region includes SQUIDs arranged in a ring.

[0014] In some embodiments, the annulus includes an inner annular edge and an outer annular edge, wherein the inner annular edge is aligned within the inner region of the annulus, and the outer annular edge is aligned outside the inner region of the annulus.

[0015] In some implementations, the lateral distance between the inner annular edge and the edge of the annulus defining the inner region of the annulus is at least 2 micrometers, and the lateral distance between the outer annular edge and the edge of the annulus defined by the inner region of the annulus is at least 2 micrometers.

[0016] In some embodiments, the annulus includes an inner annular edge and an outer annular edge, wherein the outer annular edge is aligned within the inner region of the annulus.

[0017] In some implementations, the lateral distance between the outer annular edge and the edge of the annular ring defining the inner region of the ring is at least 2 micrometers.

[0018] In some implementations, the first control element is operable to tune the superconducting quantum bit.

[0019] In some implementations, the first control element is operable to be inductively coupled to the SQUID region.

[0020] In some implementations, the first chip bumps are bonded to the second chip.

[0021] In some implementations, a gap exists between the first chip and the second chip, wherein the height of the gap between the first chip and the second chip is 1-10 micrometers.

[0022] In some implementations, the first control element, the second control element, and the readout device comprise a superconducting material.

[0023] In some implementations, superconducting qubits are transmon qubits, flux qubits, or gmon qubits.

[0024] Generally, in some aspects, the subject matter of this disclosure can be embodied in methods of operating a quantum computing system, wherein operating the quantum computing system includes operating a quantum computing device. The quantum computing device includes, for example, a first chip including superconducting qubits and a second chip bonded to the first chip, wherein the superconducting qubits include a SQUID region, a control region, and a readout region, wherein the second chip includes a first control element overlapping the SQUID region, a second control element laterally shifted from the control region and not overlapping the control region, and a readout device overlapping the readout region. Operating the quantum computing device may include coherently processing quantum information stored in the superconducting qubits using the quantum computing device. Operating the quantum computing system may also include obtaining an output from the quantum computing system and processing the output using classical circuit elements.

[0025] According to other aspects, an apparatus is provided comprising: a first chip including qubits; and a second chip bonded to the first chip, the second chip including a readout device, wherein the readout device includes a first readout element at a first end of the readout device and a second readout element at a second end of the readout device, wherein the first readout element directly overlaps with the qubits, and wherein the second readout element is laterally displaced from the qubits and does not directly overlap with the qubits.

[0026] According to other aspects, an apparatus is provided comprising: a first chip including qubits, wherein the qubits include a first control region and a second control region, the first control region including a superconducting quantum interference device (SQUID); and a second chip bonded to the first chip, the second chip including a first control element and a second control element, wherein the first control element is arranged to be inductively coupled to the first control region, and wherein the second control element is arranged to be capacitively coupled to the second control region.

[0027] Specific embodiments of the subject matter described herein can be implemented to achieve one or more of the following advantages. For example, in some embodiments, the devices and methods disclosed herein increase chip misalignment tolerance to maintain qubit coherence and qubit coupling strength while reducing stray coupling effects in stacked quantum computing devices (e.g., flip-chip architectures). Additionally, in some embodiments, the devices and methods disclosed herein allow for increased qubit density (e.g., from a one-dimensional chain of superconducting qubits to a two-dimensional array of superconducting qubits) and / or increased qubit coupling through 3D integration. Furthermore, in some embodiments, the devices and methods disclosed herein can reduce energy loss and dissipation in quantum circuit elements that may be caused by deposited dielectric materials.

[0028] Details of one or more embodiments are set forth in the accompanying drawings and the following description. Other features and advantages will be apparent from the specification, drawings, and claims. Attached Figure Description

[0029] Figure 1 This is a schematic diagram illustrating an example of a two-dimensional qubit array.

[0030] Figure 2 This is a schematic diagram illustrating an example of a stacked quantum computing device including a first chip and a second chip.

[0031] Figures 3A-3B This is a schematic diagram showing different views of an example stacked quantum computing device.

[0032] Figure 3C This is a schematic diagram showing a top view of the second chip of a stacked quantum computing device.

[0033] Figure 4A This is a schematic diagram showing a top view of the readout device formed on the second chip.

[0034] Figure 4B This is a schematic top view showing the readout region of the superconducting quantum bit formed on the first chip.

[0035] Figure 4C This is a schematic top view of a second chip, which is aligned with the readout device of the second chip above the readout area of ​​the first chip.

[0036] Figure 5A This is a schematic diagram showing a top view of the first control element formed on the second chip.

[0037] Figure 5B This is a schematic top view of the superconducting quantum interference device (SQUID) region of the superconducting qubits on the first chip.

[0038] Figure 5CThis is a schematic top view of a second chip, which is aligned with the first control element of the second chip above the SQUID area of ​​the first chip.

[0039] Figure 6A This is a schematic diagram showing a top view of a second control element formed on a second chip.

[0040] Figure 6B This is a schematic top view showing the control region of the superconducting quantum bit and the recessed region on the first chip.

[0041] Figure 6C This is a schematic top view of a second chip, which is aligned with the second control element of the second chip above the recessed area of ​​the first chip.

[0042] Figure 7 This is an optical micrograph showing a top view of the stacked quantum computing device, from the second chip to the first chip. Detailed Implementation

[0043] Quantum computing requires the coherent processing of quantum information stored in qubits (qubits) of a quantum computer. Superconducting quantum computing is a promising implementation of quantum computing technology in which the quantum computing circuit elements are partially formed from superconducting materials. Superconducting quantum computers are typically multi-stage systems, with only the first two stages used as the computational basis. In some implementations, the quantum circuit elements (e.g., quantum computing circuit elements), such as qubits, operate at very low temperatures, thereby achieving superconductivity, and thus thermal fluctuations do not cause transitions between energy levels. Additionally, it may be preferred that the quantum computing circuit elements operate with low energy loss and dissipation (e.g., the quantum computing circuit elements exhibit a high quality factor, Q). Low energy loss and dissipation can help avoid, for example, quantum decoherence.

[0044] In some types of quantum computing processors, such as quantum annealers, the qubits of the quantum processor are operably coupled together in a controllable manner, such that the quantum state of each qubit affects the corresponding quantum state of the other qubits coupled with it. Depending on the processor design, the chosen architecture may limit the density and total number of qubits available for coupling, and thus limit the processor's ability to execute complex problems requiring a large number of qubits. Furthermore, in some quantum computing designs, qubits may suffer from energy loss and decoherence due to interactions with two-level systems (TLS). Two-level systems (TLS) are material defects inherent in a dielectric substrate, arising from tunneling effects between two configurations of atoms in the dielectric substrate, or, in some implementations, material defects inherent at the interfaces between material layers. For example, in quantum computers using qubits formed from superconducting materials, the presence of detrimental non-superconducting materials, such as deposited dielectrics, classical circuit elements through which the quantum computer communicates, and the connections between classical and quantum circuit elements, can lead to increased decoherence. To increase qubit density and expand the number of qubits available for coupling in quantum processors (such as quantum annealers with superconducting quantum circuit elements), 3D integration can be used to construct the processor and associated circuit elements. That is, instead of fabricating the quantum circuit elements of the processor in a single plane of a chip extending in one and / or two dimensions (e.g., the x and / or y directions), the quantum circuit elements can also be formed in multiple chips coupled together in a third dimension (e.g., the z direction). One way to achieve 3D integration without introducing lossy processing / dielectrics is to couple the chips using bump bonding, where the chips are connected to each other by, for example, superconducting bump bonding. In some embodiments, in addition to the physical coupling of the chips, bump bonding can be used to electrically couple components from different chips together. Alternatively, bump bonding can be used alone to physically couple different chips together. By using superconducting bump bonding for coupling, it is possible to achieve a reduction in energy loss and decoherence that would otherwise occur in lossy non-superconducting materials.

[0045] Alignment is a challenge in the fabrication of stacked quantum computing devices, particularly the alignment between interacting elements located on individual chips, which can be electrically and mechanically connected using bump bonding.

[0046] This disclosure relates to apparatus and methods for coupling stacked quantum computing devices. In particular, in some embodiments, this disclosure relates to providing a plurality of chips arranged in a stack, wherein a first chip in the stack includes a two-dimensional array of qubits, and at least a second chip in the stack includes control elements for coupling the qubits to the first chip.

[0047] Figure 1 This is a schematic diagram illustrating an example of a two-dimensional array 100 of superconducting qubits. The array 100 of superconducting qubits can be part of a quantum computing system (e.g., a quantum annealer) for performing quantum computing operations. Figure 1 In the example shown, each superconducting qubit is an xmon qubit, typically represented in a "plus" shape with four arms. Qubit 100 can include, but is not limited to, other types of qubits such as flux qubits, transmon qubits, and gmon qubits. Figure 1 A four-by-four array 100 of superconducting qubits is depicted, but any number of qubits can be implemented in a one-dimensional (1D) or two-dimensional (2D) array. In some implementations, quantum computing systems operating arrays comprising superconducting qubits (such as array 100 of superconducting qubits) require the superconducting qubits of the array to be coupled together. For example, nearest neighboring qubits 102a and 102b can be coupled to each other via their adjacent arms. Similarly, each of the inner qubits in a 2D array (e.g., qubits 102c and 102d) can be directly coupled to four nearest neighboring qubits. For example, qubit 102c can be coupled to qubits 102b, 102d, 102e, and 102f.

[0048] As the number of qubits in a 2D array increases, rapid coupling to the qubits becomes extremely challenging. For example, in a qubit array such as array 100, each internal qubit may require seven separate connections (e.g., four connections to each nearest neighboring qubit and three connections for readout control, Z control, and XY control). With the increasing number of qubits in the array, the space available for wiring decreases. One option is to wire the qubits using conventional complementary metal-oxide-semiconductor (CMOS) techniques, such as forming the wiring in a multilayer deposited dielectric. However, this dielectric is associated with high losses that cause decoherence of the qubits.

[0049] Another approach to solving the qubit wiring problem is to position the wiring and other control elements on a separate chip coupled to the chip containing the qubits. For example, the wiring and readout resonators for the individual control elements (e.g., Z-control and XY-control) for each superconducting qubit in array 100 can be moved from the chip on which the qubits are formed to a separate second chip. In some embodiments, the first chip containing the qubit array 100 is electrically and mechanically connected to the second chip containing the wiring and qubit control elements using, for example, superconducting bump bonding (such as indium).

[0050] Figure 2 This is a schematic diagram illustrating an example of a stacked quantum computing device 200 including a first chip 202 and a second chip 204. The first chip 202 includes a two-dimensional array 206 of superconducting qubits. Each superconducting qubit in the example array 206 is an xmon qubit, although other qubits may be used alternatively. The second chip 204 includes a readout device 208 and control elements 210, 212. Each of the first chip 202 and the second chip 204 may also include one or more circuit elements for performing data processing operations.

[0051] The superconducting qubits of the first chip 202 can be formed on a substrate. The substrate of the first chip can be formed of, for example, a low-loss and single-crystal dielectric (such as single-crystal silicon or sapphire). The low-loss dielectric can be defined in part by having a small loss tangent of 1e-5 or less at microwave frequencies (1-10 GHz). Other materials can be used alternatively for the substrate.

[0052] The readout device 208 of the second chip 204 may include, for example, a readout resonator. Control elements 210 and 212 may include, for example, a first control element 210 (e.g., Z-control) and a second control element 212 (e.g., XY-control). When a control pulse is applied to the Z-control element, the superconducting qubit Z-control element is operable to tune the operating frequency of the superconducting qubit coupled to it. When a control pulse is applied to the XY-control element, the superconducting qubit XY-control element is operable to excite the superconducting qubit coupled to it. The readout device is operable to read the state of the superconducting qubit capacitively coupled to it by probing the frequency of the resonator element.

[0053] Similar to the first chip 202, the second chip 204 may also include a substrate formed of a low-loss dielectric material suitable for quantum circuits, such as single-crystal silicon or sapphire. The thickness of the substrate may be, for example, between approximately 10 micrometers and approximately 1000 micrometers.

[0054] The first chip 202 can be electrically and / or mechanically bonded to the second chip via a bonding member 214 (e.g., a bump bonding member).

[0055] Figures 3A-3B These are schematic diagrams showing different views of an example of a stacked quantum computing device. Figure 3A A cross-sectional view of a stacked quantum computing device 300 is shown, in which a first chip 302 is aligned on top of a second chip 304 and electrically and / or mechanically connected using a bump bonding member 306. The bump bonding member 306 may comprise a superconducting material to avoid energy loss and decoherence of qubits that may be located on, for example, the first chip 302. Suitable superconducting materials for use as the bump bonding member 306 include, but are not limited to, indium, lead, rhenium, palladium, or niobium with a thin layer of gold.

[0056] The thickness of the bump bond 306 can be configured such that the first chip 302 and the second chip 304 are spaced apart by a gap 308. The approximate height of the gap 308 can be within the range of uncertainties limited by the accuracy and / or precision of the deposition techniques(s) used for depositing and / or removing material to form the bump bond 306 (and / or other components that may affect the distance) and the metrology(s) used to measure the gap height. In some embodiments, the height of the gap between the first chip 302 and the second chip 304 is at least 5 micrometers.

[0057] Figure 3B A schematic top view of a stacked quantum computing device layout 320 in which the second chip 304 is aligned above the first chip 302 is shown. The first chip 302 includes a superconducting quantum bit 322, which includes a readout region 324, a superconducting quantum interference device (SQUID) region 326, and a control region 328. The readout region 324 of the superconducting quantum bit 322 corresponds to a region of the superconducting quantum bit 322 defined around its center and follows the outline of the central portion of the superconducting quantum bit 322 within the dashed outline. For example, regarding Figure 3B In the example shown, superconducting qubit 322 is an Xmon-type qubit, exhibiting a cross-shaped form with four long arms and additionally including a portion of the shorter arm in the upper left quadrant branching from the center of superconducting qubit 322 (e.g., corresponding to a SQUID ring shape for the superconducting qubit). When the first and second chips are aligned about each other, the readout region 324 can be shaped to cover these regions of superconducting qubit 322: including the central portion, a portion of each of the four arms, and optionally including a portion of the branch corresponding to the SQUID ring shape for the superconducting qubit 322. (See below for reference.) Figures 4A to 4C Let's discuss reading out region 324 in more detail.

[0058] The SQUID region 326 of the superconducting quantum bit 322 corresponds to a portion of the shorter arm (e.g., corresponding to a SQUID ring) in the upper left quadrant of the superconducting quantum bit 322, including the region outlined by the dashed line. See below. Figures 5A to 5C Let's discuss SQUID region 326 in more detail.

[0059] The control region 328 of the superconducting qubit 322 corresponds to a region of the superconducting qubit 322 (e.g., a region including a portion of one arm of the superconducting qubit 322). The control region 328 is adjacent to a recessed region 329, which is formed within the edge of the ground plane facing the control region 328, wherein the "tab" portion of the superconducting ground plane directly adjacent to the superconducting qubit 322 has been removed. For example, regarding... Figure 3B In the example shown, superconducting qubit 322 is an Xmon type qubit, and the recessed region 329 is a portion of the superconducting ground plane of one arm of the adjacent superconducting qubit 322 that has been removed. See below. Figures 6A to 6C The control area 328 and the recessed area 329 will be discussed in more detail.

[0060] Although qubit 322 is shown as an Xmon type qubit, other qubits can be used instead, each of which also includes a corresponding readout region, a SQUID region, and a control region, as described in detail here.

[0061] The second chip 304 includes a readout device 330, which includes a resonator element 332 electrically coupled to a pad element 334. The second chip 304 may also include wiring elements 336. Bump bonding elements (e.g., 306) contact the first chip 302 and the second chip 304. Additionally, the second chip 304 may include a first control element 338 (e.g., a Z-control element) and a second control element 340 (e.g., an XY-control element).

[0062] In some embodiments, the pad elements 334 on the second chip 304 are oriented onto the second chip 304 such that when the first chip 302 and the second chip 304 are aligned (e.g., as shown in the figure), the pad elements 334 are oriented onto the second chip 304. Figure 3AAs shown), the pad element 334 is symmetrically aligned with the readout region 324 of the corresponding superconducting quantum bit 322 on the first chip 302, such that the pad element 334 can be electromagnetically coupled (e.g., capacitively) to the readout region 330 of the second chip. In some embodiments, if the pad element 334 and the readout region 324 have the same shape, they can be symmetrically aligned such that their centers coincide with each other and their edges (or, when the edges are curved, the tangents of their edges) are substantially parallel to each other. Additionally, the resonator element 332 of the readout device 330 on the second chip 304 is oriented on the second chip 304 such that when the first chip 302 and the second chip 304 are aligned (e.g., as shown), the resonator element 332 of the readout device 330 ...4 is symmetrically aligned with the readout region 324 of the second chip 304. Figure 3A As shown), the superconducting quantum bit 322 on the first chip 302 is not directly located below the resonator element 332. (Refer to...) Figures 4A to 4C Let's discuss more details about the readout device.

[0063] In some embodiments, the first control element 338 is disposed on the second chip 304 such that the SQUID region 326 of the superconducting quantum bit 322 on the first chip 302 is directly aligned below the first control element 338 on the second chip 304. By positioning the SQUID region 326 directly below the first control element 338, the first control element 338 can be electromagnetically coupled (e.g., inductively coupled) to the quantum bit via the SQUID region 326. (Refer to below...) Figure 5C The alignment of the SQUID region 326 relative to the first control element 338 will be discussed in more detail.

[0064] In some embodiments, the second control element 340 is disposed on the second chip 304 such that the second control element 340 is laterally displaced from the control region 328 of the superconducting quantum bit and does not overlap with the control region 328 of the superconducting quantum bit. Instead, the second control element 340 is aligned above the recessed region 329 of the superconducting quantum bit 322 on the first chip 302. By positioning the recessed region 329 directly below the second control element 340 and displacing the second control element 340 from the control region 328, the second control element 340 can be electromagnetically coupled (e.g., via mutual capacitance of the edge field) to the quantum bit through the control region 328. (See below for further details.) Figure 6C The alignment of the control area 328 relative to the second control element 340 will be discussed in more detail.

[0065] In some implementations, such as Figure 3AAs shown, the gap 308 between the first chip 302 and the second chip 304 is configured to achieve desired capacitive or inductive coupling between circuit elements on the first chip 302 and the second chip 304 (e.g., the readout region 324 of the superconducting quantum bit 322 on the first chip 302 and the readout device 330 on the second chip 304).

[0066] For example, the height of the gap 308 between the device surface of the first chip 302 and the structural element surface of the second chip 304 can be set to be between approximately 0.5 μm and approximately 100 μm (e.g., between approximately 10 μm and approximately 20 μm, between approximately 1 μm and 10 μm, between approximately 0.5 μm and approximately 20 μm, between approximately 0.5 μm and approximately 15 μm, between approximately 0.5 μm and approximately 10 μm, between approximately 0.5 μm and approximately 5 μm, or between approximately 0.5 μm and approximately 2.5 μm).

[0067] Figure 3C This is a schematic top view 350 showing a second chip 304 of a stacked quantum computing device, where the second chip 304 is aligned with the first chip 302 by a bump bond (e.g., a superconducting bump bond 306) that bonds the two chips together. Figure 3C In the schematic diagram, the white areas correspond to the superconducting material, and the shaded areas correspond to the exposed surface of the substrate. Figure 3C In the schematic diagram, the superconducting layer and substrate of the second chip 304 are transparent, and the individual circuit elements on the second chip 304 are depicted as outlines defined only by the regions of the substrate of the second chip exposed (e.g., regions where the superconducting layer has been removed).

[0068] The first chip 302 includes superconducting qubits 354, wherein white regions correspond to superconducting materials (e.g., aluminum) and black regions correspond to exposed surfaces of a substrate (e.g., a dielectric substrate). Figure 3C The superconducting qubit 354 depicted is an Xmon-type superconducting qubit. Other qubit types, such as gmon, fluxmon, or transmon qubits, may also be used alternatively. The readout region 356, the SQUID region 358, and the recessed region 361 adjacent to the edge of the control region 360 of the superconducting qubit 354 on the first chip 302 are identified by their respective dashed outlines.

[0069] The second chip 304 includes a readout device 362, which comprises an electrically coupled pad element 364 and a resonator element 366. The pad element 364 includes a cross-shaped superconducting pad aligned above the center of the superconducting quantum bit 354. Figure 3CAs shown, pad element 364 is depicted as a transparent cross-shaped profile aligned within the dashed outline of readout region 356; however, the interior of the cross-shaped profile should be understood to be composed of a superconducting material. Resonator element 366 includes, for example, elongated superconducting coplanar waveguide traces. The resonant frequency / mode portion of resonator element 366 is determined by its length and effective dielectric constant. To save space on the second chip 304, resonator element 366 is arranged in a serpentine shape.

[0070] The second chip 304 additionally includes a first control element 368, which overlaps with the SQUID region 358 of the superconducting quantum bit 354 on the first chip 302 when the first chip 302 and the second chip 304 are aligned and bonded together (e.g., via bump bonding member 306). Figure 3C The image depicts a first control element 368 such that the superconducting layer (e.g., aluminum) of the first control element 368 is transparent, and the outline of the first control element 368 (e.g., the area where the superconducting material has been removed and the substrate is exposed) is depicted in black. See below for reference. Figure 5A and 5C Further details of the first control element 368 are discussed.

[0071] The second chip 304 also includes a second control element 370, which overlaps with the recessed region 361 of the superconducting quantum bit 354 on the first chip 302 when the first chip 302 and the second chip 304 are aligned and bonded together (e.g., via bump bonding member 306). Figure 3C The superconducting layer (e.g., aluminum) of the second control element 370 is depicted in black, while the outline of the second control element 370 (e.g., the area where the superconducting material has been removed and the substrate is exposed) is depicted in black. See below for reference. Figure 6A and 6C Further details of the second control element 370 are discussed.

[0072] Figure 4A This is a schematic top view illustrating an exemplary readout device 402 formed on a second chip 404 of a stacked quantum computing device, and when the first chip (e.g., Figure 4B When the first chip 410 and the second chip are bonded together, the readout device 402 will face the first chip. Figure 4A The white areas in the diagram correspond to regions where at least a superconducting material layer exists, while the gray / black areas correspond to regions where no superconducting material exists and the substrate can be exposed. Readout device 402 (corresponding to...) Figure 4AThe components within the dashed area shown include, for example, pad element 412 and resonator element 414, and may be made of a superconducting material (e.g., aluminum). An example of a readout device 414 includes a quarter-wavelength coplanar waveguide resonator.

[0073] In some implementations, resonator element 414 is a distributed element resonator or a lumped element resonator, such as a coplanar waveguide resonator formed of a superconducting material (e.g., aluminum), wherein the frequency of the resonator is partially determined by the resonator length.

[0074] During operation of the stacked quantum computing device, the pad element 412 can be electromagnetically coupled (e.g., capacitively coupled) to the first chip (e.g., Figure 4B The superconducting qubits on the first chip 410 (e.g., Figure 4B The superconducting qubit 408 is located directly beneath the pad element 412. The superconducting qubit 408 on the first chip 410 can then be read out during operation of the stacked quantum computing device by probing the frequency of the resonator element 414. The pad element 412 can have various surface region geometries, depending in part on the individual shapes of the superconducting qubits and the required capacitance. For example, as... Figure 4B As shown, superconducting qubit 408 is an Xmon type qubit that exhibits a cross shape with four long arms, and additionally includes a portion of the shorter arm in the upper right quadrant branching from the center of superconducting qubit 408 (e.g., corresponding to the SQUID ring shape of superconducting qubits). Figure 4A The pad element 412 shown may be cross-shaped, such that when the first and second chips are aligned, the region of the superconducting qubit 408 covered by the pad element 412 includes the central portion and a portion of each of the four arms of the superconducting qubit 408. In some embodiments, a portion of the SQUID ring-shaped branch corresponding to the superconducting qubit 408 is also covered by the pad element 412. In another example, for the gmon qubit, the pad element may have a square or rectangular shape.

[0075] In some implementations... Figure 4A The resonator element 414 and pad element 412 shown are formed on the same layer on the second chip 404. In some embodiments, the resonator element 414 and pad element 412 are formed in different layers on the second chip 404.

[0076] Figure 4BThis is a schematic top view illustrating an exemplary superconducting quantum bit 408 formed on a first chip 410, which will be bonded to a second chip 404. White areas correspond to regions where superconducting material is present, while shaded areas correspond to regions where no superconducting material is present and where the substrate can be exposed. The first chip 410 includes the superconducting quantum bit 408, such as the Xmon quantum bit, although other types of superconducting quantum bits may also be used alternatively. Figure 4B In the example shown, the readout region 406 of the superconducting quantum bit 408 corresponds to the region around the center of the superconducting quantum bit 408 and follows the outline of the central portion of the superconducting quantum bit 408 (including at least a portion of each of the four arms of the superconducting quantum bit 408). Additionally, in some embodiments, a portion corresponding to a SQUID loop branch 407 extending from the center to the upper right corner of the superconducting quantum bit 408 is also included in the readout region 406 of the superconducting quantum bit 408.

[0077] Figure 4C This is a schematic top view of a second chip 410 in a stacked quantum computing device, which includes a second chip 410 bonded to a first chip 404, such that the outlines of circuit elements on the first chip aligned with circuit elements on the second chip are visible. Figure 4C As shown, the readout device 402, including pad element 412 and resonator element 414, is aligned such that the pad element 412 is directly above the readout region 406 of the superconducting quantum bit 408 on the first chip 410. Conversely, the resonator element 414 is laterally shifted so that it does not directly overlap with the superconducting quantum bit 408 on the first chip 410. This arrangement can reduce undesirable coupling and / or interference between the resonator element 414 and the superconducting quantum bit 408.

[0078] During operation of the stacked quantum computing device, readout device 402 can be electromagnetically coupled to a portion of superconducting qubit 408 located in readout region 406. For example, pad element 412 can be capacitively coupled to readout region 406 of superconducting qubit 408. The capacitance between pad element 412 and the qubit can vary depending on the relative sizes of pad element 412 and qubit 408, the overlap between them, and the gap distance between the first and second chips. In some embodiments, the dimensions of pad element 412 can be modified to achieve a specific capacitance. For example, the dimensions of pad element 412 can be adjusted to achieve a capacitance between approximately 1 and 50 nanofarads between qubit 408 and pad element 412. Other capacitance values ​​are also possible.

[0079] In some embodiments, the surface area of ​​the superconducting quantum bit 406 in the readout region 406 of the superconducting quantum bit 408 on the first chip facing the pad element 412 on the second chip (e.g., in Figure 4C The area of ​​the superconducting quantum bit 408 within the dashed outline depicted is smaller than the surface area of ​​the pad element 412 facing the first chip. For example, one or more dimensions (e.g., width 416) of one or more arms of the cross-shaped pad element 412 can be enlarged to allow for misalignment between the bonded first and second chips. That is, even if there is a slight misalignment between the first and second chips, the magnitude of the mutual coupling between the readout device 402 and the superconducting quantum bit 408 remains substantially the same because the pad element 402 will still be aligned over the same area of ​​the superconducting quantum bit 408. Exemplary misalignment can include, for example, a few micrometers in the y-direction. Therefore, increasing the width 416 on the arm of the pad element 412 by a few micrometers such that this width is a few micrometers larger than the corresponding width (e.g., width 420) of the arm of the superconducting quantum bit 408 within the readout region 406 allows for misalignment of the respective readout regions 406 and the superconducting quantum bit 408 during the bonding process of the first and second chips.

[0080] In some embodiments, the length (e.g., length 422) of one or more arms of the cross-shaped pad element 412 can be varied to adjust the capacitance between the qubit 408 and the pad element 412. Typically, the amount of overlap between the surface area of ​​the pad element 412 and the surface area of ​​the qubit 408 in the readout region 406 partially indicates the capacitance between the qubit 408 and the pad element 412 in the form of a parallel-plate capacitor.

[0081] Figure 5A This illustrates the first control element 502 (such as...) formed on the second chip. Figure 2 A schematic top view of the control element 210. White areas correspond to regions where at least a layer of superconducting material exists, while shaded areas correspond to regions where no superconducting material exists and the substrate can be exposed. The first control element 502 may include, for example, a qubit Z-control element. When a control pulse is applied to the Z-control element, the qubit Z-control element is operable to tune the operating frequency of the superconducting qubit coupled to the first control element 502. Figure 5A The first control element 502 shown includes a bias coil formed by a layer of superconducting material disposed on the surface of a substrate. The bias coil formed by the superconducting layer includes a first portion 504 coupled to a ground plane 501, a second portion 506 coupled to a source providing control pulses during operation of the stacked quantum computing device, and a third annular portion 508.

[0082] The annular portion 508 of the bias coil includes an inner annular edge 503 and an outer annular edge 505. The outer annular edge 505 is separated from the superconductor ground plane 501 by a gap 507. Figure 5A As shown, the width 509 of the superconducting material in the first portion 504 and the second portion 506 is much narrower than the width 511 of the superconducting material in the annular portion 508. This reduces the footprint of the bias line. To prevent unwanted return current, a ground connection is made where the bias line is short-circuited. This can be achieved using bump bonding, such as in... Figure 3C The bump bonding members 306 on both sides of the bias line region 390 are shown. An inner annular edge 503 and an outer annular edge 505 are formed on the second chip such that when the first and second chips are aligned and bonded together (e.g., the inner annular edge is contained within the inner annular region 512 of the SQUID region 510), the inner annular edge is within the SQUID region 510 of the superconducting quantum bit on the first chip. The outer annular edge 505 is formed such that when the first and second chips are aligned, the inner annular region 512 of the SQUID region 510 of the superconducting quantum bit on the first chip is completely contained by the outer annular edge 505 of the annular portion 508 on the second chip.

[0083] Figure 5B It shows superconducting qubits (such as Figure 2 This is a schematic top view of an example of a superconducting quantum interference device (SQUID) region 510 showing a superconducting quantum bit 206. White areas correspond to regions where a layer of superconducting material exists, while shaded areas correspond to regions where no superconducting material is present and where the substrate of the first chip can be exposed. Figure 5B In the example shown, the SQUID within SQUID region 510 is physically coupled to and extends from the central region of the superconducting qubit. SQUID region 510 comprises layers of superconducting material arranged in a generally circular manner, wherein the superconducting material is interrupted at multiple locations by Josephson junctions 514. The superconducting wiring of the Josephson junctions 514 is depicted in black. A portion of SQUID region 510 may be formed by a superconducting ground plane 513. In this example, SQUID region 510 therefore has an inner circular region 512 in which no superconductor exists. The area / perimeter of the inner circular region 512 is defined by the edge 516 of the superconducting material.

[0084] When the first chip is aligned with the second chip to provide a stacked quantum computing device, the first control element 502 is aligned above the SQUID region 510 of the corresponding qubit. During operation of the stacked quantum computing device, the first control element 502 can be electromagnetically coupled (e.g., inductively coupled) to the SQUID within the SQUID region 510. Inductive coupling allows the operating frequency of the qubit to be tuned when a control pulse is applied to the first control element 502. The first control element 502 and the SQUID of the SQUID region 510 are associated using mutual inductance. For example, the mutual inductance can be between approximately 0.1 pH and approximately 100 pH.

[0085] Figure 5C This is a schematic top view showing a first control element 502 aligned above the SQUID region 510. Typically, for superconducting circuit elements, current flows primarily along the edges of the superconducting layer forming the circuit element. As a result, variations in the position of the edges of the superconducting material forming the first control element bias coil 508 relative to the superconducting material forming the inner ring region 512 of the SQUID can lead to a change in the desired mutual inductance between the first control element and the SQUID region, as well as increased stray mutual inductance, which can cause qubit decoherence. This change can be due to, for example, misalignment between the first and second chips during the bonding process.

[0086] To achieve high coupling with the SQUID region 510 and reduce stray mutual inductance, and to avoid desired changes in mutual inductance due to misalignment during bonding, the bias coil 508 of the first control element 502 remains substantially symmetrical. For example, by providing the inner annular portion 503 of the bias coil 508 with a shape symmetrical with respect to the outer annular edge 505 of the bias coil 508 (e.g., such that the stray magnetic fields of each are equal and opposite), stray flux from the annular portion 508 cancels itself out by symmetry cancellation, while maintaining high coupling with the SQUID region 510. Furthermore, the SQUID region 510 is located near the ground plane and away from other features of the superconducting qubit (e.g., the readout region or control region of the superconducting qubit), such that the influence of flux from these other features (e.g., features other than the SQUID region 510, or other adjacent superconducting qubits) is reduced.

[0087] Furthermore, the area of ​​the annular portion 508 of the bias coil is larger relative to the inner annular region 512 of the SQUID region 510 to provide a certain tolerance for misalignment. That is, when misalignment errors exist between the first and second chips, the position of the inner annular edge 503 of the bias coil is more likely to remain directly above the inner annular region 512. Additionally, the position of the outer annular edge 505 is more likely to remain away from the inner annular region 512, such that stray mutual inductance caused by current traveling along the outer annular edge 505. For example, the lateral distance (e.g., lateral distance 520) between the inner annular edge 503 and the edge 516 of the inner annular region 512 is in the range of about 1 micrometer to about 10 micrometers. Additionally, in some embodiments, the lateral distance (e.g., lateral distance 522) between the edge 516 of the inner annular region and the edge 505 of the outer annular region is in the range of about 1 micrometer to about 20 micrometers. The ranges of lateral distances 520 and 522 may depend on the alignment errors of the stacked quantum computing device configuration. For example, if the alignment error includes a misalignment of 2 micrometers along the X-axis or Y-axis, the range of lateral distances 520 and 522 can be set to 4 micrometers.

[0088] In some implementations, when the first chip is aligned and bonded to the second chip, the inner annular edge 503 and the outer annular edge 505 of the bias coil 508 may be located within the inner annular region 512. In this case, the outer annular edge 505 has a lateral distance of at least 2 micrometers within the edge 516 of the inner annular region 512.

[0089] Figure 6A This shows the second control element 602 on the second chip (such as...). Figure 2 This is a schematic top view of an example of the second control element 212. White areas correspond to regions where superconducting material is present, while shaded areas correspond to regions where no superconducting material is present and where the substrate can be exposed. The second control element 602 may include, for example, a qubit XY control element. When a control signal is applied to the XY control element, the superconducting qubit XY control element is operable to excite the qubits coupled to it. Figure 6A The second control element 602 shown includes a pad element 604 and a wiring element 606. The pad element 604 is located at one end of the wiring element 606. The wiring element 606 can be coupled to a signal source that provides control signals to the XY control element. The pad element 604 and the wiring element 606 are formed in a superconducting layer (e.g., a superconducting thin film) on the second chip, wherein the pad element 604 and the wiring element 606 are separated from the superconducting ground plane 601 by a gap 607 in the superconducting layer (e.g., by exposing the substrate). The pad element 604 includes a pad element length 605 and a pad element width 603.

[0090] Figure 6B This shows superconducting qubits (such as...) on the first chip. Figure 2 This is a schematic top view of the control region 606 of a superconducting quantum bit (206). Generally, the control region of a superconducting quantum bit includes a region of the superconducting quantum bit (e.g., a portion of an arm of the superconducting quantum bit) in which the superconducting quantum bit on a first chip can be excited by a second control element 602 (e.g., an XY control element) on a second chip, wherein the second control element is coupled to the second chip when a control signal is applied by the second control element 602. In the example where the superconducting quantum bit is of the Xmon quantum bit type, the control region 606 of the superconducting quantum bit includes at least a portion of one arm of the superconducting quantum bit.

[0091] The white areas correspond to regions where superconducting materials are present, while the shaded areas correspond to regions where no superconducting materials are present and where the substrate can be exposed. Figure 6B The diagram also shows a superconducting ground plane 611. The edge 608 of the ground plane 611 is aligned parallel to the edge 610 of the control region 606 and separated from the edge 610 by a gap 613 in the superconducting material (e.g., a region where the substrate is exposed). The edge 608 of the ground plane 611 also includes a recessed (or notched or grooved) region 612 in which no superconducting material is present and the substrate can be exposed. The recessed region 612 includes a recessed region length 614 and a recessed region width 616, which may be greater than the pad element length 605 and the pad element width 603, respectively.

[0092] Figure 6C It is shown in Figure 6A The recessed area 612 is aligned with the top Figure 6A A schematic top view of the second control element 602. Figure 6C The schematic diagram also shows the outline of the control region 606 of the superconducting qubit, which is adjacent to... Figure 6B The recessed area 612 is aligned with the second control element 602. A ground plane 611 on the first chip is also shown. (See figure) Figure 6C As shown, the pad element 604 of the second control element 602 is laterally shifted from the control region 606 of the superconducting quantum bit and does not overlap with the control region 606. Instead, the second control element 602 is aligned above the recessed region 612. Figure 6C As shown, by laterally shifting the second control element 602 from the control region 606, significant overcoupling can be avoided (which could occur if the second control element 602 were placed directly on or overlapped with the control region 606). Using Figure 6CIn the arrangement shown, the second control element 602 and the control region 606 of the superconducting quantum bit are capacitively coupled via the mutual capacitance of the edge fields between the second control element 602 and the control region 606 of the superconducting quantum bit. For example, the second control element 602 and the control region 606 of the superconducting quantum bit have a mutual capacitance of 30 attofarads to achieve control of the superconducting quantum bit (e.g., XY control).

[0093] In some embodiments, when the first chip and the second chip are bonded together, the second control element 602 is aligned completely within the region of the recessed region 612. The surface area of ​​the recessed region 612 is selected to account for misalignment during the bonding process, such that the edges of the second control element 602 are completely aligned within the recessed region 612. Furthermore, in some embodiments, the total surface area of ​​the second control element 602 facing the first chip (which includes superconducting qubits) is smaller than the total surface area of ​​the recessed region 612 facing the second chip including the second control element 612. For example, as... Figure 6A As shown, the pad element 604 has a rectangular shape, with a length 605 and a width 603 defining the total surface area of ​​the pad element 604. Figure 6B As shown, in this example, the recessed region 612 has a rectangular shape with a length 614 and a width 616 defining the total surface area of ​​the recessed region 612. The pad element 604 and the recessed region 612 can alternatively use other shapes. By providing a second control element 602 having a total surface area facing the first chip that is smaller than the total surface area of ​​the recessed region facing the second chip, stray coupling that may occur due to misalignment can be reduced.

[0094] Figure 7 It shows a chip bonded to a second chip (such as...) Figure 2 The first chip (such as chip 204) in the middle Figure 2 A schematic top view of an exemplary stacked quantum computing device (chip 202). This view is obtained through the first chip, where the superconducting material of the first chip is depicted as transparent. Figure 7As shown, the Xmon qubit 702 is provided on a first chip and includes a readout region 704, a SQUID region 706, and a control region 708 for the superconducting qubit 702. A recessed region 710 is formed within the edge of the ground plane facing the control region 708. A readout device 712 of a second chip is aligned with the readout region 704 of the first chip. For example, a portion of the pad element 714 (e.g., pad element 412) of the readout device 714 is aligned below the readout region 704. Additionally, the annular portion 716 (e.g., inner annular 503) of the bias coil 718 of the first control element 720 (e.g., first control element 502) is aligned within the inner annular region (e.g., inner annular region 512) of the SQUID region 706. Furthermore, the second control element 722 (e.g., control element 602) is aligned within the recessed region 710 such that the edge of the control element is aligned within the recessed region and shifted from the qubit.

[0095] Superconducting (or alternatively superconducting) materials can be understood as materials that exhibit superconducting properties at or below the superconducting critical temperature. Examples of superconducting materials include aluminum (superconducting critical temperature of 1.2 Kelvin) and niobium (superconducting critical temperature of 9.3 Kelvin). The superconducting material used to form the devices disclosed herein can have a thickness, for example, ranging from about 10 nanometers to about 1000 nanometers.

[0096] Aluminum is an example of a superconducting material that can be used to form quantum computing circuit elements. Aluminum can be bonded with a dielectric to create Josephson junctions, a common component in quantum computing circuits. Examples of quantum computing circuit elements that can be formed using aluminum include circuit elements such as superconducting coplanar waveguides, quantum LC oscillators, qubits (e.g., flux qubits or charge qubits), superconducting quantum interference devices (SQUIDs) (e.g., radio frequency SQUIDs or DC-SQUIDs), inductors, capacitors, transmission lines, ground planes, etc.

[0097] For certain circuit elements disclosed herein, such as Josephson junctions, it may be necessary to introduce one or more layers of dielectric material. Such dielectric material layers can be formed to have a thickness, for example, ranging from about 50 nanometers to about 2000 nanometers.

[0098] The processes described herein may require the deposition of one or more materials, such as superconductors, dielectrics, and / or metals. Depending on the materials chosen, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), epitaxy, and other deposition processes. The processes described herein may also require the removal of one or more materials from the equipment during manufacturing. Depending on the material to be removed, the removal process may include, for example, wet etching, dry etching, or stripping processes.

[0099] The implementations of quantum themes and quantum operations described in this specification can be implemented in suitable quantum circuits, or more generally, in quantum computing systems, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term "quantum computing system" can include, but is not limited to, quantum computers, quantum information processing systems, quantum cryptography systems, or quantum simulators.

[0100] The terms quantum information and quantum data refer to information or data carried, held, or stored by quantum systems, the smallest nontrivial system being a qubit, such as a system that defines the unit of quantum information. It should be understood that the term "qubit" includes all quantum systems that can be appropriately approximated as a two-level system in the corresponding context. Such quantum systems can include, for example, multi-level systems with two or more levels. For example, such systems can include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the fundamental computational state is identified using a ground state and a first excitation state; however, it should be understood that other arrangements are possible where the computational state is identified using higher-level excitation states. It should be understood that a quantum memory is a device capable of storing quantum data for long periods with high fidelity and efficiency, such as a light-matter interface where light is used for transmission and matter is used for storage and preservation of quantum data, specifically quantum features (e.g., superposition or quantum coherence).

[0101] Quantum circuit elements (e.g., quantum computing circuit elements) include circuit elements used to perform quantum processing operations. That is, quantum circuit elements can be configured to perform operations on data in a nondeterministic manner using quantum mechanical phenomena such as superposition and entanglement. Some quantum circuit elements (such as qubits) can be configured to simultaneously represent and manipulate information from more than one state. Examples of superconducting quantum circuit elements that can be formed using the processes disclosed herein include circuit elements such as coplanar waveguides, quantum LC oscillators, qubits (e.g., flux qubits or charge qubits), superconducting quantum interference devices (SQUIDs) (e.g., radio frequency SQUIDs or DC-SQUIDs), inductors, capacitors, transmission lines, ground planes, etc.

[0102] In contrast, classical circuit elements typically process data in a deterministic manner. Classical circuit elements can be configured to collectively execute instructions of a computer program by performing basic arithmetic, logic, and / or input / output operations on data, where the data is represented in analog or digital form. In some implementations, classical circuit elements can be used to send data to and / or receive data from quantum computing circuit elements via electrical or electromagnetic connections. Examples of classical circuit elements that can be formed using the processes disclosed herein include rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices, and ERSFQ devices, which are energy-efficient versions of RSFQs that do not use bias resistors. Other classical circuit elements can also be formed using the processes disclosed herein.

[0103] During the operation of a quantum computing system using superconducting quantum computing circuit elements and / or superconducting classical circuit elements (such as those described herein), the superconducting circuit elements are cooled in a cryostat to a temperature that allows the superconducting material to exhibit superconducting properties.

[0104] While this specification contains numerous specific details of implementation, these details should not be construed as limiting the scope of the claims, but rather as descriptions of features specific to particular implementations. Certain features described in the context of individual implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although the foregoing features may be described as functioning in certain combinations, and even initially claimed in this way, in some cases one or more features from the claimed combination may be removed, and the claimed combination may refer to a sub-combination or a variation of a sub-combination.

[0105] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order or sequence shown, or requiring all of the shown operations to obtain the desired result. For example, the actions listed in the claims can be performed in a different order and still obtain the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various components in the above embodiments should not be construed as requiring such separation in all embodiments.

[0106] Many implementations have been described. However, it should be understood that various modifications can be made without departing from the spirit and scope of the invention. Other embodiments are also within the scope of the following claims.

Claims

1. A stacked quantum computing device, comprising: The first chip including qubits; as well as A second chip is bonded to the first chip, the second chip including a readout device. The readout device includes a first readout element at a first end of the readout device and a second readout element at a second end of the readout device, wherein the first readout element directly overlaps with the qubit, and wherein the second readout element is laterally shifted from the qubit and does not directly overlap with the qubit.

2. The stacked quantum computing device of claim 1, wherein the first readout element comprises a pad element.

3. The stacked quantum computing device of claim 2, wherein the central portion of the pad element is aligned above the central portion of the qubit.

4. The stacked quantum computing device of claim 2, wherein the pad elements are symmetrically aligned with the readout region of the qubit.

5. The stacked quantum computing device of claim 4, wherein the pad element has the same shape as the readout region of the qubit.

6. The stacked quantum computing device of claim 5, wherein the edges of the pad elements are arranged substantially parallel to the edges of the readout region.

7. The stacked quantum computing device of claim 2, wherein the second readout element comprises a coplanar waveguide.

8. The stacked quantum computing device of claim 7, wherein the coplanar waveguide is serpentine in shape.

9. The stacked quantum computing device of claim 1, wherein the first readout element and the second readout element are formed in different layers on the second chip.

10. The stacked quantum computing device of claim 1, wherein the first readout element is sized to achieve a capacitance between the qubit and the first readout element of between 1 nanofarad and 50 nanofarads.

11. The stacked quantum computing device of claim 1, wherein the surface area of ​​the qubit facing the first readout element is smaller than the surface area of ​​the first readout element facing the first chip.

12. A stacked quantum computing device, comprising: A first chip including qubits, wherein the qubits include a first control region and a second control region, and the first control region includes a superconducting quantum interference device (SQUID). as well as A second chip is bonded to the first chip, the second chip including a first control element and a second control element. The first control element is arranged to be inductively coupled to the first control region, and The second control element is arranged to be capacitively coupled to the second control region.

13. The stacked quantum computing device of claim 12, wherein the first control element directly overlaps with the first control region.

14. The stacked quantum computing device of claim 12, wherein the second control element is laterally shifted from the second control region and does not overlap with the second control region.

15. The stacked quantum computing device of claim 14, wherein the first chip includes a ground plane, wherein the ground plane includes a recess adjacent to the qubit, and wherein the second control element is aligned above the recess in the ground plane.

16. The stacked quantum computing device of claim 15, wherein the surface area of ​​the second control element facing the first chip is smaller than the surface area of ​​the recess facing the second chip.

17. The stacked quantum computing device of claim 12, wherein when the first control element is inductively coupled to the first control region, the first control element is operable to tune the operating frequency of the qubit.

18. The stacked quantum computing device of claim 12, wherein when the second control element is capacitively coupled to the second control region of the qubit, the second control element is operable to excite the qubit.

19. The stacked quantum computing device of claim 12, wherein the second control element is arranged to be electromagnetically coupled to the second control region via mutual capacitance of the edge field between the second control element and the second control region of the qubit.

20. The stacked quantum computing device of claim 12, wherein the second control element is arranged and sized to achieve a capacitance of 30 attofarads between the qubit and the second control element.

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