Three-dimensional phase change memory high-reliability write circuit

Abstract

The application relates to a three-dimensional phase change memory high-reliability write circuit, which comprises a bit line data sensing module, a row and column address sensing module and a lookup table module. The bit line data sensing module is used for determining the data state on a selected bit line; the row and column address sensing module is used for determining the block address to which a selected unit belongs according to the row address and the column address of the selected unit; the lookup table module is used for taking the data state on the selected bit line and the block address to which the selected unit belongs as indexes to find the optimal write current amplitude from a write current amplitude configuration table; and the write driving module is used for outputting the write current with the optimal write current amplitude to the selected unit. The application can improve the reliability of the three-dimensional phase change memory.

Description

Technical Field

[0001] This invention relates to the field of three-dimensional phase-change memory technology, and in particular to a high-reliability write circuit for a three-dimensional phase-change memory. Background Technology

[0002] Three-dimensional phase-change memory (3D phase-change memory) is a novel high-density memory that further improves storage density while retaining the advantages of traditional phase-change memory. However, 3D phase-change memory uses 1S1R memory cells without gate control terminals, resulting in larger leakage currents than traditional 1T1R and 1D1R memory cells. Furthermore, the thinner and longer array interconnects cause a larger voltage drop across the array interconnects compared to traditional phase-change memory arrays. The voltage drop across the array interconnects is coupled with the leakage current, leading to a larger leakage current amplitude and increased inconsistency in leakage current when writing to memory cells at different addresses.

[0003] Traditional fixed-write schemes use a fixed worst-case write current pulse to write all cells in a 3D phase-change memory array. This does not take into account the inconsistency of effective current in memory cells caused by voltage drop across array interconnects and leakage current coupling, which leads to over-programming, increased thermal interference in the memory array, reduced memory cell lifespan, and decreased reliability of the 3D phase-change memory. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a high-reliability write circuit for a three-dimensional phase-change memory, which can improve the reliability of the three-dimensional phase-change memory.

[0005] The technical solution adopted by this invention to solve its technical problem is: to provide a high-reliability write circuit for a three-dimensional phase-change memory, comprising:

[0006] The bit line data sensing module is used to determine the data status of the selected bit line.

[0007] The row and column address sensing module is used to determine the block address to which the selected cell belongs based on the row and column addresses of the selected cell;

[0008] The lookup table module is used to find the optimal write current amplitude from the write current amplitude configuration table by using the data status on the selected bit line and the block address to which the selected unit belongs as an index.

[0009] The write driver module is used to output the write current with the optimal write current amplitude to the selected unit.

[0010] The bit line data sensing module includes a detection circuit, a current comparator, and a register connected in sequence. The detection circuit is used to generate an output current based on the selected bit line; the current comparator is used to determine the data state on the selected bit line based on the magnitude of the output current; and the register is used to store the data state on the selected bit line determined by the current comparator.

[0011] During detection, the detection circuit connects the detection voltage to the selected bit line and keeps the word line at 0V to obtain the output current.

[0012] The current comparator replicates the output current of the detection circuit using a current mirror and compares it with four different reference currents to determine the data status on the selected bit line.

[0013] The current comparator includes a PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The PMOS transistor, as part of a current mirror, replicates the output current of the detection circuit. Its source is connected to the power supply terminal, its drain is connected to the drain of the first NMOS transistor, and its gate is connected to the gate of another PMOS transistor in the current mirror. The source of the first NMOS transistor is grounded, and its gate is connected to its drain. The gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, its source is grounded, and its drain is connected to a fourth reference current source. The gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, its source is grounded, and its drain is connected to a third reference current source. The gate of the fourth NMOS transistor is connected to the gate of the first NMOS transistor, its source is grounded, and its drain is connected to a second reference current source. The gate of the fifth NMOS transistor is connected to the gate of the first NMOS transistor, its source is grounded, and its drain is connected to a first reference current source. The drains of the second, third, fourth, and fifth NMOS transistors also serve as inputs to combinational logic circuits.

[0014] The combinational logic circuit includes a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a first AND gate, a second AND gate, a third AND gate, a first OR gate, and a second OR gate. The input of the first NOT gate is connected to the drain of a second NMOS transistor, and its output serves as the first output of the combinational logic circuit. The input of the second NOT gate is connected to the drain of a third NMOS transistor, and its output is connected to the first input of the first AND gate. The input of the third NOT gate is connected to the drain of a fourth NMOS transistor, and its output is connected to the first input of the second AND gate. The input of the fourth NOT gate is connected to the drain of a fifth NMOS transistor, and its output is connected to the first input of the second AND gate. The first input terminal of the third AND gate is connected to the first input terminal of the third AND gate; the second input terminal of the first AND gate is connected to the drain of the second NMOS transistor, and the output terminal is connected to the first input terminal of the first OR gate and the second OR gate respectively; the second input terminal of the second AND gate is connected to the drain of the third NMOS transistor, and the output terminal is connected to the second input terminal of the first OR gate; the second input terminal of the third AND gate is connected to the drain of the fourth NMOS transistor, and the output terminal is connected to the second input terminal of the second OR gate; the output terminal of the first OR gate serves as the second output terminal of the combinational logic circuit; the output terminal of the second OR gate serves as the third output terminal of the combinational logic circuit.

[0015] Beneficial effects

[0016] By adopting the above-mentioned technical solution, the present invention has the following advantages and positive effects compared with the prior art: The present invention adds a pre-detection operation before the write operation to determine the data status of the selected bit line, and controls the write driver to output a write current pulse of appropriate amplitude according to the data status of the selected bit line and the address of the selected cell through the lookup table index result. This realizes the data pattern perception and row and column address perception of the write current, reduces the degree of overprogramming while ensuring the completion of the write operation, reduces thermal interference in the three-dimensional phase change memory array, and improves the life of the memory cell, thereby improving the reliability of the three-dimensional phase change memory. Attached Figure Description

[0017] Figure 1 This is a structural block diagram of an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of the detection circuit in an embodiment of the present invention;

[0019] Figure 3 This is a connection diagram of the detection circuit and the current comparator in an embodiment of the present invention;

[0020] Figure 4 This is a circuit diagram of the current comparator in an embodiment of the present invention. Detailed Implementation

[0021] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0022] The embodiments of the present invention relate to a high-reliability write circuit for a three-dimensional phase-change memory, such as... Figure 1 As shown, it includes: a bit line data sensing module, used to determine the data status on the selected bit line; a row and column address sensing module, used to determine the block address to which the selected unit belongs based on the row address and column address of the selected unit; a lookup table module, used to find the optimal write current amplitude from the write current amplitude configuration table using the data status on the selected bit line and the block address to which the selected unit belongs as indexes; and a write drive module, used to output the write current of the optimal write current amplitude to the selected unit.

[0023] This embodiment utilizes the coupling relationship between the voltage drop and leakage current of the array interconnects. The effective current of a memory cell in a three-dimensional phase-change memory array is affected by the number of low-resistivity cells on the selected bit line and the row and column addresses of the selected cells. A high-reliability write circuit for the three-dimensional phase-change memory is proposed, which can improve the reliability of the three-dimensional phase-change memory. The bit line data sensing module of this embodiment includes a detection circuit, a current comparator, and a register connected in sequence.

[0024] This implementation adds a pre-detection operation before writing to the selected cell. First, the detection circuit and current comparator in the bit line data sensing module are used to determine the number of low-resistance cells on the selected bit line and identify them as the i-th data mode. Then, the data mode is registered through the register in the bit line data sensing module to realize the sensing of the selected bit line data mode.

[0025] The principle of the detection circuit is as follows: Figure 2 As shown, it utilizes the ability of a cross-array to simulate matrix operations. The detected voltage Vr is connected to the selected bit line, while the word line remains at 0V, allowing the output current to be obtained. The output current of the detected voltage Vr increases monotonically with the number of low-resistance cells on the selected bit line; that is, the more low-resistance cells on the selected bit line, the larger the output current. A current comparator can compare the output current with the reference current in k-1, thus classifying the selected bit line into k data modes.

[0026] like Figure 3 As shown, the connection between the detection circuit and the current comparator can be achieved through a current mirror circuit. The current comparator in this embodiment is as follows: Figure 4As shown, the current comparator replicates the output current of the detection circuit through a current mirror and compares it with four different reference currents to determine the data status on the selected bit line.

[0027] The current comparator includes a PMOS transistor PM0, a first NMOS transistor NM0, a second NMOS transistor NM1, a third NMOS transistor NM2, a fourth NMOS transistor NM3, and a fifth NMOS transistor NM4. The PMOS transistor PM0, as part of the current mirror, replicates the output current of the detection circuit. Its source is connected to the power supply terminal VDD, its drain is connected to the drain of the first NMOS transistor NM0 via an enable transistor EN, and its gate is connected to another PMOS transistor in the current mirror (…). Figure 3 The gate of the first NMOS transistor (NM0) is connected to the gate of the PMOS transistor located above it. The source of the first NMOS transistor NM0 is grounded, and its gate is connected to its drain. The gate of the second NMOS transistor NM1 is connected to the gate of the first NMOS transistor NM0, its source is grounded, and its drain is connected to the fourth reference current source I. ref 3. The gate of the third NMOS transistor NM2 is connected to the gate of the first NMOS transistor NM0, the source is grounded, and the drain is connected to the third reference current source I. ref 2. Connected; the gate of the fourth NMOS transistor NM3 is connected to the gate of the first NMOS transistor NM0, the source is grounded, and the drain is connected to the second reference current source I. ref 1. Connected; the gate of the fifth NMOS transistor NM4 is connected to the gate of the first NMOS transistor NM0, the source is grounded, and the drain is connected to the first reference current source I. ref 0 is connected; the drains of the second NMOS transistor NM1, the third NMOS transistor NM2, the fourth NMOS transistor NM3, and the fifth NMOS transistor NM4 also serve as inputs to combinational logic circuits.

[0028] The combinational logic circuit includes a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a first AND gate, a second AND gate, a third AND gate, a first OR gate, and a second OR gate; the input terminal of the first NOT gate is connected to the drain of the second NMOS transistor NM1, and its output terminal serves as the first output terminal R of the combinational logic circuit. <2> The input of the second NOT gate is connected to the drain of the third NMOS transistor NM2, and its output is connected to the first input of the first AND gate. The input of the third NOT gate is connected to the drain of the fourth NMOS transistor NM3, and its output is connected to the first input of the second AND gate. The input of the fourth NOT gate is connected to the drain of the fifth NMOS transistor NM4, and its output is connected to the first input of the third AND gate. The second input of the first AND gate is connected to the drain of the second NMOS transistor NM1, and its output is connected to the first input of the first OR gate and the second OR gate. The second input of the second AND gate is connected to the drain of the third NMOS transistor NM2, and its output is connected to the second input of the first OR gate. The second input of the third AND gate is connected to the drain of the fourth NMOS transistor NM3, and its output is connected to the second input of the second OR gate. The output of the first OR gate serves as the second output R of the combinational logic circuit. <1> The output of the second OR gate serves as the third output R of the combinational logic circuit. <0> .

[0029] The entire array is divided into blocks, each sharing a write current amplitude configuration. The row and column address sensing module determines the block address to which the selected cell belongs by using the row and column addresses of the selected cell. Then, using the selected bit line data pattern sensing result and the block address as an index, the optimal write current amplitude is found in the write current amplitude configuration table through the lookup table module. The write current amplitude configuration table can be pre-stored in the lookup table module, for example, it can be implemented using SRAM or DRAM, or it can be implemented by reserving space in a three-dimensional phase-change memory or other non-volatile memory to store the write current amplitude configuration table. When the memory is powered on, the write current amplitude configuration table is written to the lookup table module, and the optimal write current amplitude configuration can be adjusted by modifying the configuration data.

[0030] Finally, the write driver module outputs a write current of the corresponding magnitude to the selected cell based on the output of the lookup table module. This implementation achieves data pattern awareness and row / column address awareness of the write current, reducing overprogramming while ensuring the completion of the write operation, reducing thermal interference in the 3D phase-change memory array, and extending the lifespan of the memory cells, thereby improving the reliability of the 3D phase-change memory.

[0031] It is easy to see that this invention, by adding a pre-detection operation before the write operation, determines the data state on the selected bit line, and controls the write driver to output a write current pulse of appropriate amplitude based on the data state on the selected bit line and the address of the selected cell through the lookup table index result, realizes the data pattern perception and row and column address perception of the write current. This reduces the degree of overprogramming while ensuring the completion of the write operation, reduces thermal interference in the three-dimensional phase change memory array, and improves the lifespan of the memory cell, thereby improving the reliability of the three-dimensional phase change memory.

Claims

1. A high-reliability write circuit for a three-dimensional phase-change memory, characterized in that, include: The bit line data sensing module is used to determine the data status of the selected bit line. The bit line data sensing module includes a detection circuit, a current comparator, and a register connected in sequence. The detection circuit is used to generate an output current based on the selected bit line; the current comparator is used to determine the data state on the selected bit line based on the magnitude of the output current; and the register is used to store the data state on the selected bit line determined by the current comparator. The current comparator replicates the output current of the detection circuit via a current mirror and compares it with four different reference currents to determine the data state on the selected bit line. The current comparator includes a PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The PMOS transistor, as part of the current mirror, replicates the output current of the detection circuit. Its source is connected to the power supply terminal, its drain is connected to the drain of the first NMOS transistor via an enable transistor, and its gate is connected to the gate of another PMOS transistor in the current mirror. The source of the first NMOS transistor is grounded, and its gate is connected to its drain. The second NMOS transistor... The gate of the MOS transistor is connected to the gate of the first NMOS transistor, the source is grounded, and the drain is connected to the fourth reference current source; the gate of the third NMOS transistor is connected to the gate of the first NMOS transistor, the source is grounded, and the drain is connected to the third reference current source; the gate of the fourth NMOS transistor is connected to the gate of the first NMOS transistor, the source is grounded, and the drain is connected to the second reference current source; the gate of the fifth NMOS transistor is connected to the gate of the first NMOS transistor, the source is grounded, and the drain is connected to the first reference current source; the drains of the second, third, fourth, and fifth NMOS transistors also serve as inputs to combinational logic circuits; The combinational logic circuit includes a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a first AND gate, a second AND gate, a third AND gate, a first OR gate, and a second OR gate. The input of the first NOT gate is connected to the drain of a second NMOS transistor, and its output serves as the first output of the combinational logic circuit. The input of the second NOT gate is connected to the drain of a third NMOS transistor, and its output is connected to the first input of the first AND gate. The input of the third NOT gate is connected to the drain of a fourth NMOS transistor, and its output is connected to the first input of the second AND gate. The input of the fourth NOT gate is connected to the drain of a fifth NMOS transistor, and its output is connected to the first input of the second AND gate. The first input terminal of the third AND gate is connected to the first input terminal of the third AND gate; the second input terminal of the first AND gate is connected to the drain of the second NMOS transistor, and the output terminal is connected to the first input terminal of the first OR gate and the second OR gate respectively; the second input terminal of the second AND gate is connected to the drain of the third NMOS transistor, and the output terminal is connected to the second input terminal of the first OR gate; the second input terminal of the third AND gate is connected to the drain of the fourth NMOS transistor, and the output terminal is connected to the second input terminal of the second OR gate; the output terminal of the first OR gate serves as the second output terminal of the combinational logic circuit; the output terminal of the second OR gate serves as the third output terminal of the combinational logic circuit. The row and column address sensing module is used to determine the block address to which the selected cell belongs based on the row and column addresses of the selected cell; The lookup table module is used to find the optimal write current amplitude stored in the write current amplitude configuration table by using the data status on the selected bit line and the block address to which the selected unit belongs as an index. The write driver module is used to output the write current with the optimal write current amplitude to the selected unit.

2. The high-reliability write circuit for the three-dimensional phase-change memory according to claim 1, characterized in that, During detection, the detection circuit connects the detection voltage to the selected bit line and keeps the word line at 0V to obtain the output current.

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