Epitaxial Structure, Semiconductor Device, and Preparation Method

Abstract

Embodiments of the present application relate to a method for preparing an epitaxial structure, an epitaxial structure, a method for preparing a semiconductor device, and a semiconductor device. A buffer layer is epitaxially grown on a substrate; a first high-resistance semiconductor layer is epitaxially grown on the buffer layer; a part of the first high-resistance semiconductor layer is removed to form at least two grooves extending from the upper surface of the first high-resistance semiconductor layer to the inside of the first high-resistance semiconductor layer. The at least two grooves include a first groove and a second groove. Wherein, the part of the first high-resistance semiconductor layer located between the first groove and the second groove is not removed to form isolation sidewalls; a low-resistance semiconductor layer is epitaxially grown on the first high-resistance semiconductor layer; a first device material layer is epitaxially grown on the part of the low-resistance semiconductor layer located in the first groove, and the first device material layer is formed of a semiconductor material different from that of the low-resistance semiconductor layer; thus, at least two devices made of different semiconductor materials can be integrated on the same substrate.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a method for preparing an epitaxial structure, an epitaxial structure, a method for preparing a semiconductor device, and a semiconductor device. Background Art

[0002] With the rapid development of technologies such as consumer electronics, aerospace electronics, and military electronics, semiconductor devices, which are the core of modern information technology, must be miniaturized, lightweight, highly integrated, and highly reliable to the greatest extent. Integrating multiple devices on a single substrate can not only reduce the overall volume of the devices but also solve the parasitic capacitance problem caused by the external interconnection lines of the chips, thereby improving the overall performance of the devices. However, while noticing many advantages, how to overcome the technological difficulties has become the primary problem that those skilled in the art need to solve.

[0003] Taking gallium nitride (GaN) devices and gallium oxide (Ga2O3) devices as examples, since both gallium nitride and gallium oxide belong to wide-bandgap semiconductor materials and have the characteristic of high breakdown voltage, vertically cascading gallium nitride devices and gallium oxide devices can form enhanced power devices. However, in terms of specific processes, since the epitaxial layer materials required for gallium nitride devices and gallium oxide devices are different, how to form both a gallium nitride epitaxial layer and a gallium oxide epitaxial layer on a single substrate, and at the same time form an isolation structure between the two to avoid mutual interference in electrical performance between the two devices, which poses a huge challenge. Currently, a monolithic integration method proposed in the prior art is to first epitaxially grow gallium oxide on the substrate, then remove a part of the gallium oxide material to expose the substrate, and then epitaxially grow gallium nitride on the exposed area of the substrate. This not only causes serious material waste but also makes the process very complex; more prominent is that when using a material with a high dielectric constant (high K) such as silicon nitride (SiN) to form the isolation structure between the two devices, if the gap between the two devices is too small, the filling difficulty of the high-K material is very large, and it is impossible to ensure that the high-K material can be effectively filled, and thus the isolation effect cannot be guaranteed; in order to avoid isolation failure, a relatively large gap often needs to be left, but this in turn limits the further miniaturization of the devices. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a method for preparing an epitaxial structure, an epitaxial structure, a method for preparing a semiconductor device, and a semiconductor device to solve at least one problem in the background art.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing an epitaxial structure, the method comprising:

[0006] Epitaxially growing a buffer layer on a substrate;

[0007] Epitaxially grow a first high-resistance semiconductor layer on the buffer layer;

[0008] Remove a part of the first high-resistance semiconductor layer to form at least two grooves extending from the upper surface of the first high-resistance semiconductor layer into the interior of the first high-resistance semiconductor layer. The at least two grooves include a first groove and a second groove. Among them, the part of the first high-resistance semiconductor layer located between the first groove and the second groove is not removed to form an isolation sidewall;

[0009] Epitaxially grow a low-resistance semiconductor layer on the first high-resistance semiconductor layer;

[0010] Epitaxially grow a first device material layer on the part of the low-resistance semiconductor layer located in the first groove. The first device material layer is formed of a semiconductor material different from that of the low-resistance semiconductor layer.

[0011] Combined with the first aspect of the present application, in an alternative embodiment, the first device material layer is a gallium oxide-based semiconductor material layer, and the low-resistance semiconductor layer is a gallium nitride-based semiconductor material layer.

[0012] Combined with the first aspect of the present application, in an alternative embodiment,

[0013] After epitaxially growing the buffer layer on the substrate, the method further includes: removing a part of the buffer layer to form at least two through holes exposing the substrate;

[0014] The epitaxial growth of the first high-resistance semiconductor layer on the buffer layer includes: epitaxially growing the first high-resistance semiconductor layer on the remaining buffer layer and on the regions of the substrate exposed through at least two through holes.

[0015] Combined with the first aspect of the present application, in an alternative embodiment,

[0016] The removal of a part of the first high-resistance semiconductor layer includes: removing a part of the first high-resistance semiconductor layer formed on the remaining buffer layer.

[0017] Combined with the first aspect of the present application, in an alternative embodiment, after epitaxially growing the low-resistance semiconductor layer on the first high-resistance semiconductor layer, the method further includes:

[0018] Removing the low-resistance semiconductor layer formed on the isolation sidewall;

[0019] Epitaxially grow a second high-resistance semiconductor layer on the remaining low-resistance semiconductor layer and on the isolation sidewall;

[0020] Remove a portion of the second high-resistance semiconductor layer to form at least two openings exposing the low-resistance semiconductor layer, where the at least two openings include a first opening and a second opening, and wherein the first opening is located above the first groove and the second opening is located above the second groove;

[0021] The first device material layer grows epitaxially along the portion of the low-resistance semiconductor layer exposed through the first opening.

[0022] In combination with the first aspect of the present application, in an alternative embodiment, the method further includes:

[0023] Grow a second device material layer epitaxially on the portion of the low-resistance semiconductor layer located within the second groove, where the second device material layer is formed of a semiconductor material different from that of the first device material layer.

[0024] In combination with the first aspect of the present application, in an alternative embodiment, the first device material layer is a gallium oxide layer, the low-resistance semiconductor layer is a gallium nitride layer, and the second device material layer is an aluminum gallium nitride layer.

[0025] In combination with the first aspect of the present application, in an alternative embodiment, the material of the first high-resistance semiconductor layer is carbon-doped and / or iron-doped gallium nitride.

[0026] In a second aspect, an embodiment of the present application provides an epitaxial structure, including:

[0027] A substrate;

[0028] A buffer layer located on the substrate;

[0029] A first high-resistance semiconductor layer located on the buffer layer;

[0030] At least two grooves extending from the upper surface of the first high-resistance semiconductor layer into the first high-resistance semiconductor layer, where the at least two grooves include a first groove and a second groove, and wherein the portion of the first high-resistance semiconductor layer located between the first groove and the second groove forms an isolation sidewall;

[0031] A low-resistance semiconductor layer located within the first groove and the second groove;

[0032] A first device material layer formed on the portion of the low-resistance semiconductor layer located within the first groove, where the first device material layer is formed of a semiconductor material different from that of the low-resistance semiconductor layer.

[0033] In combination with the second aspect of the present application, in an alternative embodiment, the first device material layer is a gallium oxide-based semiconductor material layer, and the low-resistance semiconductor layer is a gallium nitride-based semiconductor material layer.

[0034] In combination with the second aspect of the present application, in an alternative embodiment, it further includes:

[0035] At least two through holes penetrating the buffer layer;

[0036] The first high-resistance semiconductor layer is also located in the through holes and is connected to the substrate.

[0037] In combination with the second aspect of the present application, in an alternative embodiment, the vertical projection of the low-resistance semiconductor layer on the substrate plane falls within the range of the vertical projection of the buffer layer on the substrate plane.

[0038] In combination with the second aspect of the present application, in an alternative embodiment, it further includes:

[0039] A second high-resistance semiconductor layer covering the low-resistance semiconductor layer and the isolation sidewalls;

[0040] At least two openings penetrating the second high-resistance semiconductor layer, and the at least two openings include a first opening and a second opening, wherein the first opening is located above the first groove, and the second opening is located above the second groove;

[0041] The first device material layer is connected to the low-resistance semiconductor layer through the first opening.

[0042] In combination with the second aspect of the present application, in an alternative embodiment, it further includes:

[0043] A second device material layer epitaxially grown on a portion of the low-resistance semiconductor layer located in the second groove, and the second device material layer is formed of a semiconductor material different from that of the first device material layer.

[0044] In combination with the second aspect of the present application, in an alternative embodiment, the first device material layer is a gallium oxide layer, the low-resistance semiconductor layer is a gallium nitride layer, and the second device material layer is an aluminum gallium nitride layer.

[0045] In combination with the second aspect of the present application, in an alternative embodiment, the material of the first high-resistance semiconductor layer is carbon-doped and / or iron-doped gallium nitride.

[0046] In a third aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, and the method includes the steps in the method for manufacturing an epitaxial structure according to any one of the above first aspects, or includes manufacturing a semiconductor device by using the epitaxial structure according to any one of the above second aspects.

[0047] Fourthly, an embodiment of the present application provides a semiconductor device, including the epitaxial structure described in any one of the second aspects above, or prepared by using the epitaxial structure described in any one of the second aspects above.

[0048] In the preparation method of the epitaxial structure, the epitaxial structure, the preparation method of the semiconductor device, and the semiconductor device provided by the embodiments of the present application, a buffer layer is epitaxially grown on a substrate; a first high-resistance semiconductor layer is epitaxially grown on the buffer layer; a part of the first high-resistance semiconductor layer is removed to form at least two grooves extending from the upper surface of the first high-resistance semiconductor layer to the inside of the first high-resistance semiconductor layer. The at least two grooves include a first groove and a second groove. Among them, the part of the first high-resistance semiconductor layer located between the first groove and the second groove is not removed to form isolation sidewalls; a low-resistance semiconductor layer is epitaxially grown on the first high-resistance semiconductor layer; a first device material layer is epitaxially grown on the part of the low-resistance semiconductor layer located in the first groove. The first device material layer and the low-resistance semiconductor layer are formed of different semiconductor materials. In this way, two regions respectively used to form different devices can be defined by the first groove and the second groove. Among them, the first device material layer located above the first groove can be used to form a first device, and the low-resistance semiconductor layer located above the second groove can be used to form a second device, so as to realize the integration of at least two devices made of different semiconductor materials on the same substrate, with less material waste in the process and reduced production costs; the first groove and the second groove are isolated by the first high-resistance semiconductor layer (specifically, the isolation sidewalls), which can not only ensure electrical isolation between the subsequent prepared devices, but also does not require deep trench filling, reducing the process difficulty and facilitating the miniaturization of the devices.

[0049] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present application. Description of the Drawings

[0050] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation to the present application. In the drawings:

[0051] Figure 1 It is a schematic flow chart of the preparation method of the epitaxial structure provided by the embodiment of the present application;

[0052] Figures 2 to 11 It is a schematic cross-sectional structure diagram of the epitaxial structure in the preparation process of a specific example;

[0053] Figure 12 It is a schematic cross-sectional structure diagram of the semiconductor device in the preparation process of a specific example. Detailed Embodiments

[0054] Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application disclosed can be fully conveyed to those skilled in the art.

[0055] In the following description, numerous specific details are given in order to provide a more thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application may be practiced without one or more of these details. In other instances, some well-known technical features are not described in order to avoid obscuring the present application; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0056] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals throughout the drawings denote the same elements.

[0057] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section.

[0058] Spatial relationship terms such as "under", "beneath", "on", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the drawings to other elements or features. It should be understood that, in addition to the orientation shown in the drawings, spatial relationship terms are intended to also include different orientations of the device during use and operation.

[0059] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. When used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the related listed items.

[0060] To thoroughly understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may have other implementation manners.

[0061] First, please refer to Figure 1 . An embodiment of the present application provides a method for preparing an epitaxial structure, the method comprising:

[0062] Step 101, epitaxially growing a buffer layer on a substrate;

[0063] Step 102, epitaxially growing a first high-resistance semiconductor layer on the buffer layer;

[0064] Step 103, removing a part of the first high-resistance semiconductor layer to form at least two grooves extending from the upper surface of the first high-resistance semiconductor layer to the inside of the first high-resistance semiconductor layer. The at least two grooves include a first groove and a second groove. Among them, the part of the first high-resistance semiconductor layer located between the first groove and the second groove is not removed to form isolation sidewalls;

[0065] Step 104, epitaxially growing a low-resistance semiconductor layer on the first high-resistance semiconductor layer;

[0066] Step 105, epitaxially growing a first device material layer on the part of the low-resistance semiconductor layer located in the first groove. The first device material layer is formed of a semiconductor material different from that of the low-resistance semiconductor layer.

[0067] Wherein, the material of the substrate may include at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material or other semiconductor materials known in the art, and other substrates containing semiconductor materials may also be used. Specifically, for example, a silicon substrate, a germanium substrate, a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium oxide substrate, etc. may be used.

[0068] The function of the buffer layer is to reduce the lattice mismatch between the substrate material and the first high-resistance semiconductor layer material, and at the same time provide a nucleation layer for the epitaxial growth of the first high-resistance semiconductor layer.

[0069] The first high-resistance semiconductor layer can also be referred to as the first insulating semiconductor layer. On the one hand, a semiconductor material is used to provide a basis for the epitaxial growth of other semiconductor layers stacked on the first high-resistance semiconductor layer subsequently. On the other hand, the conductivity of the semiconductor material is reduced as much as possible to form a high-resistance layer that can block the movement of carriers, so as to form an insulating isolation between different devices. The reduction of the conductivity of the semiconductor material can be achieved by one or a combination of methods such as non-doping (i.e., forming an intrinsic semiconductor layer), insulating P-type doping (such as carbon doping or iron doping of gallium nitride, etc.), and incorporation of oxygen elements.

[0070] The first groove and the second groove can define two regions respectively for forming different devices. Among them, the first device material layer located above the first groove can be used to form the first device, and the low-resistance semiconductor layer located above the second groove can be used to form the second device, so as to integrate at least two devices made of different semiconductor materials on the same substrate, with less material waste in the process and reduced production costs.

[0071] It should be understood that only the first groove and the second groove are taken as representatives of at least two grooves for illustration here. The at least two grooves certainly also include the third groove, and even the fourth groove, the fifth groove, etc. Each groove can respectively correspond to forming different types of devices, or a part of the grooves can correspond to forming one type of device, and another part of the grooves can correspond to forming another type of device. The present application does not make specific limitations on this.

[0072] The low-resistance semiconductor layer can also be referred to as a conductive semiconductor layer. For example, the conductivity of the semiconductor material is improved by N-type or P-type doping. The low-resistance semiconductor layer provides a substrate material for the preparation of subsequent devices.

[0073] The first device material layer is made of a semiconductor material different from that of the low-resistance semiconductor layer, so as to be used for preparing different types of semiconductor devices.

[0074] Using the first high-resistance semiconductor layer as the electrical isolation structure between devices not only effectively avoids the mutual interference of devices in electrical performance, but also does not require deep trench filling, reduces the process difficulty, and is conducive to the miniaturization of devices.

[0075] The epitaxial growth mentioned in the embodiments of the present application can be realized by using the MOCVD (Metal Organic Chemical Vapor Deposition) process.

[0076] As an optional implementation manner, the first device material layer is a gallium oxide-based semiconductor material layer, and the low-resistance semiconductor layer is a gallium nitride-based semiconductor material layer. Exemplarily, the first device material layer is a gallium oxide layer, and the low-resistance semiconductor layer is a gallium nitride layer.

[0077] The lattice mismatch generated by epitaxially growing gallium oxide on gallium nitride is much smaller than that generated by directly epitaxially growing gallium oxide on substrates such as silicon or sapphire. Therefore, growing a gallium nitride-based semiconductor material layer in the groove first is beneficial to improving the crystallization quality of the first device material layer, that is, it is beneficial to grow a high-quality gallium oxide-based semiconductor material layer, thereby improving the device performance. In addition, the heat dissipation of the gallium oxide-based semiconductor material is poor. The gallium nitride-based semiconductor material layer formed below the gallium oxide-based semiconductor material layer helps to dissipate the heat generated during the operation of the first device, avoiding adverse effects on the device caused by excessive temperature.

[0078] Both gallium oxide and gallium nitride have relatively large bandgaps, which are suitable for preparing high-power devices with high breakdown resistance requirements. For example, a Ga2O3 FET (Field Effect Transistor) is prepared using the first groove, and a GaN HEMT (High Electron Mobility Transistor) is prepared using the second groove. In addition, both gallium oxide and gallium nitride can be used to make optical devices. For example, a solar-blind photodetector is prepared using the first groove, and an ultraviolet photodetector is prepared using the second groove, etc. Of course, one of them can also be used to make an optical device, and the other is used to prepare a power device. For example, one is made into a photodetector, and the other is prepared into a power amplifier or a power switch element, thereby combining to form an optoelectronic device, converting an optical signal into an electrical signal, then amplifying the electrical signal and inputting it, or using the converted electrical signal to control the opening and closing of the power switch element to form optoelectronic isolation.

[0079] Furthermore, corresponding to the low-resistance semiconductor layer being a gallium nitride layer, the material of the buffer layer can also include gallium nitride.

[0080] As an alternative implementation, the material of the first high-resistance semiconductor layer is carbon-doped and / or iron-doped gallium nitride. Incorporating carbon and / or iron into gallium nitride will introduce a large number of defects, increasing the material resistance and forming a high-resistance semiconductor layer.

[0081] As an alternative implementation, the method further includes: epitaxially growing a second device material layer on a part of the low-resistance semiconductor layer located in the second groove, and the second device material layer is formed of a semiconductor material different from that of the first device material layer.

[0082] Furthermore, the second device material layer can be the same as the low-resistance semiconductor layer, both being gallium nitride-based semiconductor material layers.

[0083] Specifically, for example, the low-resistance semiconductor layer is a gallium nitride layer, and the second device material layer is an aluminum gallium nitride (AlGaN) layer. In this way, it is convenient to fabricate a GaN HEMT using the low-resistance semiconductor layer and the second device material layer. The low-resistance semiconductor layer is used to form the channel layer of the GaN HEMT, and the second device material layer is used to form the barrier layer of the GaN HEMT. A two-dimensional electron gas channel is formed in at least a part of the channel layer close to the barrier layer.

[0084] In order to integrate devices that need to be fabricated on different epitaxial materials on the same substrate, the method for preparing the epitaxial structure provided in this embodiment epitaxially grows a first device material layer on a part of the low-resistance semiconductor layer located in the first groove, and epitaxially grows a second device material layer on a part of the low-resistance semiconductor layer located in the second groove. The material of the second device material layer is different from that of the first device material layer, realizing providing the respective required epitaxial materials for different devices.

[0085] As an optional implementation manner, after epitaxially growing a buffer layer on the substrate, the above method further includes: removing a part of the buffer layer to form at least two through holes exposing the substrate; epitaxially growing a first high-resistance semiconductor layer on the buffer layer, including: epitaxially growing the first high-resistance semiconductor layer on the remaining buffer layer and on the regions of the substrate exposed through the at least two through holes.

[0086] It can be understood that a part of the first high-resistance semiconductor layer grows epitaxially along the buffer layer, and a part grows epitaxially along the substrate. The internal stresses of the two parts are opposite, which is beneficial to the release of internal stress and the realization of stress balance, thereby being beneficial to improving the epitaxial growth quality of the first high-resistance semiconductor layer.

[0087] Further optionally, removing a part of the first high-resistance semiconductor layer includes: removing a part of the first high-resistance semiconductor layer formed on the remaining buffer layer.

[0088] It is easy to understand that the buffer layer, as a functional layer for reducing the lattice mismatch between the substrate material and the first high-resistance semiconductor layer material, the crystal quality of growing the first high-resistance semiconductor layer above the buffer layer is obviously better than that of growing the first high-resistance semiconductor layer above the substrate. Therefore, removing the part with better growth quality formed on the remaining buffer layer to form a groove for fabricating the device functional layer; and the part with worse growth quality formed above the substrate can be used to form an isolation sidewall.

[0089] As an alternative embodiment, after epitaxially growing a low-resistance semiconductor layer on the first high-resistance semiconductor layer, the above method further includes: removing the low-resistance semiconductor layer formed on the isolation sidewall; epitaxially growing a second high-resistance semiconductor layer on the remaining low-resistance semiconductor layer and the isolation sidewall; removing a part of the second high-resistance semiconductor layer to form at least two openings exposing the low-resistance semiconductor layer, where the at least two openings include a first opening and a second opening, and the first opening is located above the first groove and the second opening is located above the second groove; and epitaxially growing a first device material layer along the part of the low-resistance semiconductor layer exposed through the first opening.

[0090] Among them, removing the low-resistance semiconductor layer formed on the isolation sidewall can be achieved by a Chemical Mechanical Polishing (CMP) process. By removing the low-resistance semiconductor layer formed on the isolation sidewall, the second high-resistance semiconductor layer can be connected to the isolation sidewall in the first high-resistance semiconductor layer, and a closed isolation structure is formed between the first device and the second device.

[0091] The material of the second high-resistance semiconductor layer can be the same as that of the first high-resistance semiconductor layer; that is, the material of the second high-resistance semiconductor layer can also be gallium nitride doped with carbon and / or iron. The thickness of the second high-resistance semiconductor layer can be less than that of the first high-resistance semiconductor layer.

[0092] The second high-resistance semiconductor layer can be used as a passivation layer, and the at least two openings can define the areas that need to be processed for the first device and the second device in subsequent processes. In this way, self-alignment of device fabrication is effectively achieved.

[0093] Next, a specific example is used to further elaborate on the method for preparing the epitaxial structure provided in the embodiments of the present application.

[0094] First, please refer to Figure 2 . Provide a substrate 210.

[0095] Among them, the substrate 210 is specifically a silicon substrate or a sapphire substrate.

[0096] Next, please refer to Figure 3 . Epitaxially grow a buffer layer 220 on the substrate 210.

[0097] The material of the buffer layer 220 can be selected by those skilled in the art according to the materials of the first high-resistance semiconductor layer and the low-resistance semiconductor layer to be grown subsequently. In this specific example, the material of the buffer layer 220 is gallium nitride.

[0098] The buffer layer 220 is formed by a low-temperature growth process. For example, a gallium nitride buffer layer is epitaxially grown at a temperature of about 535 degrees Celsius. In this way, internal stress can be effectively released, and lattice mismatch and thermal mismatch can be reduced.

[0099] Next, please refer to Figure 4 . Remove a part of the buffer layer 220 to form at least two through-holes (please refer to 221 and 222 in the figure) exposing the substrate 210.

[0100] The through-holes are formed by a dry etching process or a wet etching process, and the present application does not make specific limitations thereon.

[0101] The through-holes can serve as stress release regions for the subsequent epitaxial growth process. In addition, the positions where the through-holes are located will also become the positions of isolation sidewalls in the subsequent process.

[0102] Next, please refer to Figure 5 . Epitaxially grow a first high-resistance semiconductor layer 230 on the remaining buffer layer 220 and on the regions of the substrate 210 exposed through at least two through-holes 221 and 222.

[0103] Among them, the material of the first high-resistance semiconductor layer 230 is gallium nitride doped with carbon and / or iron. The first high-resistance semiconductor layer 230 is formed by a high-temperature growth process. The first high-resistance semiconductor layer 230 will be formed into an electrical isolation structure between devices in the subsequent process.

[0104] Exposing a part of the substrate 210 through the through-holes enables the first high-resistance semiconductor layer 230 to grow epitaxially partially along the buffer layer 220 and partially along the substrate 210. The internal stresses of the two parts are opposite, which is beneficial to the release of internal stress and the realization of stress balance, making the epitaxial growth quality of the first high-resistance semiconductor layer 230 higher.

[0105] Due to the existence of the through-holes, the starting surface of the epitaxial growth of the first high-resistance semiconductor layer 230 is not flat, resulting in the upper surface of the first high-resistance semiconductor layer 230 formed after epitaxial growth also having a similar concave-convex morphology. As Figure 5 shown, specifically, at the positions corresponding to the through-holes 221 and 222, the upper surface of the first high-resistance semiconductor layer 230 is recessed towards the substrate 210.

[0106] As mentioned above, the part of the first high-resistance semiconductor layer 230 that grows epitaxially upward along the buffer layer 220 has better crystal quality, while the part that grows epitaxially upward along the substrate 210 has poorer crystal quality. Correspondingly, as Figure 5 shown, the part of the upper surface of the first high-resistance semiconductor layer 230 that protrudes has better crystal quality, while the part that is recessed has poorer crystal quality.

[0107] Next, please refer to Figure 6. Part of the first high-resistance semiconductor layer 230 is removed to form at least two grooves extending from the upper surface of the first high-resistance semiconductor layer 230 into the interior of the first high-resistance semiconductor layer 230 (please refer to 231, 232, and 233 in the figure). The at least two grooves include a first groove 231 and a second groove 232. Among them, the part of the first high-resistance semiconductor layer 230 located between the first groove 231 and the second groove 232 is not removed to form isolation sidewalls (please refer to 234 and 235 in the figure).

[0108] Understandably, the present application does not specifically limit the number of grooves. Figure 6 The third groove 233 is also shown in the figure.

[0109] Each groove can be formed by a dry etching process, thereby defining regions for preparing each device in the first high-resistance semiconductor layer 230, and playing a positioning role in subsequent process steps. The bottom and sidewalls of each groove are made of the first high-resistance semiconductor material, thereby providing relatively independent electrical isolation regions for each device. The size of each groove can be set according to the size of each device to be formed.

[0110] Removing part of the first high-resistance semiconductor layer 230 can specifically be removing the part of the first high-resistance semiconductor layer 230 formed on the remaining buffer layer 220. Thus, grooves are formed in the part with better crystal quality, providing a good foundation for the growth of the subsequent low-resistance semiconductor layer and other device functional layers; while the part with poor growth quality can be used to form isolation sidewalls.

[0111] In the actual process, since the upper surface of the first high-resistance semiconductor layer 230 is uneven, the part corresponding to the sunken position has relatively poor growth quality. Therefore, it is only necessary to etch downward the protruding part on the upper surface of the first high-resistance semiconductor layer 230 to form grooves, without the need to additionally set alignment marks.

[0112] Next, please refer to Figure 7 . A low-resistance semiconductor layer 240 is epitaxially grown on the first high-resistance semiconductor layer 230.

[0113] In this specific example, the low-resistance semiconductor layer 240 is an N-type low-doped gallium nitride layer; specifically, it is formed by doping magnesium (Mg) elements into gallium nitride. Of course, the present application does not exclude that the low-resistance semiconductor layer 240 is a P-type low-doped gallium nitride layer; specifically, it is formed by doping silicon (Si) elements into gallium nitride. The low-resistance semiconductor layer 240 provides a substrate material for the preparation of subsequent devices.

[0114] Since the first high-resistance semiconductor layer 230 is etched to form at least two grooves, the low-resistance semiconductor layer 240 is partially formed in the grooves and partially formed above the isolation sidewalls.

[0115] Next, please refer toFigure 8 Remove the low-resistance semiconductor layer 240 formed on the isolation sidewalls.

[0116] Specifically, compare Figure 7 and Figure 8 , and the portion of the low-resistance semiconductor layer 240 above the isolation sidewalls 234 and 235 is removed. In actual fabrication, a CMP process can be used to achieve this.

[0117] Next, please refer to Figure 9 . Epitaxially grow a second high-resistance semiconductor layer 250 on the remaining low-resistance semiconductor layer 240 and on the isolation sidewalls 234 and 235.

[0118] Among them, the material of the second high-resistance semiconductor layer 250 is specifically gallium nitride doped with carbon and / or iron. The second high-resistance semiconductor layer 250 is connected to the isolation sidewalls 234 and 235 to form a passivation layer covering the non-processed area.

[0119] Next, please refer to Figure 10 . Remove a portion of the second high-resistance semiconductor layer 250 to form at least two openings exposing the low-resistance semiconductor layer 240. The at least two openings include a first opening 251 and a second opening 252. Among them, the first opening 251 is located above the first groove 231, and the second opening 252 is located above the second groove 232.

[0120] The first opening 251 and the second opening 252 define the areas that need to be processed for the first device and the second device in subsequent processes, effectively achieving self-alignment in device fabrication.

[0121] Next, please refer to Figure 11 . Epitaxially grow a first semiconductor material layer 261 on the portion of the low-resistance semiconductor layer 240 located within the first groove 231, and epitaxially grow a second semiconductor material layer 262 on the portion of the low-resistance semiconductor layer 240 located within the second groove 232.

[0122] Specifically, the first semiconductor material layer 261 is located on the portion of the low-resistance semiconductor layer 240 exposed through the first opening 251; the second semiconductor material layer 262 is located on the portion of the low-resistance semiconductor layer 240 exposed through the second opening 252. The first semiconductor material layer 261 and the second semiconductor material layer 262 are isolated by the second high-resistance semiconductor layer 250.

[0123] In this specific example, the material of the first semiconductor material layer 261 is gallium oxide, and the material of the second semiconductor material layer is aluminum gallium nitride. In this way, for example, a monolithic integrated device for forming a Ga2O3 FET and a GaN HEMT, or a monolithic integrated device for forming a Ga2O3 solar-blind photodetector and a GaN HEMT can be formed.

[0124] In the preparation method of the epitaxial structure provided in this specific example, carbon-doped and / or iron-doped silicon nitride is used to form the first high-resistance semiconductor layer 230 and the second high-resistance semiconductor layer 250, which simply and efficiently realizes the self-alignment and self-isolation of the device on the two high-resistance semiconductor layers, eliminates the need for deep trench filling, reduces the process difficulty, and is conducive to realizing the highly integrated interconnection of Ga2O3 / GaN devices and the miniaturization of the devices. Moreover, the above method has less etching amount of the epitaxial material, saves production costs, and reduces the pollution to the device surface and the etching chamber. In addition, for the epitaxial structure obtained by this preparation method, the crystallization quality of each epitaxial layer is high, which is conducive to improving the overall performance of the final device.

[0125] On this basis, the embodiment of the present application further provides an epitaxial structure. Please continue to refer to Figure 11 . The epitaxial structure includes: a substrate 210; a buffer layer 220 located on the substrate 210; a first high-resistance semiconductor layer 230 located on the buffer layer 220; at least two grooves extending from the upper surface of the first high-resistance semiconductor layer 230 to the inside of the first high-resistance semiconductor layer 230. The at least two grooves include a first groove 231 and a second groove 232. Among them, the part of the first high-resistance semiconductor layer 230 located between the first groove 231 and the second groove 232 forms an isolation sidewall 234; a low-resistance semiconductor layer 240 located in the first groove 231 and the second groove 232; a first device material layer 261 formed on the part of the low-resistance semiconductor layer 240 located in the first groove 231. The first device material layer 261 and the low-resistance semiconductor layer 240 are formed of different semiconductor materials.

[0126] In the epitaxial structure provided in this embodiment, the first high-resistance semiconductor layer 230 is used as an isolation structure, and two regions respectively used for forming different devices are defined by the first groove 231 and the second groove 232, so that the self-alignment of the devices can be realized during subsequent device preparation. The first device material layer 261 located above the first groove 231 can be used to form a first device, and the low-resistance semiconductor layer 240 located above the second groove 232 can be used to form a second device, so as to integrate at least two devices made of different semiconductor materials on the same substrate 210. The first groove 231 and the second groove 232 are isolated by the first high-resistance semiconductor layer 230 (specifically, the isolation sidewall 234), effectively ensuring the electrical isolation between the devices prepared subsequently and being conducive to the miniaturization of the devices.

[0127] As an optional implementation manner, the first device material layer 261 is a gallium oxide-based semiconductor material layer, and the low-resistance semiconductor layer 240 is a gallium nitride-based semiconductor material layer.

[0128] As an alternative embodiment, the epitaxial structure further includes: at least two through holes penetrating the buffer layer 220 (please refer to 221 and 222 in the figure); the first high-resistance semiconductor layer 230 is also located within the through holes and is connected to the substrate 210.

[0129] As an alternative embodiment, the vertical projection of the low-resistance semiconductor layer 240 on the substrate plane falls within the range of the vertical projection of the buffer layer 220 on the substrate plane.

[0130] Herein, the substrate plane refers to the upper surface or the lower surface of the substrate 210, or strictly speaking, the central plane in the thickness direction of the substrate 210.

[0131] As an alternative embodiment, the epitaxial structure further includes: a second high-resistance semiconductor layer 250 covering the low-resistance semiconductor layer 240 and the isolation sidewalls (please refer to 234 and 235 in the figure); at least two openings penetrating the second high-resistance semiconductor layer 250, the at least two openings including a first opening 251 and a second opening 252, wherein the first opening 251 is located above the first groove 231 and the second opening 252 is located above the second groove 232; the first device material layer 261 is connected to the low-resistance semiconductor layer 240 through the first opening 251.

[0132] As an alternative embodiment, the epitaxial structure further includes: a second device material layer 262 epitaxially grown on a portion of the low-resistance semiconductor layer 240 located within the second groove 232, and the second device material layer 262 is formed of a semiconductor material different from that of the first device material layer 261.

[0133] Herein, the second device material layer 262 is connected to the low-resistance semiconductor layer 240 through the second opening 252.

[0134] As an alternative embodiment, the first device material layer 261 is a gallium oxide layer, the low-resistance semiconductor layer 240 is a gallium nitride layer, and the second device material layer 262 is an aluminum gallium nitride layer.

[0135] As an alternative embodiment, the material of the first high-resistance semiconductor layer 230 is carbon-doped and / or iron-doped gallium nitride.

[0136] Furthermore, the material of the second high-resistance semiconductor layer 250 can also be carbon-doped and / or iron-doped gallium nitride.

[0137] On this basis, the embodiment of the present application further provides a method for manufacturing a semiconductor device, and this method includes the steps in the method for manufacturing the epitaxial structure described in any of the foregoing embodiments, or includes manufacturing a semiconductor device by using the epitaxial structure described in any of the foregoing embodiments.

[0138] Specifically, the method for manufacturing the semiconductor device may include integrating different power devices on the same substrate, integrating different optoelectronic devices on the same substrate, or integrating power devices and optoelectronic devices on the same substrate. The present application does not make specific limitations thereto.

[0139] Exemplarily, the method for manufacturing the semiconductor device includes integrating a first device and a second device on the same substrate. As an alternative implementation, the first device is a Ga2O3 FET and the second device is a GaN HEMT. As another alternative implementation, the first device is a Ga2O3 solar-blind photodetector and the second device is a GaN power amplifier.

[0140] Next, with specific examples, the method for manufacturing the semiconductor device provided in the embodiments of the present application will be further described in detail.

[0141] Please refer to Figure 12 . Based on the epitaxial structure obtained by the manufacturing shown in Figure 11 , a source electrode 271, a gate electrode 272, and a drain electrode 273 of the first device are formed on the first device material layer 261; a source electrode 281, a gate electrode 282, and a drain electrode 283 of the second device are formed on the second device material layer 262.

[0142] Although Figure 12 it is shown by taking the source electrode, the gate electrode, and the drain electrode formed on the corresponding device material layer as an example, the present application is not limited thereto. For example, in order to manufacture a Ga2O3 solar-blind photodetector, the method may also include: removing a part of the second high-resistance semiconductor layer 250 above the first groove 231 to form two electrode openings exposing the low-resistance semiconductor layer 240, and forming a source electrode 271 and a drain electrode 273 connected to the low-resistance semiconductor layer 240 in the two electrode openings respectively.

[0143] On this basis, the embodiments of the present application also provide a semiconductor device, including the epitaxial structure described in any of the above embodiments, or manufactured by using the epitaxial structure described in any of the above embodiments.

[0144] It should be noted that the embodiments of the method for manufacturing the epitaxial structure, the embodiments of the epitaxial structure, the embodiments of the method for manufacturing the semiconductor device, and the embodiments of the semiconductor device provided by the present application belong to the same concept; among the technical features in the technical solutions recorded in each embodiment, they can be arbitrarily combined without conflict.

[0145] It should be understood that the above embodiments are all exemplary and do not cover all possible implementation manners included in the claims. Without departing from the scope of the present disclosure, various deformations and changes can be made on the basis of the above embodiments. Similarly, various technical features of the above embodiments can be arbitrarily combined to form additional embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only represent several implementation manners of the present application and do not limit the protection scope of the patent of the present application.

Claims

1. A method for preparing an epitaxial structure, characterized in that, The method includes: Epitaxially growing a buffer layer on a substrate; Epitaxially growing a first high-resistance semiconductor layer on the buffer layer; Removing a part of the first high-resistance semiconductor layer to form at least two grooves extending from the upper surface of the first high-resistance semiconductor layer into the interior of the first high-resistance semiconductor layer. The at least two grooves include a first groove and a second groove. Among them, the part of the first high-resistance semiconductor layer located between the first groove and the second groove is not removed to form isolation sidewalls; Epitaxially growing a low-resistance semiconductor layer on the first high-resistance semiconductor layer; Removing the low-resistance semiconductor layer formed on the isolation sidewalls. The part of the low-resistance semiconductor layer located in the first groove and the part of the low-resistance semiconductor layer located in the second groove are isolated by the isolation sidewalls; Epitaxially growing a first device material layer on the part of the low-resistance semiconductor layer located in the first groove. The first device material layer is formed of a semiconductor material different from that of the low-resistance semiconductor layer.

2. The method for preparing the epitaxial structure according to claim 1, characterized in that, The first device material layer is a gallium oxide-based semiconductor material layer, and the low-resistance semiconductor layer is a gallium nitride-based semiconductor material layer.

3. The method for preparing an epitaxial structure according to claim 1, wherein After epitaxially growing the buffer layer on the substrate, the method further includes: removing a part of the buffer layer to form at least two through holes exposing the substrate; The epitaxial growth of the first high-resistance semiconductor layer on the buffer layer includes: epitaxially growing the first high-resistance semiconductor layer on the remaining buffer layer and on the regions of the substrate exposed through the at least two through holes.

4. The method for preparing an epitaxial structure according to claim 3, wherein The removing a part of the first high-resistance semiconductor layer includes: removing a part of the first high-resistance semiconductor layer formed on the remaining buffer layer.

5. The method for preparing the epitaxial structure according to claim 1, characterized in that, After removing the low-resistance semiconductor layer formed on the isolation sidewalls, the method further includes: Epitaxially growing a second high-resistance semiconductor layer on the remaining low-resistance semiconductor layer and on the isolation sidewalls; Removing a part of the second high-resistance semiconductor layer to form at least two openings exposing the low-resistance semiconductor layer. The at least two openings include a first opening and a second opening. Among them, the first opening is located above the first groove, and the second opening is located above the second groove; The first device material layer grows epitaxially along the part of the low-resistance semiconductor layer exposed through the first opening.

6. The method for preparing the epitaxial structure according to claim 1, wherein The method further includes: Epitaxially growing a second device material layer on the part of the low-resistance semiconductor layer located in the second groove. The second device material layer is formed of a semiconductor material different from that of the first device material layer.

7. The method for preparing the epitaxial structure according to claim 6, wherein, The first device material layer is a gallium oxide layer, the low-resistance semiconductor layer is a gallium nitride layer, and the second device material layer is an aluminum gallium nitride layer.

8. The method for preparing the epitaxial structure according to any one of claims 1 to 7, characterized in that, The material of the first high-resistance semiconductor layer is carbon-doped and / or iron-doped gallium nitride.

9. An epitaxial structure, characterized in that, Including: A substrate; A buffer layer located on the substrate; A first high-resistance semiconductor layer located on the buffer layer; At least two grooves extending from the upper surface of the first high-resistance semiconductor layer into the first high-resistance semiconductor layer, the at least two grooves including a first groove and a second groove, wherein a portion of the first high-resistance semiconductor layer located between the first groove and the second groove is formed as an isolation sidewall; Low-resistance semiconductor layers located within the first groove and the second groove, with the portion of the low-resistance semiconductor layer within the first groove and the portion of the low-resistance semiconductor layer within the second groove isolated from each other by the isolation sidewall; A first device material layer formed over the portion of the low-resistance semiconductor layer within the first groove, the first device material layer being formed of a semiconductor material different from that of the low-resistance semiconductor layer.

10. The epitaxial structure according to claim 9, characterized in that, The first device material layer is a gallium oxide-based semiconductor material layer, and the low-resistance semiconductor layer is a gallium nitride-based semiconductor material layer.

11. The epitaxial structure according to claim 9, characterized in that, Further comprising: At least two through holes penetrating the buffer layer; The first high-resistance semiconductor layer is also located within the through holes and is connected to the substrate.

12. The epitaxial structure according to claim 11, wherein The vertical projection of the low-resistance semiconductor layer on the substrate plane falls within the range of the vertical projection of the buffer layer on the substrate plane.

13. The epitaxial structure according to claim 9, wherein Further comprising: A second high-resistance semiconductor layer covering the low-resistance semiconductor layer and the isolation sidewall; At least two openings penetrating the second high-resistance semiconductor layer, the at least two openings including a first opening and a second opening, wherein the first opening is located above the first groove and the second opening is located above the second groove; The first device material layer is connected to the low-resistance semiconductor layer through the first opening.

14. The epitaxial structure according to claim 9, wherein, Further comprising: A second device material layer epitaxially grown over the portion of the low-resistance semiconductor layer within the second groove, the second device material layer being formed of a semiconductor material different from that of the first device material layer.

15. The epitaxial structure according to claim 14, characterized in that, The first device material layer is a gallium oxide layer, the low-resistance semiconductor layer is a gallium nitride layer, and the second device material layer is an aluminum gallium nitride layer.

16. The epitaxial structure according to any one of claims 9 to 15, characterized in that, The material of the first high-resistance semiconductor layer is carbon-doped and / or iron-doped gallium nitride.

17. A method for manufacturing a semiconductor device, characterized in that, The method includes the steps in the preparation method of the epitaxial structure according to any one of claims 1 to 8, or includes fabricating a semiconductor device using the epitaxial structure according to any one of claims 9 to 15.

18. A semiconductor device, characterized in that, Including the epitaxial structure according to any one of claims 9 to 15, or fabricated using the epitaxial structure according to any one of claims 9 to 15.

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