A layout of a driving circuit, a semiconductor structure and a semiconductor memory

Abstract

The embodiment of the application provides a kind of drive circuit layout, semiconductor structure and semiconductor memory, the layout includes: P-type transistor, N-type transistor and four test modules;Wherein, the four test modules are distributed in the two sides of the P-type transistor and the N-type transistor and present up-down symmetry structure, the P-type transistor and the N-type transistor are in the middle of the four test modules and present up-down structure distribution.This not only can improve the matching and consistency of signal, reduce the influence of external factors;While overall layout presents symmetry structure, and arrangement is compact, can also achieve the purpose of saving area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a layout of a driving circuit, a semiconductor structure and a semiconductor memory. BACKGROUND

[0002] With the continuous development of semiconductor technology, integrated circuits have entered the era of system on chip (SOC), and the design of layout is becoming more and more important with the continuous reduction of process size.

[0003] In dynamic random access memory (DRAM), the layout design of the power driving circuit is not only large in area, but also reduces the matching and consistency of signals due to the incomplete consideration of factors in layout and wiring. SUMMARY

[0004] The present application provides a layout of a driving circuit, a semiconductor structure and a semiconductor memory, which can improve the matching and consistency of signals, reduce the influence of external factors, and achieve the purpose of saving area with the overall layout being symmetrical and compact.

[0005] The technical solution of the present application is as follows:

[0006] In a first aspect, the present application provides a layout of a driving circuit, which can include a P-type transistor, an N-type transistor and four test modules; wherein the four test modules are distributed on both sides of the P-type transistor and the N-type transistor and have an up-down symmetrical structure, and the P-type transistor and the N-type transistor are distributed in an up-down structure in the middle of the four test modules.

[0007] In a second aspect, the present application provides a semiconductor structure, which includes two storage banks (Bank) and two power generators, the two storage banks are arranged along a second direction, and one power generator is distributed on both sides of the two storage banks along a first direction.

[0008] The power generator is composed of N driving circuits corresponding to the layout of the first aspect and an operational amplifier circuit, and N is an integer greater than zero.

[0009] In a third aspect, the present application provides a semiconductor memory, which is characterized by including a driving circuit corresponding to the layout of the first aspect.

[0010] The embodiment of the present application provides a layout of a driving circuit, a semiconductor structure and a semiconductor memory, the layout can comprise a P-type transistor, an N-type transistor and four test modules; wherein the four test modules are distributed on two sides of the P-type transistor and the N-type transistor and present an up-down symmetric structure, and the P-type transistor and the N-type transistor present an up-down structure and are distributed in the middle of the four test modules. In this way, the matching and consistency of signals can be improved, and the influence of external factors can be reduced; meanwhile, the overall layout presents a symmetric structure, is arranged compactly, and can achieve the purpose of saving area. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 It is a circuit structure schematic diagram of a power generator;

[0012] Figure 2 It is a specific circuit structure schematic diagram of a driving circuit;

[0013] Figure 3 It is a layout structure schematic diagram of a driving circuit;

[0014] Figure 4 It is a layout structure schematic diagram of a driving circuit provided by the embodiment of the present application;

[0015] Figure 5 It is a layout structure partial enlarged schematic diagram of a test module provided by the embodiment of the present application;

[0016] Figure 6 It is a signal layer schematic diagram of a layout connection provided by the embodiment of the present application;

[0017] Figure 7 It is a component schematic diagram of a semiconductor structure provided by the embodiment of the present application;

[0018] Figure 8 It is a layout schematic diagram of a semiconductor structure provided by the embodiment of the present application;

[0019] Figure 9 It is an application schematic diagram of a connection hole position in a feedback circuit provided by the embodiment of the present application;

[0020] Figure 10 It is another application schematic diagram of a connection hole position in a feedback circuit provided by the embodiment of the present application;

[0021] Figure 11 It is a component structure schematic diagram of a semiconductor memory provided by the embodiment of the present application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the application are shown in the drawings.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application.

[0024] In the following description, reference is made to the "some embodiments", which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0025] It should be noted that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0026] Referring to Figure 1 , a circuit structure schematic diagram of a power generator is shown. As Figure 1 shown, the circuit structure can include a power supply VDD, a first operational amplifier U1, a second operational amplifier U2, a first transistor P1 and a second transistor N1. Among them, the power supply VDD is connected with the source of the first transistor P1, the output end of the first operational amplifier U1 is connected with the gate of the first transistor P1, the output end of the second operational amplifier U2 is connected with the gate of the second transistor N1, the source of the second transistor N1 is connected with the ground, and the drain of the second transistor N1 is connected with the drain of the first transistor P1 and then connected with the output end, which is used to provide an output voltage signal (represented by VARY); the first resistor R1 and the second resistor R2 are connected in series between the output end and the ground, and the first resistor R1 and the second resistor R2 are connected to form a first connection point, the positive input end of the first operational amplifier U1 and the positive input end of the second operational amplifier U2 are connected to form a second connection point, and the first connection point and the second connection point are connected, which is used to obtain a feedback signal (represented by VARY_FB).

[0027] It should be noted that the first resistor R1 and the second resistor R2 form a voltage divider circuit, so R1 and R2 can also be referred to as "voltage divider resistors". The first transistor P1 and the second transistor N1 can be a metal-oxide-semiconductor field-effect transistor (MOSFET), abbreviated as "MOS tube". Specifically, in Figure 1 , the first transistor P1 is a P-type MOS tube, and the second transistor N1 is an N-type MOS tube. In addition, the operational amplifier is an abbreviation of "operational amplifier", and in the embodiments of the present application, the operational amplifier herein is a differential amplifier.

[0028] It should also be noted that the power generator can also be referred to as a power generation circuit. By Figure 1 It can be seen that the core architecture is "MOS tube + operational amplifier", which adjusts the gate voltage of the MOS tube through the operational amplifier and the voltage divider resistors (R1 and R2), so that a stable VARY voltage can be output. Here, the first operational amplifier U1 and the second operational amplifier U2 form an operational amplifier circuit (denoted by VARY ACT), and the first transistor P1 and the second transistor N1 form a driving circuit (denoted by VARY DRIVER).

[0029] For the driving circuit, see Figure 2 , which shows a specific circuit structure diagram of a driving circuit. As Figure 2 shown, the circuit structure can include a power supply VDD, a first P-type transistor P1, a second P-type transistor P2, a third P-type transistor P3, a first N-type transistor N1, a second N-type transistor N2, a third N-type transistor N3, a first test module (TestMode1), a second test module (Test Mode2), a third test module (Test Mode3), and a fourth test module (TestMode4).

[0030] The source of the first P-type transistor P1, the source of the second P-type transistor P2, and the source of the third P-type transistor P3 are all connected with the power supply VDD, and the source of the first N-type transistor N1, the source of the second N-type transistor N2, and the source of the third N-type transistor N3 are all connected with the ground VSS. In addition, the gate of the first P-type transistor P1 is connected with the first driving signal, the gate of the second P-type transistor P2 is connected with the first test module, the gate of the third P-type transistor P3 is connected with the second test module, the gate of the first N-type transistor N1 is connected with the second driving signal, the gate of the second N-type transistor N2 is connected with the third test module, the gate of the third N-type transistor N3 is connected with the fourth test module, and the drain of the first P-type transistor P1, the drain of the second P-type transistor P2, the drain of the third P-type transistor P3, the drain of the first N-type transistor N1, the drain of the second N-type transistor N2, and the drain of the third N-type transistor N3 are all connected with the output end for providing an output voltage signal. The first driving signal can be a pull up (PU) signal, the second driving signal can be a pull down (PD) signal, and the output voltage signal is represented by VARY.

[0031] For Figure 2 , the main purpose is to adjust VARY through P-type transistors and N-type transistors. Therefore, Figure 2 the important part in the present application is the transistors P1, P2, P3, N1, N2, and N3. In addition, the four test modules (including the first test module, the second test module, the third test module, and the fourth test module) are used to select whether to turn on P2, P3, N2, and N3 according to requirements.

[0032] Based on the driving circuit shown in Figure 2 , Figure 3 a layout structure schematic diagram of a driving circuit is shown. As shown in Figure 3 , in the layout, the first test module, the second test module, the transistor, the third test module, and the fourth test module are arranged in sequence along the horizontal direction, that is, the four test modules are distributed on both sides of the transistor; and the three P-type transistors P1, P2, and P3 and the three N-type transistors N1, N2, and N3 are arranged in an upper-lower asymmetric structure, and the edge of the N-type substrate surrounds the upper half of the P-type MOS transistor (referred to as "PMOS transistor"), and the edge of the P-type substrate surrounds the lower half of the N-type MOS transistor (referred to as "NMOS transistor"). However, for the layout of Figure 3 , due to the fact that the layout and wiring are not considered comprehensively at present, not only the area is large, but also the matching and consistency of the signal are reduced.

[0033] Based on this, the embodiment of the present application provides a layout of a driving circuit, which can include a P-type transistor, an N-type transistor and four test modules; wherein the four test modules are distributed on both sides of the P-type transistor and the N-type transistor and present an up-down symmetric structure, and the P-type transistor and the N-type transistor present an up-down structure and are distributed in the middle of the four test modules. In this way, not only the matching and consistency of the signal can be improved, and the influence of external factors can be reduced, but also the overall layout presents a symmetric structure, and the arrangement is compact, and the purpose of saving area can also be achieved.

[0034] The embodiments of the present application will be described in detail below with reference to the drawings.

[0035] In an embodiment of the present application, referring to Figure 4 , a layout structure diagram of a driving circuit provided by the embodiment of the present application is shown. As Figure 4 indicated, the layout can include a P-type transistor, an N-type transistor and four test modules; wherein the four test modules are distributed on both sides of the P-type transistor and the N-type transistor and present an up-down symmetric structure, and the P-type transistor and the N-type transistor present an up-down structure and are distributed in the middle of the four test modules.

[0036] It should be noted that Figure 4 is a layout provided for the driving circuit shown in Figure 2 , and can also be referred to as a "layout structure". Specifically, Figure 4 , the layout as a whole presents a symmetric structure. Among them, the four test modules distributed on both sides of the P-type transistor and the N-type transistor present an up-down symmetric structure and a left-right symmetric structure, and the P-type transistor and the N-type transistor in the middle present an up-down symmetric structure.

[0037] It should also be noted that in the embodiment of the present application, the four test modules can include a first test module, a second test module, a third test module and a fourth test module. Specifically, for the four test modules, in some embodiments, as Figure 4 indicated, the first test module and the second test module are distributed on both sides of the P-type transistor and present a left-right symmetric structure, and the third test module and the fourth test module are distributed on both sides of the N-type transistor and present a left-right symmetric structure.

[0038] It should also be noted that in the embodiment of the present application, the P-type transistor includes a first P-type transistor, a second P-type transistor and a third P-type transistor, and the N-type transistor includes a first N-type transistor, a second N-type transistor and a third N-type transistor. Among them, as Figure 4 indicated, the first P-type transistor is represented by P1, the second P-type transistor is represented by P2, the third P-type transistor is represented by P3, the first N-type transistor is represented by N1, the second N-type transistor is represented by N2, and the third N-type transistor is represented by N3.

[0039] For these transistors, the gate of the first P-type transistor is connected with the first driving signal, the gate of the second P-type transistor is connected with the first test module, and the gate of the third P-type transistor is connected with the second test module; the gate of the first N-type transistor is connected with the second driving signal, the gate of the second N-type transistor is connected with the third test module, and the gate of the third N-type transistor is connected with the fourth test module.

[0040] In the embodiments of the present application, in combination with Figure 2 Since these transistors are mainly used for adjusting the output voltage signal (VARY), the transistors P1, P2, P3, N1, N2 and N3 can also be called adjusting tubes. It should be noted that these transistors can be MOS tubes, or even can be silicon-controlled, etc. Preferably, P1, P2, P3, N1, N2 and N3 in the embodiments of the present application are MOS tubes, wherein P1, P2 and P3 are P-type MOS tubes, and N1, N2 and N3 are N-type MOS tubes.

[0041] Further, in order to facilitate wiring, in some embodiments, the first P-type transistor is located between the second P-type transistor and the third P-type transistor, so that the second P-type transistor is close to the first test module, and the third P-type transistor is close to the second test module.

[0042] The first N-type transistor is located between the second N-type transistor and the third N-type transistor, so that the second N-type transistor is close to the third test module, and the third N-type transistor is close to the fourth test module.

[0043] That is, the P-type transistors and the N-type transistors are located between the four test modules, and P1 is located between P2 and P3, and N1 is located between N2 and N3, so that P2, P3, N2 and N3 are close to the test modules, facilitating connection. Specifically, as shown in Figure 4 P2 is close to the first test module, P3 is close to the second test module, N2 is close to the third test module, and N3 is close to the fourth test module.

[0044] In some embodiments, for each test module, referring to Figure 5 , the test module can include P-type MOS tubes and N-type MOS tubes; wherein the N-type MOS tubes are distributed in the middle part of the test module, and the P-type MOS tubes are distributed on both sides of the N-type MOS tubes along a first direction.

[0045] It should be noted that the P-type MOS tube can be referred to as "PMOS tube" for short, and the N-type MOS tube can be referred to as "NMOS tube" for short.

[0046] It should be further noted that the first direction is a vertical direction. In this way,Figure 5 As shown in the vertical direction, the test module can be regarded as being composed of PMOS-NMOS-PMOS, and the distribution is mainly considered for the overall structure and connection of the layout and the purpose of saving area.

[0047] Further, in some embodiments, referring to Figure 5 , the test module can further include a P-type substrate and an N-type substrate; wherein the edge of the P-type substrate surrounds the N-type MOS tube, and the edge of the N-type substrate surrounds the P-type MOS tube, so as to reduce the influence between the N-type MOS tube and the P-type MOS tube.

[0048] That is, in each test module, the edge of the P-type substrate surrounds the NMOS tube, and the edge of the N-type substrate surrounds the PMOS tube; thereby compared with the layout of Figure 3 , the P-type substrate and the N-type substrate are added in the embodiments of the present application, so that the influence between the tubes is reduced, and the environment is cleaner.

[0049] Further, for P1, P2, P3, N1, N2, N3, in some embodiments, the first P-type transistor, the second P-type transistor, the third P-type transistor, the first N-type transistor, the second N-type transistor and the third N-type transistor are all in a finger structure; wherein the finger number in the finger structure is determined according to the overall structure and connection of the layout.

[0050] It should be noted that finger refers to a single MOS tube in a finger shape. The reason for making the MOS tube into a finger structure is: on the one hand, based on the layout of the layout, the width-length ratio of the transistor in the analog circuit design can be large, and thus it needs to be made into a finger structure; on the other hand, based on the case that the width-length ratio of the transistor is large, the gate parasitic resistance can be reduced through the finger structure; on the other hand, based on the consideration under high frequency, the noise of the gate resistance can also be reduced.

[0051] It should be further noted that, in the embodiments of the present application, as shown in Figure 4 , the height of P1, P2, P3 corresponds to the height of the first test module or the second test module, and the height of N1, N2, N3 corresponds to the height of the third test module or the fourth test module, and no matter the first test module, the second test module, the third test module or the fourth test module, the inside of each of them includes PMOS-NMOS-PMOS; thereby the number of fingers of P1, P2, P3, N1, N2, N3 can be adjusted to adapt to the height of the test module. Here, in order to make the layout more symmetrical, the number of fingers can usually be even.

[0052] That is, in the embodiments of the present application, for P1, P2, P3, N1, N2, N3, the total width of each transistor = single finger width x finger number; in this way, the finger number of P1, P2, P3, N1, N2, N3 can be adjusted to be suitable for the layout and wiring of the overall structure.

[0053] It can be understood that in the embodiments of the present application, the layout can be divided into a layout layer and a signal layer, and the signal layer is located above the layout layer; wherein the first P-type transistor, the second P-type transistor, the third P-type transistor, the first N-type transistor, the second N-type transistor, the third N-type transistor and the four test modules are located in the layout layer.

[0054] That is, Figure 4 It can be seen that the layout layer is Figure 5 a local enlarged schematic view of the test module in the layout layer. As Figure 5 shown, the part filled with dense points is a via, the part filled with grid lines is a polysilicon gate (Poly Gate), and the part filled with sparse points is a Metal 0 layer (Metal 0).

[0055] From Figure 4 and Figure 5 , it can be seen that for each transistor (such as P1, P2, P3, N1, N2, N3, PMOS tube, NMOS tube, etc.), it can include a via, a polysilicon gate and a Metal 0 layer, the via penetrates the Metal 0 layer, and the drain between the P-type transistor and the N-type transistor is also connected through the Metal 0 layer.

[0056] Further, referring to Figure 6 , a signal layer schematic diagram of a layout wiring is shown. As Figure 6 shown, the signal layer can include the first drive signal, the second drive signal and the output voltage signal; wherein the first drive signal and the second drive signal are matched and distributed in an up-down structure, and the two sides of the first drive signal and the second drive signal are distributed as output voltage signals.

[0057] In some embodiments, referring to Figure 6 , the signal layer can further include a first test input signal, a second test input signal, a third test input signal and a fourth test input signal; wherein the first test input signal, the second test input signal, the third test input signal and the fourth test input signal are uniformly distributed and have an up-down symmetric and left-right symmetric structure.

[0058] It should be noted that in the embodiments of the present application, the first drive signal can be represented by PU, the second drive signal can be represented by PD, the output voltage signal can be represented by VARY, the first test input signal is represented by TM_VARY_PU<0>, the second test input signal is represented by TM_VARY_PU<1>, the third test input signal is represented by TM_VARY_PD<0>, and the fourth test input signal is represented by TM_VARY_PD<1>.

[0059] It should also be noted that in the embodiments of the present application, the first test input signal is distributed above the first test module, the second test input signal is distributed above the second test module, the third test input signal is distributed above the third test module, and the fourth test input signal is distributed above the fourth test module.

[0060] That is, Figure 6 The layout example of the horizontal first metal layer (Metal 1) is mainly shown. Among them, the input signals TM_VARY_PU<0>, TM_VARY_PU<1>, TM_VARY_PD<0> and TM_VARY_PD<1> of the test module are uniformly distributed, which are symmetrical in up-down and left-right; and each input signal is located above the corresponding test module, such as TM_VARY_PU<0> above the first test module, TM_VARY_PU<1> above the second test module, TM_VARY_PD<0> above the third test module, and TM_VARY_PD<1> above the fourth test module. In addition, the PU and PD signals are matched and distributed in an up-down structure, and the signal lines distributed on both sides are power signals (i.e. output voltage signal VARY), which reduces the influence of external factors on the signal.

[0061] In addition, still taking the drive circuit of Figure 2 as an example, for the supply voltage signal, the supply voltage signal is connected with the source of the first P-type transistor, the source of the second P-type transistor and the source of the third P-type transistor; the output voltage signal is connected with the drain of the first P-type transistor, the drain of the second P-type transistor and the drain of the third P-type transistor, and the drain of the first N-type transistor, the drain of the second N-type transistor and the drain of the third N-type transistor. For the ground signal, the ground signal is connected with the source of the first N-type transistor, the source of the second N-type transistor and the source of the third N-type transistor.

[0062] Further, in some embodiments, referring to Figure 6 , the signal layer can further include a supply voltage signal and a ground signal; wherein,

[0063] The first driving signal, the output voltage signal, the first test input signal and the second test input signal, the ground signal and the power supply voltage signal are arranged in the vertical upward direction in turn with the power supply voltage signal as a reference, and the second driving signal, the output voltage signal, the third test input signal and the fourth test input signal, the ground signal and the power supply voltage signal are arranged in the vertical downward direction in turn.

[0064] It should be noted that, in the embodiment of the present application, the power supply voltage signal is represented by VDD, and the ground signal is represented by VSS. That is, PU, VARY, TM_VARY_PU<0> and TM_VARY_PU<1>, VSS and VDD are arranged in the vertical upward direction in turn with VDD as a reference, and PD, VARY, TM_VARY_PD<0> and TM_VARY_PD<1>, VSS and VDD are arranged in the vertical downward direction in turn; wherein TM_VARY_PU<0> and TM_VARY_PU<1> are arranged in the horizontal direction and correspond to the upper side of the first test module and the second test module; TM_VARY_PD<0> and TM_VARY_PD<1> are arranged in the horizontal direction and correspond to the upper side of the third test module and the fourth test module; so that the signal distribution of the signal layer is uniform, the power supply capacity is sufficient, and the overall structure is beautiful.

[0065] It should also be noted that, in the embodiment of the present application, Metal 0 and Metal 1 are adjacent metal layers and can be connected by a via. Figure 6 The four signal lines not marked in the figure are internal connections, i.e. the connections between P2 and the first test module, P3 and the second test module, N2 and the third test module, and N3 and the fourth test module.

[0066] In this way, in the layout of the embodiment of the present application, as shown in the layout layer of Figure 4 , the four test modules are located at the four corners and have a symmetrical structure; the P-type transistors (P1, P2, P3) and the N-type transistors (N1, N2, N3) are located in the middle of the four test modules, and P1 is located in the middle of P2 and P3, and N1 is located in the middle of N2 and N3, so that P2, P3, N2 and N3 are close to the corresponding test modules, facilitating the connection; and the overall layout of the layout layer has a symmetrical structure. As shown in the signal layer of Figure 6 , the signal layer is located above the layout layer; wherein the input signals TM_VARY_PU<0:1> and TM_VARY_PD<0:1> of the test modules are uniformly distributed and have a symmetrical structure; in addition, the PU and PD signals are matched and have an up-down structure, and the signal lines on both sides are power supply signals, reducing the influence of external factors on the signals; and the power supply signals are uniformly distributed, the power supply is sufficient, and the overall structure is beautiful.

[0067] In conclusion, it can be seen that... Figure 3 and Figure 4 In comparison, for Figure 4 Regarding the layout, on the one hand, the overall structure has changed, facilitating internal wiring; on the other hand, the internal structure of the test module has changed, and its position has also changed, with each module distributed next to the MOS transistors with which it is connected, making wiring convenient and neat; furthermore, by changing the finger count of P1, P2, P3 and N1, N2, N3, it is made suitable for the overall structural layout and wiring; most importantly, the first P-type transistor P1 and the first N-type transistor N1, which are connected to the PD and PU signals, are placed between P2 and P3, and N2 and N3, respectively, making the PD and PU signal lines more matched; furthermore, the overall layout structure of this embodiment is compact, saving more area, and by appropriately increasing the P and N substrates, the influence between the transistors is reduced, resulting in a cleaner environment; moreover, the new layout layout also makes the distribution of the upper signal layer more symmetrical and aesthetically pleasing, the matching degree of the signal lines higher, and the power supply distribution more sufficient.

[0068] This embodiment provides a layout for a driving circuit, which may include P-type transistors, N-type transistors, and four test modules. The four test modules are distributed on both sides of the P-type and N-type transistors in a symmetrical top-to-bottom structure, while the P-type and N-type transistors are distributed vertically in the middle of the four test modules. This not only improves signal matching and consistency and reduces the influence of external factors, but also achieves a symmetrical and compact layout, thus saving area.

[0069] In another embodiment of this application, see Figure 7 This illustrates a schematic diagram of the composition of a semiconductor structure provided in an embodiment of this application. For example... Figure 7 As shown, the semiconductor structure 70 may include two banks and two power generators, the two banks being arranged along a second direction, and a power generator being distributed on each side of the two banks along a first direction.

[0070] The power generator consists of N driving circuits corresponding to the layout described in any of the foregoing embodiments and an operational amplifier circuit, where N is an integer greater than zero.

[0071] Furthermore, in some embodiments, for the power generator, the operational amplifier circuit is located in the middle of the N drive circuits.

[0072] It should be noted that the first direction can be horizontal, and the second direction can be vertical. For example... Figure 7 As shown, two storage units are arranged horizontally, and two power generators are distributed vertically on both sides of the two storage units.

[0073] It should also be noted that in the embodiments of this application, the value of N can be 8. That is, each power generator can consist of 8 driver circuits and one operational amplifier circuit.

[0074] In one possible implementation, see Figure 8 This illustrates a schematic layout of a semiconductor structure 70 provided in an embodiment of this application. Figure 8 As shown in the diagram, two storage repositories are arranged horizontally, and two power generators are distributed vertically on both sides of the two storage repositories. Each power generator can include eight driver circuits and one operational amplifier circuit. In each power generator, the operational amplifier circuit is located in the middle of the eight driver circuits.

[0075] Furthermore, in some embodiments, such as Figure 8 As shown, in the layout corresponding to this semiconductor structure, the output voltage signals generated by each driving circuit on both sides are interconnected and evenly distributed in the two storage bins.

[0076] Furthermore, in some embodiments, such as Figure 8 As shown, in the layout corresponding to this semiconductor structure, the output feedback signals received by the operational amplifier circuits distributed on both sides are connected, and the output feedback signal is connected to the output voltage signal through a connection hole at the middle position of the two storage banks to form the feedback circuit of the semiconductor structure.

[0077] It should be noted that the output voltage signal generated by each driver circuit (VARY DRIVER) is... Figure 8 In this context, VARY represents the output voltage signals generated by all the drive circuits in these two power generators, and these signals are interconnected and evenly distributed. Furthermore, each operational amplifier circuit (VARY ACT) receives an output feedback signal in... Figure 8 In the diagram, VARY_FB is used to represent the two operational amplifier circuits. The output feedback signals received by each of these two operational amplifier circuits are interconnected, and the output feedback signal is connected to the output voltage signal at the midpoint between the two storage banks through a connection hole marked C to form the feedback circuit of the semiconductor structure 70.

[0078] It should also be noted that, in Figure 8 In the diagram, the connection hole used to connect the output feedback signal (VARY_FB) and the output voltage signal (VARY) is positioned either as indicated by B or C. This will be discussed in the following section. Figure 9 and Figure 10 Provide a detailed description.

[0079] in, Figure 9An application diagram of the connection hole position in the feedback circuit is shown, Figure 10 An application diagram of the connection hole position in another feedback circuit is shown. Here, the input signal is represented by VARYR, and the output feedback signal is represented by VARY_FB. After passing through the operational amplifier, the two signals will also flow through the VARY power supply network, which supplies power to the sense amplifier (SA). In addition, Figure 9 Point B in Figure 8 corresponds to the B marked position, Figure 10 Point C in Figure 8 corresponds to the C marked position. It should also be noted that Figure 9 and Figure 10 operational amplifiers are not actual operational amplifiers, but represent the overall circuit (i.e., the power generator) of the operational amplifier and the driver; and the voltage dividing resistor is omitted here, and the output voltage VARY is directly connected as the feedback circuit VARY_FB.

[0080] In the embodiments of the present application, Figure 9 and Figure 10 are mainly used to illustrate that when the connection hole position of VARY_FB in the layout is different, the resulting output voltage (V_E) is also different. Figure 9 When the connection hole is at the B marked position, the resulting output voltage V_E = VARYR - I x R_par. Since the distance from point B to point E is very far, I is used to represent the current flowing through this distance, and R_par represents the parasitic resistance contained in this distance. Figure 10 When the connection hole is at the C marked position, the resulting output voltage V_E = VARYR. Since the distance from point C to point E is very short, the parasitic resistance generated by this distance is almost negligible. As can be seen, compared with Figure 9 and Figure 10 , it is concluded that Figure 10 the V_E obtained is more stable; therefore, the C marked position is a better choice for the connection hole position. In addition, here, V_E represents the voltage at point E, which is the center point voltage of the entire VARY power supply network.

[0081] It should also be noted that in the layout corresponding to the semiconductor structure, Figure 8For example, one power generator is distributed above and below the two memory banks, and one power generator is composed of 8 driving circuits (VARY DRIVER) and one operational amplifier circuit (VARY ACT). In addition, the VARY voltage generated by each VARY DRIVER is connected by metal wires (Metal), ensuring that the power network of VARY is strong enough, while being evenly distributed in the memory bank. VARY ACT is located in the middle of the 8 VARY DRIVER, in addition, the generated VARY_FB is connected, and in the middle position of the two memory banks, it is connected with the VARY voltage through a contact hole (Contact), forming the feedback circuit of VARY.

[0082] The embodiment provides a semiconductor structure, which comprises two memory banks and two power generators, the two memory banks are arranged along a second direction, and one of the power generators is distributed on each side of the two memory banks along a first direction; wherein the power generator is composed of N driving circuits corresponding to the layout and one operational amplifier circuit, N is an integer greater than zero. In this way, since the layout of the driving circuit in it, the four test modules are distributed on both sides of the P-type transistor and the N-type transistor and are in a symmetrical structure, and the P-type transistor and the N-type transistor are in a symmetrical structure and are distributed in the middle of the four test modules; thereby not only improving the matching and consistency of PU and PD signals, reducing the influence of external factors; at the same time, the overall layout is in a symmetrical structure, and the arrangement is compact, and the purpose of saving area can also be achieved.

[0083] In another embodiment of the present application, referring to Figure 11 , which shows a schematic diagram of a semiconductor memory structure provided by the embodiment of the present application. As Figure 11 shown, the semiconductor memory 110 can comprise the driving circuit corresponding to the layout as described in any one of the preceding embodiments.

[0084] In the embodiment of the present application, the semiconductor memory 110 can be a DRAM chip.

[0085] It should be noted that in order to optimize the VARY driving performance, according to the requirements, the embodiment of the present application provides a layout design of VARY driving applied to a DRAM chip, that is, the layout of the driving circuit described in the preceding embodiments.

[0086] It should be noted that, for the semiconductor memory 110, in the layout of the internal drive circuit, the four test modules are distributed on both sides of the P-type transistor and the N-type transistor in a symmetrical structure, and the P-type transistor and the N-type transistor are distributed in a symmetrical structure in the middle of the four test modules. In this way, not only can the matching and consistency of the PU and PD signals be improved, and the influence of external factors can be reduced, but also the overall layout is symmetrical and compact, and the purpose of saving area can be achieved.

[0087] The above merely provides the preferred embodiments of the present application, but does not limit the protection scope of the present application.

[0088] It should be noted that, in the present application, the terms "comprising", "containing" or any other variants thereof are intended to cover the non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes the elements inherent to such process, method, article or device. Without more limitations, the element defined by the sentence "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0089] The above-mentioned sequence numbers of the embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0090] The methods disclosed in the several method embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments.

[0091] The features disclosed in the several product embodiments provided by the present application can be combined arbitrarily without conflict to obtain new product embodiments.

[0092] The features disclosed in the several method or device embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method or device embodiments.

[0093] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A layout of a drive circuit, characterized by, The layout comprises a P-type transistor, an N-type transistor and four test modules; wherein the four test modules are distributed on both sides of the P-type transistor and the N-type transistor and have an up-down symmetric structure, and the P-type transistor and the N-type transistor are distributed in an up-down structure in the middle of the four test modules.

2. The layout of claim 1, wherein, The four test modules comprise a first test module, a second test module, a third test module and a fourth test module; wherein, The first test module and the second test module are distributed on both sides of the P-type transistor and have a symmetric structure, and the third test module and the fourth test module are distributed on both sides of the N-type transistor and have a symmetric structure.

3. The layout of claim 2, wherein, The P-type transistor comprises a first P-type transistor, a second P-type transistor and a third P-type transistor, and the N-type transistor comprises a first N-type transistor, a second N-type transistor and a third N-type transistor; wherein, The gate of the first P-type transistor is connected with a first driving signal, the gate of the second P-type transistor is connected with the first test module, and the gate of the third P-type transistor is connected with the second test module; The gate of the first N-type transistor is connected with a second driving signal, the gate of the second N-type transistor is connected with the third test module, and the gate of the third N-type transistor is connected with the fourth test module.

4. The layout according to claim 3, wherein, The first P-type transistor is located in the middle of the second P-type transistor and the third P-type transistor, so that the second P-type transistor is close to the first test module and the third P-type transistor is close to the second test module; The first N-type transistor is located in the middle of the second N-type transistor and the third N-type transistor, so that the second N-type transistor is close to the third test module and the third N-type transistor is close to the fourth test module.

5. The layout of claim 3, wherein, The first P-type transistor, the second P-type transistor, the third P-type transistor, the first N-type transistor, the second N-type transistor and the third N-type transistor are all in a finger structure; The number of fingers in the finger structure is determined according to the overall structure and the distribution of the wires of the layout.

6. The layout of claim 1, wherein, The test module comprises a P-type MOS tube and an N-type MOS tube; wherein the N-type MOS tube is distributed in the middle part of the test module, and the P-type MOS tube is distributed on both sides of the N-type MOS tube along a first direction.

7. The layout of claim 6, wherein, The test module further comprises a P-type substrate and an N-type substrate; wherein the edge of the P-type substrate surrounds the N-type MOS tube, and the edge of the N-type substrate surrounds the P-type MOS tube.

8. The layout of claim 3, wherein, The layout is divided into a layout layer and a signal layer, and the signal layer is located above the layout layer; The first P-type transistor, the second P-type transistor, the third P-type transistor, the first N-type transistor, the second N-type transistor, the third N-type transistor and the four test modules are all located in the layout layer.

9. The layout of claim 8, wherein, The signal layer comprises the first driving signal, the second driving signal and an output voltage signal; The first driving signal and the second driving signal are matched and arranged in an up-down structure, and the first driving signal and the second driving signal are arranged on both sides of the output voltage signal.

10. The layout of claim 9, wherein, The signal layer further comprises a first test input signal, a second test input signal, a third test input signal and a fourth test input signal. The first test input signal, the second test input signal, the third test input signal and the fourth test input signal are uniformly arranged and arranged in an up-down symmetric and left-right symmetric structure.

11. The layout according to claim 10, wherein, The first test input signal is arranged above the first test module, the second test input signal is arranged above the second test module, the third test input signal is arranged above the third test module, and the fourth test input signal is arranged above the fourth test module.

12. The layout of claim 11, wherein, The signal layer further comprises a power supply voltage signal and a ground signal. The first driving signal, the output voltage signal, the first test input signal and the second test input signal, the ground signal and the power supply voltage signal are arranged in a vertical upward direction in sequence, and the second driving signal, the output voltage signal, the third test input signal and the fourth test input signal, the ground signal and the power supply voltage signal are arranged in a vertical downward direction in sequence.

13. The layout according to claim 12, wherein, The power supply voltage signal is connected to the source of the first P-type transistor, the source of the second P-type transistor and the source of the third P-type transistor. The output voltage signal is connected to the drain of the first P-type transistor, the drain of the second P-type transistor and the drain of the third P-type transistor, and the drain of the first N-type transistor, the drain of the second N-type transistor and the drain of the third N-type transistor. The ground signal is connected to the source of the first N-type transistor, the source of the second N-type transistor and the source of the third N-type transistor.

14. A semiconductor structure, characterized by The semiconductor structure comprises two storage banks and two power generators, the two storage banks are arranged along a second direction, and one of the power generators is arranged on each side of the two storage banks along a first direction; The power generator is composed of N driving circuits corresponding to the layout according to any one of claims 1 to 13 and an operational amplifier circuit, N is an integer greater than zero.

15. The semiconductor structure of claim 14, wherein, In the power generator, the operational amplifier circuit is located at the middle position of the N driving circuits.

16. The semiconductor structure of claim 14 or 15, wherein, N is 8.

17. The semiconductor structure of claim 14, wherein, In the layout corresponding to the semiconductor structure, the output voltage signals generated by each of the driving circuits arranged on both sides are connected to each other and uniformly distributed in the two storage banks.

18. The semiconductor structure of claim 17, wherein, In the layout corresponding to the semiconductor structure, the output feedback signals received by the two op-amp circuits on both sides are connected, and the output feedback signals are connected to the output voltage signal through a connection hole at the middle position of the two storage banks, to form a feedback circuit of the semiconductor structure.

19. A semiconductor memory, characterized by comprising: The driving circuit corresponding to the layout as claimed in any one of claims 1 to 13.

20. The semiconductor memory of claim 19, wherein, The semiconductor memory is a dynamic random access memory (DRAM) chip.

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