A bidirectional low-capacitance NPN device for ESD protection

Abstract

The present invention provides a bidirectional low-capacitance NPN device for ESD protection, comprising: an n+-type substrate, an n-type buried layer, a first p-type buried layer, a second p-type buried layer, a first n-type epitaxial layer, a second n-type epitaxial layer, a third n-type epitaxial layer, a fourth n-type epitaxial layer, a fifth n-type epitaxial layer, a p-type well region, a Zener-implanted p-type well region, a tungsten plug region, a first N+ contact region, a second N+ contact region, a third N+ contact region, a P+ region, a first isolation region, a second isolation region, a third isolation region, a fourth isolation region, and a fifth isolation region; by introducing the tungsten plug region, the p-type buried layer, and a diode with a vertical structure, the present invention realizes the bidirectional low-capacitance characteristics of the device, perfectly combines the advantages of high current efficiency of the vertical device and high integration of the lateral device, and can realize various single-chip protection structures such as bidirectional, unidirectional, and array.

Description

Technical Field

[0001] The present invention belongs to the field of electronic science and technology, and is mainly used for ElectroStatic Discharge (ESD) protection technology. Further, it is a method for optimizing the parasitic capacitance of an NPN structure and related device structures by increasing a series of vertical diode structures to reduce the parasitic capacitance. Background Art

[0002] ESD, namely ElectroStatic Discharge, is an ancient natural phenomenon. ESD exists in every corner of people's daily life. However, such a common electrical phenomenon is a fatal threat to precision integrated circuits.

[0003] With the improvement of integrated circuit manufacturing technology, its minimum line width has dropped to the sub-micron or even nano level. While bringing about an improvement in chip performance, its ability to withstand ESD strikes has been greatly reduced, so electrostatic damage is more serious. Most ESD events can cause non-fatal damage to integrated circuits, thereby reducing the lifespan and reliability of integrated circuits, and further causing the degradation of system functions, which poses a great obstacle to the realization of large-scale highly reliable integration.

[0004] Nowadays, a type of data transmission interface is also included in the interfaces of electronic devices. For such interfaces, in addition to the ESD protection devices used needing to provide basic ESD protection functions, the device also needs to be in a "completely invisible" state when the system is operating normally, that is, when transmitting data, which means it cannot interfere with the integrity of the data transmission signal. This poses strict requirements on the parasitic capacitance of the ESD protection devices used. Therefore, today, with the increasing data transmission speed, how to enable ESD protection devices to reduce the capacitance as much as possible while ensuring sufficient ESD protection capabilities to maintain the signal integrity of high-speed data interfaces has become a new and severe challenge. Although traditional vertical devices can provide good over-current capabilities per unit capacitance, it is difficult to integrate them into multi-port arrays, while lateral devices are conducive to integration, but their over-current capabilities per unit capacitance are much lower. Therefore, if a vertical guiding diode with low capacitance and high current is integrated with a lateral TVS discharge tube with good symmetry, the device performance and integration degree will be greatly improved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to reduce the parasitic capacitance of a device by increasing a series of vertical diode structures without significantly increasing the device area.

[0006] To achieve the above invention object, the technical solution of the present invention is as follows:

[0007] A bidirectional low-capacitance NPN device for ESD protection, comprising: an n+-type substrate 01, an n-type epitaxial layer epitaxially grown on the n+-type substrate 01 is divided into five parts by five isolation regions and a tungsten plug region 05 of the same depth. The five isolation regions and a tungsten plug region 05 all penetrate the n-type epitaxial layer from the device surface and reach the inside of the n+-type substrate 01 at the bottom. The five divided parts are, from left to right in sequence: the first n-type epitaxial layer 21, the second n-type epitaxial layer 22, the third n-type epitaxial layer 23, the fourth n-type epitaxial layer 24, and the fifth n-type epitaxial layer 25; wherein the first isolation region 51 is located at the leftmost end of the device; the second isolation region 52 is located between the first n-type epitaxial layer 21 and the second n-type epitaxial layer 22; the third isolation region 53 is located between the second n-type epitaxial layer 22 and the third n-type epitaxial layer 23; the tungsten plug region 05 is located between the third n-type epitaxial layer 23 and the fourth n-type epitaxial layer 24; the fourth isolation region 54 is located between the fourth n-type epitaxial layer 24 and the fifth n-type epitaxial layer 25; the fifth isolation region 55 is located at the rightmost end of the device;

[0008] Below the first n-type epitaxial layer 21 on the n+-type substrate 01 and between the first isolation region 51 and the second isolation region 52, there is an n-type buried layer 11 injected before the epitaxial n-type epitaxial layer; below the second n-type epitaxial layer 22 on the n+-type substrate 01 and between the second isolation region 52 and the third isolation region 53, there is a first p-type buried layer 121 injected before the epitaxial n-type epitaxial layer; below the third n-type epitaxial layer 23 on the n+-type substrate 01 and between the third isolation region 53 and the tungsten plug region 05, there is a second p-type buried layer 122 injected before the epitaxial n-type epitaxial layer;

[0009] It further includes a p-type well region 03 injected above the first n-type epitaxial layer 21; a P+ region 41 injected on the surface of the p-type well region 03; a first N+ contact region 31 injected on the surface of the second n-type epitaxial layer 22;

[0010] The surfaces of the first N+ contact region 31 and the P+ region 41 are short-circuited with metal to form the first input or output port 61 of the device; in addition, the contact parts of the third isolation region 53 with the first p-type buried layer 121 and the second p-type buried layer 122 on both sides are hollowed out, and the hollowed-out part is still a p-type buried layer, so that the p-type buried layers on both sides are connected into a whole;

[0011] On the right side of the fourth isolation region 54 is an NPN structure.

[0012] As a preferred mode: the NPN structure includes: a Zener-injected p-type well region 04 injected on the surface of the fifth n-type epitaxial layer 25, and a second N+ contact region 32 and a third N+ contact region 33 injected on the surface of the Zener-injected p-type well region 04; the tungsten plug region 05 and the surface of the second N+ contact region 32 are short-circuited with metal to form a path; the third N+ contact region 33 serves as the second input or output port 62 of the device.

[0013] As a preferred embodiment: the NPN structure is replaced by a PNP structure, including an n-type well region 06 implanted on the surface of the fifth n-type epitaxial layer 25; a second P+ region 42 and a third P+ region 43 implanted on the surface of the n-type well region 06; a metal tungsten plug region 05 and the surface of the second P+ region 42 are shorted with metal to form a path; the third P+ region 43 serves as the second input or output port 62 of the device.

[0014] As a preferred embodiment: the NPN structure is replaced by an SCR structure, including: a Zener-implanted p-type well region 04 implanted on the surface of the fifth n-type epitaxial layer 25 and an n-type well region 06 tangent to the right edge of the Zener-implanted p-type well region 04, a second P+ region 42 and a second N+ contact region 32 implanted on the surface of the Zener-implanted p-type well region 04, a third P+ region 43 and a third N+ contact region 33 implanted on the surface of the n-type well region 06; a metal tungsten plug region 05 and the surfaces of the second P+ region 42 and the second N+ contact region 32 are shorted with metal to form a path; the surfaces of the third P+ region 43 and the third N+ contact region 33 are shorted with metal to form the second input or output port 62.

[0015] As a preferred embodiment: the metal type of the metal tungsten plug region 05 is replaced with other metals to form a metal plug region 07.

[0016] The beneficial effects of the present invention are as follows: the device can combine the advantages of vertical devices and horizontal devices through the tungsten plug structure to establish an ohmic contact located in the body. To sum up, the present invention proposes a bidirectional low-capacitance NPN device for ESD, which can not only reduce the parasitic capacitance, but also achieve a stronger current capacity by changing the corresponding structure. Therefore, the new device proposed by the present invention is very suitable for the application of transient protection of high-speed data transmission interfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a structural diagram of a bidirectional low-capacitance NPN device for ESD proposed in Embodiment 1 of the present invention.

[0018] Figure 2 It is a structural diagram of a bidirectional low-capacitance NPN device for ESD proposed in Embodiment 2 of the present invention.

[0019] Figure 3 It is a structural diagram of a bidirectional low-capacitance NPN device for ESD proposed in Embodiment 3 of the present invention.

[0020] Figure 4 It is a structural diagram of a bidirectional low-capacitance NPN device for ESD proposed in Embodiment 4 of the present invention.

[0021] 01 is an n+-type substrate, 11 is an n-type buried layer, 121 is a first p-type buried layer, 122 is a second p-type buried layer, 21 is a first n-type epitaxial layer, 22 is a second n-type epitaxial layer, 23 is a third n-type epitaxial layer, 24 is a fourth n-type epitaxial layer, 25 is a fifth n-type epitaxial layer, 03 is a p-type well region, 04 is a p-type well region with Zener implantation, 05 is a tungsten plug region, 06 is an n-type well region, 07 is a metal plug region, 31 is a first N+ contact region, 32 is a second N+ contact region, 33 is a third N+ contact region, 41 is a P+ region, 42 is a second P+ region, 43 is a third P+ region, 51 is a first isolation region, 52 is a second isolation region, 53 is a third isolation region, 54 is a fourth isolation region, 55 is a fifth isolation region, 61 is a first input or output port, 62 is a second input or output port. Detailed implementation manners

[0022] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0023] Example 1

[0024] As Figure 1 shown, a bidirectional low-capacitance NPN device for ESD proposed in this embodiment:

[0025] It includes: an n+-type substrate 01. The n-type epitaxial layer epitaxially grown on the n+-type substrate 01 is divided into five parts by five isolation regions and a tungsten plug region 05 with the same depth. The five isolation regions and a tungsten plug region 05 all penetrate the n-type epitaxial layer from the device surface and reach the inside of the n+-type substrate 01 at the bottom. The five divided parts are, from left to right in sequence: a first n-type epitaxial layer 21, a second n-type epitaxial layer 22, a third n-type epitaxial layer 23, a fourth n-type epitaxial layer 24, a fifth n-type epitaxial layer 25; where the first isolation region 51 is located at the leftmost end of the device; the second isolation region 52 is located between the first n-type epitaxial layer 21 and the second n-type epitaxial layer 22; the third isolation region 53 is located between the second n-type epitaxial layer 22 and the third n-type epitaxial layer 23; the tungsten plug region 05 is located between the third n-type epitaxial layer 23 and the fourth n-type epitaxial layer 24; the fourth isolation region 54 is located between the fourth n-type epitaxial layer 24 and the fifth n-type epitaxial layer 25; the fifth isolation region 55 is located at the rightmost end of the device;

[0026] There is an n-type buried layer 11 implanted before the epitaxial n-type epitaxial layer under the first n-type epitaxial layer 21 on the n+-type substrate 01 and between the first isolation region 51 and the second isolation region 52; there is a first p-type buried layer 121 implanted before the epitaxial n-type epitaxial layer under the second n-type epitaxial layer 22 on the n+-type substrate 01 and between the second isolation region 52 and the third isolation region 53; there is a second p-type buried layer 122 implanted before the epitaxial n-type epitaxial layer under the third n-type epitaxial layer 23 on the n+-type substrate 01 and between the third isolation region 53 and the tungsten plug region 05;

[0027] It also includes a p-type well region 03 implanted above the first n-type epitaxial layer 21; a P+ region 41 implanted on the surface of the p-type well region 03; a first N+ contact region 31 implanted on the surface of the second n-type epitaxial layer 22;

[0028] The surfaces of the first N+ contact region 31 and the P+ region 41 are short-circuited with metal to form the first input or output port 61 of the device; in addition, the contact parts between the third isolation region 53 and the first p-type buried layer 121 and the second p-type buried layer 122 on both sides are hollowed out, and the hollowed-out part is still the p-type buried layer, so that the p-type buried layers on both sides are connected into a whole;

[0029] On the right side of the fourth isolation region 54 is an NPN structure.

[0030] The NPN structure includes: a Zener-implanted p-type well region 04 implanted on the surface of the fifth n-type epitaxial layer 25, and a second N+ contact region 32 and a third N+ contact region 33 implanted on the surface of the Zener-implanted p-type well region 04; the tungsten plug region 05 and the surface of the second N+ contact region 32 are short-circuited with metal to form a path; the third N+ contact region 33 serves as the second input or output port 62 of the device.

[0031] Working principle:

[0032] When the ESD voltage is input from the first input or output port 61, the pn junction between the p-type well region 03 and the first n-type epitaxial layer 21 conducts, and the current flows from the input end through the P+ region 41, the p-type well region 03, the first n-type epitaxial layer 21, and the n-type buried layer 11 into the n+-type substrate 01. The n+-type substrate 01 and the second p-type buried layer 122 both form ohmic contacts with the tungsten plug region 05, so that they have the same electric potential. The current will flow from the n+-type substrate 01 through the tungsten plug region 05 to reach the second N+ contact region 32 through the device surface. As the current increases, the voltage drop generated on the p-type well region 04 with Zener injection is sufficient to turn on the npn, and the current will be output from the second input or output port 62. Vice versa, when the ESD voltage is input from the second input or output port 62, when its value rises to the breakdown voltage of the junction between the third N+ contact region 33 and the p-type well region 04 with Zener injection, the npn turns on, and the current passes through the second N+ contact region 32 to reach the tungsten plug region 05. Similarly, since the n+-type substrate 01 and the second p-type buried layer 122 both form ohmic contacts with the tungsten plug region 05, the current will pass through the second p-type buried layer 122 to reach the pn junction between the first p-type buried layer 121 and the second n-type epitaxial layer 22, making it forward-conduct and finally output from the first input or output port 61 through the first N+ contact region 31.

[0033] It can be seen that this device can combine the advantages of vertical devices and horizontal devices through the tungsten plug structure and establish ohmic contacts located in the body. In summary, the present invention proposes a bidirectional low-capacitance NPN device for ESD, which can not only reduce the parasitic capacitance, but also achieve stronger current capacity by changing the corresponding structure. Therefore, the new device and manufacturing method proposed by the present invention are very suitable for the application of transient protection of high-speed data transmission interfaces. The structure proposed by the present invention can be implemented by various other processes or substrates in addition to the embodiments, and its structure should be within the protection scope of the present invention.

[0034] Embodiment 2

[0035] As Figure 2 shown, the difference between this embodiment and Embodiment 1 is that the NPN structure is replaced with a PNP structure, including an n-type well region 06 implanted on the surface of the fifth n-type epitaxial layer 25; a second P+ region 42 and a third P+ region 43 implanted on the surface of the n-type well region 06; the tungsten plug region 05 and the surface of the second P+ region 42 are short-circuited with metal to form a path; the third P+ region 43 serves as the second input or output port 62 of the device.

[0036] Embodiment 3

[0037] As Figure 3As shown, the difference between this embodiment and Embodiment 1 lies in that the NPN structure is replaced by an SCR structure, including: a Zener-implanted p-type well region 04 implanted on the surface of the fifth n-type epitaxial layer 25 and an n-type well region 06 tangent to the right edge of the Zener-implanted p-type well region 04, a second P+ region 42 and a second N+ contact region 32 implanted on the surface of the Zener-implanted p-type well region 04, a third P+ region 43 and a third N+ contact region 33 implanted on the surface of the n-type well region 06; a metal tungsten plug region 05 is short-circuited with the surfaces of the second P+ region 42 and the second N+ contact region 32 by metal to form a path; the surfaces of the third P+ region 43 and the third N+ contact region 33 are short-circuited by metal to form a second input or output port 62.

[0038] Embodiment 4

[0039] As Figure 4 shown, the difference between this embodiment and Embodiment 1 lies in that the metal type of the metal tungsten plug region 05 is replaced by other metals to form a metal plug region 07.

[0040] An ESD protection bidirectional NPN device proposed by the present invention effectively reduces the parasitic capacitance by introducing a metal region and a series vertical diode structure.

[0041] The above embodiments merely illustrate the principles and effects of the present invention, rather than limiting the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A bidirectional low-capacitance NPN device for ESD protection, characterized in that Including: An n+-type substrate (01), on which an n-type epitaxial layer is epitaxially grown and is divided into five parts by five isolation regions and a tungsten plug region (05) with the same depth. The five isolation regions and a tungsten plug region (05) all penetrate from the device surface through the n-type epitaxial layer to the inside of the n+-type substrate (01). The five divided parts are, from left to right in sequence: the first n-type epitaxial layer (21), the second n-type epitaxial layer (22), the third n-type epitaxial layer (23), the fourth n-type epitaxial layer (24), and the fifth n-type epitaxial layer (25); among which the first isolation region (51) is located at the leftmost end of the device; the second isolation region (52) is located between the first n-type epitaxial layer (21) and the second n-type epitaxial layer (22); the third isolation region (53) is located between the second n-type epitaxial layer (22) and the third n-type epitaxial layer (23); the tungsten plug region (05) is located between the third n-type epitaxial layer (23) and the fourth n-type epitaxial layer (24); the fourth isolation region (54) is located between the fourth n-type epitaxial layer (24) and the fifth n-type epitaxial layer (25); the fifth isolation region (55) is located at the rightmost end of the device. Below the first n-type epitaxial layer (21) on the n+-type substrate (01) and between the first isolation region (51) and the second isolation region (52), there exists an n-type buried layer (11) injected before the epitaxial n-type epitaxial layer; below the second n-type epitaxial layer (22) on the n+-type substrate (01) and between the second isolation region (52) and the third isolation region (53), there exists a first p-type buried layer (121) injected before the epitaxial n-type epitaxial layer; below the third n-type epitaxial layer (23) on the n+-type substrate (01) and between the third isolation region (53) and the tungsten plug region (05), there exists a second p-type buried layer (122) injected before the epitaxial n-type epitaxial layer. It further includes a p-type well region (03) injected above the first n-type epitaxial layer (21); a P+ region (41) injected on the surface of the p-type well region (03); a first N+ contact region (31) injected on the surface of the second n-type epitaxial layer (22). The surface of the first N+ contact region (31) and the P+ region (41) are short-circuited by metal to form the first input or output port (61) of the device; in addition, the contact parts of the third isolation region (53) with the first p-type buried layer (121) and the second p-type buried layer (122) on both sides are hollowed out, and the hollowed-out part is still the p-type buried layer, so that the p-type buried layers on both sides are connected into a whole. On the right side of the fourth isolation region (54) is an NPN structure.

2. The bidirectional low-capacitance NPN device for ESD protection according to claim 1, characterized in that: The NPN structure includes: a p-type well region (04) with Zener injection injected on the surface of the fifth n-type epitaxial layer (25), and a second N+ contact region (32) and a third N+ contact region (33) injected on the surface of the p-type well region (04) with Zener injection; the tungsten plug region (05) and the surface of the second N+ contact region (32) are short-circuited by metal to form a path; the third N+ contact region (33) serves as the second input or output port (62) of the device.

3. The bidirectional low-capacitance NPN device for ESD protection according to claim 1, wherein: The NPN structure is replaced with a PNP structure, including an n-type well region (06) implanted on the surface of the fifth n-type epitaxial layer (25); a second P+ region (42) and a third P+ region (43) implanted on the surface of the n-type well region (06); a tungsten plug region (05) and the surface of the second P+ region (42) are shorted with metal to form a path; the third P+ region (43) serves as the second input or output port (62) of the device.

4. The bidirectional low-capacitance NPN device for ESD protection according to claim 1, wherein: The NPN structure is replaced with an SCR structure, including a Zener-implanted p-type well region (04) implanted on the surface of the fifth n-type epitaxial layer (25) and an n-type well region (06) tangent to the right edge of the Zener-implanted p-type well region (04), a second P+ region (42) and a second N+ contact region (32) implanted on the surface of the Zener-implanted p-type well region (04), a third P+ region (43) and a third N+ contact region (33) implanted on the surface of the n-type well region (06); a tungsten plug region (05) and the surfaces of the second P+ region (42) and the second N+ contact region (32) are shorted with metal to form a path; the surfaces of the third P+ region (43) and the third N+ contact region (33) are shorted with metal to form the second input or output port (62).

5. The bidirectional low-capacitance NPN device for ESD protection according to claim 1, wherein: The metal type of the tungsten plug region (05) is replaced with another metal to form a metal plug region (07).

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