Micro-trench gate IGBT device and method of manufacturing the same

Abstract

The application discloses a kind of micro-groove gate IGBT devices, including emitter PAD area and gate PAD area, the normal die area and short-circuit suppression area are arranged on the emitter PAD area, short-circuit suppression area is interval arrangement, and the normal die area is arranged between each adjacent two short-circuit suppression areas.The micro-groove gate IGBT device of the application, the introduction of short-circuit current suppression area can effectively reduce the short-circuit current of device, so as to ensure that the contact overcurrent capacity of device inside is enough, and the short-circuit current value is reasonable.Through the control of short-circuit current suppression area to the inhibition ability of short-circuit current, the size ratio of short-circuit current suppression area and normal die area is adjusted, the short-circuit current of device is controlled to suitable current value, so that the device has suitable short-circuit resistance capacity.The application further discloses a kind of manufacturing method of micro-groove gate IGBT device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor product technology. Specifically, this invention relates to a micro-trench gate IGBT device and its manufacturing method. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs), as one of the most important power semiconductor devices, combine the advantages of high operating frequency and low on-state voltage drop. In recent years, with the rapid development of the new energy and electric vehicle industries, the performance parameters of IGBTs have become increasingly demanding. As the most advanced technology internationally, micro-trench gate IGBTs can meet the current and future development needs of applications. Micro-trench gate technology features highly integrated deep trenches. These high-density deep trenches can store a large number of minority carriers in the drift region of the device when it is turned on, greatly reducing on-state losses. During reverse blocking, the high-density deep trenches provide reverse breakdown voltage close to that of a planar junction. The high-density trench gate can effectively adjust the optimal capacitance ratio, resulting in lower switching losses and superior switching characteristics during switching.

[0003] Existing micro-trench gate IGBTs are relatively small in size, especially the contact vias. The small contact via size leads to insufficient current handling, particularly under short-circuit conditions where the current is extremely high, and the contact vias' current-carrying capacity is insufficient. To enhance the contact's current-carrying capacity, increasing the number of contact vias inevitably increases the number of channels, resulting in excessive short-circuit current. To reduce the short-circuit current, the channel density must be reduced, which in turn necessitates a reduction in contact via density. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, the present invention provides a micro-trench gate IGBT device, the purpose of which is to reduce the short-circuit current of the device, ensure sufficient internal contact overcurrent capacity, and achieve a more reasonable short-circuit current value.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a micro trench gate IGBT device, including an emitter PAD region and a gate PAD region, wherein a normal die region and a short-circuit suppression region are provided on the emitter PAD region, the short-circuit suppression regions are arranged at intervals, and a normal die region is provided between every two adjacent short-circuit suppression regions.

[0006] The width of the short-circuit suppression region is 1-20 μm, and the width of the normal die region is 1-20 μm.

[0007] The ratio of the width of the short-circuit suppression region to the width of the normal die region is 1:2 to 2:1.

[0008] The short-circuit suppression regions are arranged in multiple rows, with adjacent rows of short-circuit suppression regions staggered.

[0009] The short-circuit suppression region and the normal die region are rectangular or square.

[0010] The present invention also provides a method for manufacturing a micro-trench gate IGBT device, wherein multiple short-circuit suppression regions are provided on the emitter PAD region along the direction parallel to the channel, and a normal die region is provided between every two adjacent short-circuit suppression regions.

[0011] The manufacturing process of the short-circuit suppression region includes the following steps:

[0012] S1. Prepare the terminal pressure-resistant ring;

[0013] S2. Prepare the short-circuit suppression region;

[0014] S3. Acceptor impurity ion implantation is performed on the short-circuit suppression region;

[0015] S4. Activate the acceptor impurity ions injected into the short-circuit suppression region.

[0016] In step S4, activation is performed by rapid thermal annealing, with an annealing temperature of less than or equal to 900°C and greater than or equal to 600°C, and an annealing time of 30 seconds to 2 minutes.

[0017] The manufacturing process of the short-circuit suppression region includes the following steps:

[0018] F1. Prepare the terminal pressure-resistant ring;

[0019] F2, Acceptor impurities are injected to form the Pwell region;

[0020] F3. Prepare the short-circuit suppression region;

[0021] F4. Ion implantation is performed on the short-circuit suppression region;

[0022] F5. High-temperature push-bonding of the Pwell region.

[0023] In step F5, the bonding temperature is 1050℃-1250℃, and the bonding time is 60min-150min.

[0024] The micro-trench gate IGBT device of this invention effectively reduces the short-circuit current by introducing a short-circuit current suppression region, thereby ensuring sufficient internal contact overcurrent capability and a reasonable short-circuit current value. By controlling the short-circuit current suppression capability of the short-circuit current suppression region and adjusting the size ratio of the short-circuit current suppression region to the normal die region, the short-circuit current of the device is controlled to a suitable current value, giving the device appropriate short-circuit withstand capability. Attached Figure Description

[0025] This manual includes the following figures, which illustrate the following:

[0026] Figure 1 This is a schematic diagram of the structure of the micro-trench gate IGBT device of the present invention;

[0027] Figure 2 This is a schematic diagram of the strip distribution of the short-circuit suppression region in the micro-trench gate IGBT device of the present invention;

[0028] Figure 3 This is a schematic diagram of the square arrangement of the short-circuit suppression region in the micro-trench gate IGBT device of the present invention;

[0029] Figure 4 This is a schematic diagram of the short-circuit suppression region arranged in a triangular pattern in the micro-trench gate IGBT device of the present invention;

[0030] Figure 5 This is a flowchart of the manufacturing method for a blocking short-circuit suppression region;

[0031] Figure 6 This is a flowchart of the manufacturing method for the weakened short-circuit suppression region;

[0032] The diagram is marked as follows:

[0033] 1. Emitter PAD region; 2. Gate PAD region; 3. Normal die region; 4. Short circuit suppression region. Detailed Implementation

[0034] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, in order to help those skilled in the art to have a more complete, accurate and in-depth understanding of the concept and technical solutions of the present invention, and to facilitate its implementation.

[0035] Example 1

[0036] like Figure 2As shown, the present invention provides a micro-trench gate IGBT device, including an emitter PAD region (E-pad) and a gate PAD region (G-pad). The emitter PAD region is provided with multiple normal die regions and multiple short-circuit suppression regions. The short-circuit suppression regions are arranged at intervals. A normal die region is arranged between every two adjacent short-circuit suppression regions, and a short-circuit suppression region is arranged between every two adjacent normal die regions.

[0037] In this embodiment, the width of the short-circuit suppression region is 1-20 μm, and the width of the normal die region is 1-20 μm. The ratio of the width of the short-circuit suppression region to the width of the normal die region is between 1:2 and 2:1. The ratio of the width of the short-circuit suppression region to the width of the normal die region can be 1:2, 2:3, 3:2, 1:1, or 2:1.

[0038] Example 2

[0039] like Figure 3 As shown, in the micro-trench gate IGBT device provided in this embodiment, the short-circuit suppression region can be arranged in a square pattern. Compared with the strip pattern, the square arrangement results in a more uniform current distribution during device conduction, which can improve the overcurrent capability of the device. The shape of the short-circuit suppression region can be rectangular or oriented in the positive direction, but the area ratio of the short-circuit suppression region to the normal die region in the square arrangement is close to 1:1.

[0040] like Figure 3 As shown, all short-circuit suppression regions are arranged in multiple rows along the length of the emitter PAD region, and all short-circuit suppression regions in the same row are arranged sequentially along the width of the emitter PAD region. Within each row of short-circuit suppression regions, a normal die region is placed between every two adjacent short-circuit suppression regions. The short-circuit suppression regions in adjacent rows are staggered. This staggered arrangement means that, for two adjacent rows of short-circuit suppression regions, on a projection plane perpendicular to the length of the emitter PAD region, the position of each short-circuit suppression region in one row is adjacent to the position of a short-circuit suppression region in the other row.

[0041] Example 3

[0042] like Figure 4 As shown, in the micro-trench gate IGBT device provided in this embodiment, the short-circuit suppression region can be arranged in a triangular pattern. The triangular arrangement combines the advantages of strip and square arrangements, and the current distribution is relatively more uniform during device conduction. At the same time, the ratio of the short-circuit suppression region to the normal die region can be adjusted according to application requirements.

[0043] Example 4

[0044] This embodiment provides a method for manufacturing a micro-trench gate IGBT device, wherein multiple short-circuit suppression regions are set on the emitter PAD region along the direction parallel to the channel, and a normal die region is set between every two adjacent short-circuit suppression regions.

[0045] This embodiment provides a micro-trench gate IGBT device whose short-circuit suppression region can be divided into blocking type, weakening type, and combined type. The blocking type means that when the device enters the short-circuit condition, its short-circuit suppression region cannot be opened at all, and the short-circuit current in the short-circuit suppression region is zero. The weakening type means that when the device enters the short-circuit condition, its short-circuit suppression region is weakly opened, and the short-circuit current in the short-circuit suppression region is very small. The combined type means that the short-circuit suppression region inside the device includes both blocking and weakening types.

[0046] This embodiment provides a micro-trench gate IGBT device, whose blocking short-circuit suppression region is manufactured by adding a dose greater than or equal to 1E14 / cm to the device surface. 2 High-dose boron ion implantation blocks the channel in the short-circuit suppression region, preventing the short-circuit suppression region from opening when the device is in a short-circuit state, thereby suppressing the short-circuit current.

[0047] like Figure 5 As shown, in this embodiment, the manufacturing process of the short-circuit suppression region includes the following steps:

[0048] S1. Prepare the terminal pressure-resistant ring;

[0049] S2. Prepare the short-circuit suppression region;

[0050] S3. Acceptor impurity ion implantation is performed on the short-circuit suppression region;

[0051] S4. Activate the acceptor impurity ions injected into the short-circuit suppression region;

[0052] S5. Fabricate contact holes, front metal electrodes, passivation layers, and back metal electrodes.

[0053] In step S1 above, the structure and doping settings of the conventional terminal withstand ring region and trench active region are completed.

[0054] In step S2 above, the short-circuit suppression region is opened by photolithography, which requires sequential steps such as coating, exposure, development, CD inspection, and adhesive fixation.

[0055] In step S3 above, ion implantation is performed on the short-circuit suppression region. Examples of implanted ions include acceptor impurity ions such as B ions and BF2 ions.

[0056] In step S4 above, activation is performed by rapid thermal annealing, with an annealing temperature of less than or equal to 900°C and greater than or equal to 600°C, and an annealing time of 30 seconds to 2 minutes.

[0057] Example 5

[0058] This embodiment provides a micro-trench gate IGBT device. The weakened short-circuit suppression region is manufactured by dividing the Pwell region of the device into two parts: one part has a normal threshold value, and the other part has a threshold value set to 8-12V. The part with the higher threshold is the short-circuit suppression region. When the device is in a short-circuit state, the short-circuit suppression region is weakly open, with a very small electron current, reducing the overall short-circuit current of the device. However, since the short-circuit suppression region is in an open state and has some electron current, it can effectively share the hole current in the normal die region, effectively reducing the overcurrent pressure in the normal die region.

[0059] like Figure 6 As shown, in this embodiment, the manufacturing process of the short-circuit suppression region includes the following steps:

[0060] F1. Prepare the terminal pressure-resistant ring;

[0061] F2, Acceptor impurities are injected to form the Pwell region;

[0062] F3. Prepare the short-circuit suppression region;

[0063] F4. Ion implantation is performed on the short-circuit suppression region;

[0064] F5. High-temperature push-bonding of the Pwell region;

[0065] F6. Fabrication of contact holes, front metal electrodes, passivation layers, and back metal electrodes, etc.

[0066] In step F3 above, the short-circuit suppression region is opened by photolithography, which requires sequential steps such as coating, exposure, development, CD inspection, and adhesive fixation.

[0067] In step F4 above, ion implantation is performed on the short-circuit suppression region. Examples of implanted ions include B ions, with an implantation dose of 1e13-2e14 cm⁻¹. -2 .

[0068] In step F5 above, the bonding temperature is 1050℃-1250℃ and the bonding time is 60min-150min.

[0069] Example 6

[0070] This embodiment provides a micro-trench gate IGBT device, whose comprehensive short-circuit suppression region manufacturing method is to add a cell region opening when the device is set in the terminal ring region, and inject the terminal ring region acceptor impurities into the die region short-circuit suppression region. Its manufacturing method is the same as that of conventional micro-trench gate, except that the die region is added at the ring region injection position.

[0071] The present invention has been described above by way of example with reference to the accompanying drawings. Obviously, the specific implementation of the present invention is not limited to the above-described manner. Any non-substantial improvements made using the inventive concept and technical solution; or the direct application of the inventive concept and technical solution to other situations without modification, are all within the protection scope of the present invention.

Claims

1. A micro-trench gate IGBT device, comprising an emitter PAD region and a gate PAD region, characterized in that, The emitter PAD region is provided with multiple normal die regions and multiple short-circuit suppression regions. The short-circuit suppression regions are arranged in a square pattern and are spaced apart. All short-circuit suppression regions are arranged in multiple rows along the length of the emitter PAD region, and all short-circuit suppression regions in the same row are arranged sequentially along the width of the emitter PAD region; in all short-circuit suppression regions in the same row, a normal die region is set between every two adjacent short-circuit suppression regions. The short-circuit suppression regions in two adjacent rows are staggered. This staggered arrangement means that, for two adjacent rows of short-circuit suppression regions, on a projection plane perpendicular to the length direction of the emitter PAD region, the position of each short-circuit suppression region in one row on the projection plane is adjacent to the position of a short-circuit suppression region in the other row on the projection plane.

2. The micro-trench gate IGBT device according to claim 1, characterized in that, The width of the short-circuit suppression region is 1-20 μm, and the width of the normal die region is 1-20 μm.

3. The micro-trench gate IGBT device according to claim 1, characterized in that, The ratio of the width of the short-circuit suppression region to the width of the normal die region is 1:2 to 2:

1.

4. The micro-trench gate IGBT device according to claim 1, characterized in that, The short-circuit suppression region and the normal die region are rectangular or square.

5. The method for manufacturing a micro-trench gate IGBT device according to any one of claims 1 to 4, characterized in that, Multiple short-circuit suppression regions are set on the emitter PAD region along the direction parallel to the channel, and a normal die region is set between every two adjacent short-circuit suppression regions.

6. The method for manufacturing a micro-trench gate IGBT device according to claim 5, characterized in that, The manufacturing process of the short-circuit suppression region includes the following steps: S1. Prepare the terminal pressure-resistant ring; S2. Prepare the short-circuit suppression region; S3. Acceptor impurity ion implantation is performed on the short-circuit suppression region; S4. Activate the acceptor impurity ions injected into the short-circuit suppression region.

7. The method for manufacturing a micro-trench gate IGBT device according to claim 6, characterized in that, In step S4, activation is performed by rapid thermal annealing, with an annealing temperature of less than or equal to 900°C and greater than or equal to 600°C, and an annealing time of 30 seconds to 2 minutes.

8. The method for manufacturing a micro-trench gate IGBT device according to claim 5, characterized in that, The manufacturing process of the short-circuit suppression region includes the following steps: F1. Prepare the terminal pressure-resistant ring; F2, Acceptor impurities are injected to form the Pwell region; F3. Prepare the short-circuit suppression region; F4. Ion implantation is performed on the short-circuit suppression region; F5. High-temperature push-bonding of the Pwell region.

9. The method for manufacturing a micro-trench gate IGBT device according to claim 8, characterized in that, In step F5, the bonding temperature is 1050℃-1250℃, and the bonding time is 60min-150min.

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