A column-level readout circuit and an infrared imager

Abstract

The present invention provides a column-level readout circuit and an infrared imager, which relate to the field of integrated circuits. A transconductance module generates a first current and a second current and respectively outputs them to a first current-controlled oscillator and a second current-controlled oscillator; the first current-controlled oscillator receives the first current to generate a first pulse output and transmits it to a first Gray code counting unit; the first Gray code counting unit performs an operation on the first pulse output to obtain a first counting result and transmits it to a first self-calibration unit; a first phase sampling unit samples the phase of each stage of the ring oscillator to obtain first phase information and transmits it to the first self-calibration unit; the first self-calibration unit calibrates the first counting result based on the first phase information to obtain a first accurate code value and transmits it to a difference unit; the difference unit subtracts the second accurate code value from the first accurate code value to obtain a quantization result and outputs it outside the chip. The column-level readout circuit of the present invention has low power consumption, small occupied area, good monotonicity, high signal-to-noise ratio, and has high practicability.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a column-level readout circuit and an infrared imager. Background Art

[0002] A column-level analog-to-digital converter (Column-ADC) refers to implementing the function of analog-to-digital conversion at the column level in an array-type readout circuit. With the progress of technology, the scale of infrared focal plane detection arrays is getting larger and the pixel size is getting smaller. Implementing analog-to-digital converters at the pixel level and output level is respectively limited by area, speed, and accuracy. Implementing analog-to-digital conversion at the column level is only limited by one dimension in terms of area compared with implementing it in pixels, the requirements for speed are relaxed compared with implementing it at the output level or off-chip, and the signal-to-noise ratio is better. It is a relatively mature method in current array-type readout circuits.

[0003] However, in current Column-ADCs, due to the structure of the column-level readout circuit, there are errors in the quantization results, and it occupies a large area, consumes a large amount of power, has poor monotonicity, and a low signal-to-noise ratio. Summary of the Invention

[0004] In view of the above problems, the present invention is proposed to provide a column-level readout circuit and an infrared imager that solve or partially solve the above problems.

[0005] In a first aspect of an embodiment of the present invention, a column-level readout circuit is provided. The column-level readout circuit includes: a transconductance module, a first current-controlled oscillator, a second current-controlled oscillator, a first Gray code counting unit, a second Gray code counting unit, a first phase sampling unit, a second phase sampling unit, a first self-calibration unit, a second self-calibration unit, and a difference unit;

[0006] The first current-controlled oscillator and the second current-controlled oscillator have the same structure and function, the first Gray code counting unit and the second Gray code counting unit have the same structure and function, the first phase sampling unit and the second phase sampling unit have the same structure and function, and the first self-calibration unit and the second self-calibration unit have the same structure and function;

[0007] The transconductance module receives a pixel voltage and a reference voltage from a pixel array, generates a first current and a second current, and outputs the first current to the first current-controlled oscillator and the second current to the second current-controlled oscillator;

[0008] For the first current-controlled oscillator: it receives the first current, generates a first pulse output, and transmits the first pulse output to the first Gray code counting unit;

[0009] For the first Gray code counting unit: perform operations on the first pulse output to obtain a first counting result and transmit it to the first self-calibration unit;

[0010] For the first phase sampling unit: sample the phases of each stage of the ring oscillator in the first fluidic oscillator to obtain first phase information and transmit it to the first self-calibration unit;

[0011] For the first self-calibration unit: based on the first phase information, calibrate the first counting result to obtain a first accurate code value and transmit it to the difference unit;

[0012] The difference unit subtracts the second accurate code value from the second self-calibration unit from the first accurate code value, and outputs the difference result as a quantization result outside the chip.

[0013] Optionally, the transconductance module converts the voltage difference between the pixel voltage and the reference voltage into the first current and the second current with a current difference.

[0014] Optionally, the transconductance module includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a resistor;

[0015] The first MOS transistor and the second MOS transistor are respectively two input pair transistors of the transconductance module. The gate of the first MOS transistor receives the pixel voltage, and the gate of the second MOS transistor receives the reference voltage;

[0016] The fifth MOS transistor and the sixth MOS transistor are respectively connected to a current source to provide two current biases. The gates of the fifth MOS transistor and the sixth MOS transistor both receive a first bias voltage;

[0017] The sixth MOS transistor, the second MOS transistor, and the fourth MOS transistor are connected in series in sequence. One end of the resistor is connected to the series connection point of the sixth MOS transistor and the second MOS transistor, and the other end of the resistor is connected to the pixel array;

[0018] The third MOS transistor and the fourth MOS transistor are common-gate transistors, which are used to isolate the influence of the first fluidic oscillator and the second fluidic oscillator on the two input pair transistors. The third MOS transistor and the fourth MOS transistor respectively output the first current and the second current to the first fluidic oscillator and the second fluidic oscillator. The gates of the third MOS transistor and the fourth MOS transistor both receive a second bias voltage.

[0019] Optionally, each stage of the ring oscillator includes two output terminals; the first phase sampling unit includes: multiple groups of SAFF flip-flops, a parity bit flip-flop, and a count value flip-flop;

[0020] Each group of SAFF flip-flops includes: two SAFF flip-flops, and the two SAFF flip-flops respectively sample the phases of the two output terminals of each stage of the ring oscillator. Each SAFF flip-flop uses an external Sample signal as an enable signal and samples the phase when the Sample signal is valid;

[0021] The signal output by each SAFF flip-flop is transmitted to a phase decoder, so that the phase decoder decodes it into the first phase information corresponding to each stage of the ring oscillator;

[0022] Both the parity bit flip-flop and the count value flip-flop are SAFF flip-flops;

[0023] The parity bit flip-flop samples the parity bit in the first Gray code counting unit, obtains the sampled parity bit signal and transmits it to the first self-calibration unit. The parity bit flip-flop uses the Sample signal as an enable signal and samples the parity bit in the first Gray code counting unit when the Sample signal is valid;

[0024] The count value flip-flop samples the first counting result, obtains the binary code value and parity signal corresponding to the first counting result and transmits them to the first self-calibration unit. The count value flip-flop uses the Sample signal as an enable signal and samples the first counting result when the Sample signal is valid.

[0025] Optionally, the first self-calibration unit includes: an OR gate, an exclusive NOR gate, an AND gate, and an adder;

[0026] The OR gate receives the first phase information corresponding to each stage of the ring oscillator and outputs a phase check bit signal to the AND gate;

[0027] The exclusive NOR gate receives the sampled parity bit signal and the parity signal and outputs a count check bit signal to the AND gate;

[0028] The AND gate outputs a self-calibration bit signal to the adder, and the adder uses the self-calibration bit signal as an enable signal;

[0029] The adder uses the binary code value corresponding to the first counting result and the power supply voltage as input signals, and the adder outputs the first accurate code value.

[0030] Optionally, the first Gray code counting unit includes: an asynchronous Gray code counter;

[0031] Take the least significant bit of the asynchronous Gray code counter as the post-sampling check bit, and take the second least significant bit of the asynchronous Gray code counter as the least significant bit of the count value of the asynchronous Gray code counter. The role of the post-sampling check bit is: as a 1 / 2 bit to judge the counting state of the asynchronous Gray code counter at the current moment. Among them, when the asynchronous Gray code counter is at the edge of a transition, the post-sampling check bit is a definite value, and the counting state of the asynchronous Gray code counter at the current moment is judged by combining the count value at the current moment;

[0032] The counting state calibrates the first counting result in combination with the corresponding relationship between the count value at the current moment and the first phase information corresponding to each ring oscillator. Among them, if the counting state is that the count is in the last N phases, and the phase sampled at the current moment is the first N phases, then the asynchronous Gray code counter at the current moment is in a state that has not flipped yet, and the calibration adds one to the first counting result to obtain the first accurate code value.

[0033] Optionally, the specific steps for the post-sampling check bit to judge the counting state of the asynchronous Gray code counter at the current moment by combining the count value at the current moment include:

[0034] If the value of the post-sampling check bit is 0 and the count value at the current moment is even, then the counting state at the current moment is: the count is in the first N phases;

[0035] If the value of the post-sampling check bit is 1 and the count value at the current moment is even, then the counting state at the current moment is: the count is in the last N phases;

[0036] If the value of the post-sampling check bit is 0 and the count value at the current moment is odd, then the counting state at the current moment is: the count is in the last N phases;

[0037] If the value of the post-sampling check bit is 1 and the count value at the current moment is odd, then the counting state at the current moment is: the count is in the first N phases.

[0038] Optionally, for any flow-controlled oscillator, there is:

[0039] The oscillation frequency f of the flow-controlled oscillator CCO is modulated by the magnitude of the current I flowing into the flow-controlled oscillator CCO That is:

[0040] f CCO = K CCO I CCO + f0

[0041] Where K CCO is the frequency modulation sensitivity of the flow-controlled oscillator, and f0 represents the current I CCOThe intercept when t = 0, and the flow control oscillator integrates the output phase information of each stage of the ring oscillator within the time T0 The integration is as follows:

[0042]

[0043] Where is the initial phase of each stage of the ring oscillator, and the total integrated phase during the integration process is obtained from the count value and the phase value at the end of the oscillation of the flow control oscillator:

[0044]

[0045] Where N is the number of delay stages of the flow control oscillator, K is the count value of the asynchronous Gray code counter, N0 is the remaining number of phase bits sampled by the phase sampling, is the quantized unit phase, is the unquantized residual phase. According to the charge conservation, the total integrated charge amount is:

[0046] I CCO ×T0 = (2N×K + N0)×Q u +Q s

[0047] Where Q u is the average charge amount consumed when oscillating one phase , and Q s is the unquantized residual charge. By quantizing the total integrated phase within the time T0, the quantization of the input current is achieved in the time domain.

[0048] Optionally, let the overall transconductance of the transconductance module be G m , then there is:

[0049] ΔI CCO = G m ×ΔV IN

[0050] Where Gm = 1 / R, R represents the resistance value of the resistor, and ΔV IN = V REF -V IN , V REF represents the voltage value of the reference voltage, and V IN represents the voltage value of the pixel voltage. Then the current difference I CCO1，2 between the first current and the second current generated by the transconductance module is expressed as:

[0051] I CCO1，2 = I0 ± ΔI CCO .

[0052] Wherein, I0 represents the current value provided by the current source, and ΔI CCO represents the current value flowing through the resistor.

[0053] In a second aspect of the embodiments of the present invention, an infrared imager is provided. The infrared imager includes: a photocurrent detector and a column-level readout circuit according to any one of the first aspects.

[0054] In the column-level readout circuit provided by the present invention, the first current-controlled oscillator and the second current-controlled oscillator have the same structure and function, the first Gray code counting unit and the second Gray code counting unit have the same structure and function, the first phase sampling unit and the second phase sampling unit have the same structure and function, and the first self-calibration unit and the second self-calibration unit have the same structure and function.

[0055] The transconductance module receives the pixel voltage and the reference voltage from the pixel array, generates a first current and a second current, and outputs the first current to the first current-controlled oscillator and the second current to the second current-controlled oscillator.

[0056] For the first current-controlled oscillator: it receives the first current, generates a first pulse output, and transmits the first pulse output to the first Gray code counting unit; naturally, it can be understood that for the second current-controlled oscillator: it receives the second current, generates a second pulse output, and transmits the second pulse output to the second Gray code counting unit.

[0057] For the first Gray code counting unit: it operates on the first pulse output, obtains a first counting result and transmits it to the first self-calibration unit; naturally, it can be understood that for the second Gray code counting unit: it operates on the second pulse output, obtains a second counting result and transmits it to the second self-calibration unit.

[0058] For the first phase sampling unit: it samples the phase of each stage of the ring oscillator in the first current-controlled oscillator, obtains first phase information and transmits it to the first self-calibration unit; naturally, it can be understood that for the second phase sampling unit: it samples the phase of each stage of the ring oscillator in the second current-controlled oscillator, obtains second phase information and transmits it to the second self-calibration unit.

[0059] For the first self-calibration unit: based on the first phase information, it calibrates the first counting result, obtains a first accurate code value and transmits it to the difference unit; naturally, it can be understood that for the second self-calibration unit: based on the second phase information, it calibrates the second counting result, obtains a second accurate code value and transmits it to the difference unit. Finally, the difference unit calculates the difference between the second accurate code value and the first accurate code value, and outputs the difference result as a quantization result outside the chip.

[0060] The column-level readout circuit of the present invention uses a current-controlled oscillator to complete the time-domain quantization of the voltage within the pixel at the column level, and has a self-calibration function based on sampling error, with technical advantages such as low power consumption, small occupied area, good monotonicity, and high signal-to-noise ratio, and has high practicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0062] Figure 1 is a schematic structural diagram of a preferred transconductance module in an embodiment of the present invention;

[0063] Figure 2 is a schematic structural diagram of a preferred first phase sampling unit in an embodiment of the present invention;

[0064] Figure 3 is a schematic structural diagram of a preferred first self-calibration unit in an embodiment of the present invention;

[0065] Figure 4 is the overall working timing diagram in an embodiment of the present invention;

[0066] Figure 5 is the overall structural diagram of the column-level readout circuit shown in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0067] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0068] The column-level readout circuit of the embodiment of the present invention includes: a transconductance module, a first current-controlled oscillator, a second current-controlled oscillator, a first Gray code counting unit, a second Gray code counting unit, a first phase sampling unit, a second phase sampling unit, a first self-calibration unit, a second self-calibration unit, and a difference unit.

[0069] Among them, the structures and functions of the first current-controlled oscillator and the second current-controlled oscillator are the same, the structures and functions of the first Gray code counting unit and the second Gray code counting unit are the same, the structures and functions of the first phase sampling unit and the second phase sampling unit are the same, and the structures and functions of the first self-calibration unit and the second self-calibration unit are the same. Therefore, in the following, the first current-controlled oscillator, the first Gray code counting unit, the first phase sampling unit, and the first self-calibration unit are taken as examples for explanation and illustration. Since the structures and functions of the second current-controlled oscillator, the second Gray code counting unit, the second phase sampling unit, and the second self-calibration unit are the same as those of their corresponding parts, the column-level readout circuit of the embodiment of the present invention can be simply understood.

[0070] In the column-level readout circuit, the transconductance module receives the pixel voltage and the reference voltage from the pixel array, generates a first current and a second current, and outputs the first current to the first current-controlled oscillator and the second current to the second current-controlled oscillator. Specifically, the transconductance module converts the voltage difference between the received pixel voltage and the reference voltage into the first current and the second current with a current difference.

[0071] For the first current-controlled oscillator: it receives the first current, generates a first pulse output, and transmits the first pulse output to the first Gray code counting unit. Naturally, it can be understood that for the second current-controlled oscillator: it receives the second current, generates a second pulse output, and transmits the second pulse output to the second Gray code counting unit.

[0072] For the first Gray code counting unit: it performs an operation on the first pulse output, obtains a first counting result and transmits it to the first self-calibration unit. Naturally, it can be understood that for the second Gray code counting unit: it performs an operation on the second pulse output, obtains a second counting result and transmits it to the second self-calibration unit.

[0073] For the first phase sampling unit: it samples the phase of each stage of the ring oscillator in the first current-controlled oscillator, obtains a first phase information and transmits it to the first self-calibration unit. Naturally, it can be understood that for the second phase sampling unit: it samples the phase of each stage of the ring oscillator in the second current-controlled oscillator, obtains a second phase information and transmits it to the second self-calibration unit.

[0074] For the first self-calibration unit: based on the first phase information, it calibrates the first counting result, obtains a first accurate code value and transmits it to the difference unit. Naturally, it can be understood that for the second self-calibration unit: based on the second phase information, it calibrates the second counting result, obtains a second accurate code value and transmits it to the difference unit.

[0075] The difference unit subtracts the second accurate code value from the first accurate code value, and outputs the difference result as a quantization result outside the chip.

[0076] To more clearly illustrate the above column-level readout circuit, taking the circuit structure of a preferred specific transconductance module as an example, the structure and working principle of the transconductance module will be described.

[0077] Refer to Figure 1 , which shows a schematic structural diagram of a preferred transconductance module. The transconductance module includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a resistor. It should be noted that Figure 1 In

[0078] Figure 1 , the first MOS transistor M1 and the second MOS transistor M2 in IN are respectively the two input pair transistors of the transconductance module. The gate of the first MOS transistor M1 receives the pixel voltage V IN , the source and drain of the first MOS transistor are respectively connected to the drain of the fifth MOS transistor M5 and the source of the third MOS transistor M3, and RS<1> represents the strobe switch of each row of P(1, 1) in the pixel array. The gate of the second MOS transistor M2 receives the reference voltage V REF .

[0079] The source of the fifth MOS transistor M5 and the source of the sixth MOS transistor M6 are respectively connected to a current source. The current values of the two current biases provided by the current source are both I0. The gates of the fifth MOS transistor M5 and the sixth MOS transistor M6 both receive the first bias voltage V BP .

[0080] The sixth MOS transistor M6, the second MOS transistor M2, and the fourth MOS transistor M4 are connected in series in sequence. One end of the resistor R is connected to the drain of the sixth MOS transistor M6 and the source of the second MOS transistor M2 respectively, and the other end of the resistor R is connected to the pixel array.

[0081] The third MOS transistor M3 and the fourth MOS transistor M4 are common-gate transistors, which are used to isolate the influence of the first current-controlled oscillator and the second current-controlled oscillator on the two input pair transistors (i.e., the first MOS transistor M1 and the second MOS transistor M2). The third MOS transistor M3 and the fourth MOS transistor M4 respectively output the first current I CCO1 and the second current I CCO2 to the first current-controlled oscillator and the second current-controlled oscillator. The gates of the third MOS transistor M3 and the fourth MOS transistor M4 both receive the second bias voltage V B .

[0082] If the overall transconductance of the transconductance module is set as G m , then there is:

[0083] ΔICCO = G m × ΔVI N

[0084] where Gm = 1 / R, R represents the resistance value of resistor R, ΔV IN = V REF - V IN ,V REF represents the voltage value of reference voltage V REF ,V IN represents the voltage value of pixel voltage V IN ,then the current difference I CCO1，2 between the first current and the second current generated by the transconductance module is expressed as:

[0085] I CCO1，2 = I0 ± ΔI CCO .

[0086] where I0 represents the current value provided by the current source, and ΔI CCO represents the current value flowing through resistor R.

[0087] For each voltage-controlled oscillator, each stage of the ring oscillator includes two output terminals. And the first phase sampling unit includes: multiple groups of SAFF flip-flops, parity check flip-flops, and count value flip-flops. Referring to Figure 2 , a schematic structural diagram of a preferred first phase sampling unit is shown. Figure 2 In, the dashed box CCO represents the structure of the voltage-controlled oscillator; K-bit GRAY COUNTER represents a K-bit asynchronous Gray code counter (i.e., the first Gray code counting unit); COUNTER<1:K> represents the count value output by the K-bit asynchronous Gray code counter; FLAG0 represents the parity check bit of the K-bit asynchronous Gray code counter; Sample represents the Sample signal; PHASE DECODER represents the phase decoder; GRAY to BIN represents the module for converting the count value into the corresponding binary code value, COUNTER_BIN<1:K> represents the binary code value corresponding to the first counting result, ODD-EVEN represents the parity signal; FLAG represents the parity check bit signal after sampling; the multiple groups of SAFF flip-flops are connected to the two output terminals of each stage of the ring oscillator, and each is represented by SAFF; the SAFF flip-flop that outputs FLAG is the parity check flip-flop; the SAFF flip-flops that output COUNTER_BIN<1:K> and ODD-EVEN are the count value flip-flops.

[0088] By Figure 2It can be known that each group of SAFF flip - flops in multiple groups of SAFF flip - flops includes: two SAFF flip - flops. The two SAFF flip - flops respectively sample the phases of the two output terminals of each stage of the ring oscillator. Each SAFF flip - flop uses the external Sample signal as the enable signal and performs phase sampling when the Sample signal is valid.

[0089] The signal output by each SAFF flip - flop is transmitted to the phase decoder PHASE DECODER, so that the phase decoder PHASE DECODER decodes it into the first - phase information PHASE<1:2N> corresponding to each stage of the ring oscillator.

[0090] The parity - bit flip - flop samples the parity - bit FLAG0 in the first Gray - code counter unit, obtains the sampled parity - bit signal FLAG and transmits it to the first self - calibration unit. The parity - bit flip - flop uses the Sample signal as the enable signal and samples the parity - bit FLAG0 in the first Gray - code counter unit when the Sample signal is valid.

[0091] The count - value flip - flop samples the first count result COUNTER<1:K>, obtains the binary - code value COUNTER_BIN<1:K> corresponding to the first count result and the parity signal ODD - EVEN and transmits them to the first self - calibration unit. The count - value flip - flop uses the Sample signal as the enable signal and samples the first count result when the Sample signal is valid.

[0092] When the current - controlled oscillator integration ends, the falling edge of the Sample signal is valid. The SAFF flip - flop collects the phase information of each stage of the ring oscillator, and then the phase decoder decodes it into phase information. At the same time, the count value and the parity - bit of the asynchronous Gray - code counter that is counting are also sampled by the SAFF flip - flop together. Using SAFF flip - flops can alleviate the error - code situation caused by the metastability of flip - flops.

[0093] For any current - controlled oscillator, there is:

[0094] The oscillation frequency f of the current - controlled oscillator CCO is modulated by the magnitude of the current I flowing into the current - controlled oscillator, that is: F CCO = K CCO I CCO + f0 CCO where K

[0095] is the frequency - modulation sensitivity of the current - controlled oscillator, and f0 represents the intercept when the current I CCO = 0. The current - controlled oscillator integrates the output phase information of each stage of its ring oscillator within the time T0 as: CCO = For:

[0096]

[0097] wherein is the initial phase of each - stage ring oscillator, and the total integration phase during the integration process is obtained from the count value and phase value at the end of the oscillation of the current - controlled oscillator:

[0098]

[0099] where N is the number of delay stages of the current - controlled oscillator, K is the count value of the asynchronous Gray - code counter, N0 is the remaining number of phase bits sampled by the phase sampling, is the quantized unit phase, is the unquantized residual phase. According to the charge conservation, the total integrated charge quantity is:

[0100] I CCO ×T0=(2N×K + N0)×Q u +Q s

[0101] where Q u is the average charge quantity consumed when oscillating one phase and Q s is the unquantized residual charge. By quantizing the total integration phase within the time T0, the quantization of the input current is achieved in the time domain.

[0102] Referring to Figure 3 , a structural schematic diagram of a preferred first self - calibration unit is shown. Figure 3 It includes: an OR gate OR, an exclusive - NOR gate AOR, an AND gate AND, and an adder K - bit ADDER.

[0103] The OR gate receives the first - phase information corresponding to each - stage ring oscillator, Figure 3 where PHASE<1>......PHASE <n>, the output phase check bit signal PHASE_CHECK is sent to the AND gate AND; the exclusive NOR gate AOR receives the sampled check bit signal FLAG and the parity signal ODD - EVEN, and outputs the count check bit signal COUNTER_CHECK to the AND gate AND.

[0104] The output of the AND gate, the self - calibration bit signal Calibration, is sent to the enable terminal EN of the adder K - bitADDER. The adder K - bit ADDER uses the self - calibration bit signal Calibration as the enable signal; the adder K - bit ADDER takes the binary code value COUNTER_BIN<1:K> corresponding to the first count result and the voltage signal VDD of the power supply voltage as input signals, and the adder K - bit ADDER outputs the first accurate code value COUNTER_OUT<1:K>.

[0105] In the embodiment of the present invention, the overall working timing diagram is referred to Figure 4 as shown, RS<1>~RS <m>RS is the row select signal that conducts sequentially from the first row to the Mth row, FLAG is the parity bit signal after sampling, Phase<1> to Phase<2N> are the phases of the first-stage to the Nth-stage ring oscillators, Counter_ideal and Counter_actual are the count values of the ideal and actual asynchronous Gray code counters respectively, the time delay difference between them is Δt, and the Sample signal is the sampling signal, which samples at the falling edge.

[0106] When the integration within the pixel ends, the row select signal RS is turned on row by row. The transconductance module generates a differential current that flows into two current-controlled oscillators. After a time I0, at the falling edge of the Sample signal, the phases and count values of each stage of the ring oscillator of the current-controlled oscillator are sampled to obtain the integration time, thus completing quantization.

[0107] Due to the problem of delay in the asynchronous Gray code counter, the higher the number of bits, the longer the flip delay time. And the oscillation frequency of the current-controlled oscillator is very high. Affected by the flip delay during sampling, the phase value and the count value may not match, resulting in a relatively serious error code problem, which is also one of the main factors restricting the performance of time-domain quantization currently.

[0108] Take Figure 4 as an example. When the sampling signal Sample is valid, since the asynchronous Gray code counter has not flipped due to the time delay, if the count value sampled at this time is 01 while the ideal count value is 11, it will cause serious error codes.

[0109] To solve the above problem, the column-level readout circuit proposed in the present invention proposes a self-calibration method. An asynchronous Gray code counter is used to count the oscillation period. The advantages are low power consumption, and no matter whether the sampling is correct or not, the counter code value will have at most one deviation. Using this feature, the present invention uses the lowest bit of the asynchronous Gray code counter as the parity bit, and the second lowest bit as the lowest bit Q<0> of the counter. The role of the parity bit is: as a 1 / 2 bit to judge the counting state of the asynchronous Gray code counter at the current moment. Among them, at the edge where the asynchronous Gray code counter is in a transition, the parity bit after sampling is a definite value, and the counting state of the asynchronous Gray code counter at the current moment is judged by combining the count value at the current moment.

[0110] After that, the counting state combines the corresponding relationship between the count value at the current moment and the first phase information corresponding to each stage of the ring oscillator to calibrate the first counting result. Among them, if the counting state is that the counting is in the last N phases, and the phase sampled at the current moment is in the first N phases, then the asynchronous Gray code counter at the current moment is in a state that has not flipped yet. The calibration adds one to the first counting result to obtain the first accurate code value. Thus, the correct quantization value is obtained, avoiding the problem of error codes caused by delay.

[0111] The specific steps for the check bit after sampling to combine with the count value at the current moment to determine the counting state of the asynchronous Gray code counter at the current moment include:

[0112] If the value of the check bit after sampling is 0 and the count value at the current moment is even, the counting state at the current moment is: the count is in the first N phases; if the value of the check bit after sampling is 1 and the count value at the current moment is even, the counting state at the current moment is: the count is in the last N phases; if the value of the check bit after sampling is 0 and the count value at the current moment is odd, the counting state at the current moment is: the count is in the last N phases; if the value of the check bit after sampling is 1 and the count value at the current moment is odd, the counting state at the current moment is: the count is in the first N phases. The following table can be used for intuitive understanding:

[0113] FLAG Count value Counter status 0 Even number Count is in the first N phases 1 Even number Count is in the last N phases 0 Odd number Count is in the last N phases 1 Odd number Count is in the first N phases

[0114] Combined with the structure of the self-calibration unit, the phase decoder PHASE DECODER decodes the first N phases. After passing through the OR gate OR, it is named the phase check bit signal PHASE_CHECK. If the current moment is in the first N phases, PHASE_CHECK is 1, otherwise it is 0.

[0115] Then the odd-even bit signal ODD-EVEN and the check bit signal FLAG after sampling pass through the exclusive-NOR gate AND to obtain the count check bit signal COUNTER_CHECK. If the count is in the first N phases, the count check bit signal COUNTER_CHECK is 1, otherwise it is 0.

[0116] Then, after the AND operation of the phase check bit signal PHASE_CHECK and the count check bit signal COUNTER_CHECK through the AND gate AND, the self-calibration bit signal Calibration is obtained. If the self-calibration bit signal Calibration is 1, the adder K-bit ADDER is enabled, and the sampled count value is incremented by one to obtain the calibrated counter code value, that is, the first accurate code value COUNTER_OUT<1:K>.

[0117] The column-level readout circuit proposed by the present invention can be Figure 5 shown in the overall structure diagram as Figure 5 In it, G M represents a transconductance module that receives the pixel voltage V IN and the reference voltage V REF , and converts them into two currents I CCO1 and I CCO2 They are respectively output to the current-controlled oscillators CCO1 and CCO2. Two Gray code counting units Gray Counter respectively calculate the count value K. Two phase sampling units Phase Sample respectively perform phase sampling on each stage of the ring oscillator of the current-controlled oscillator to obtain the sampling information N0. Two self-calibration units Self Calibration respectively perform self-calibration to obtain two accurate code values 2N*K + N0, and all are transmitted to the difference unit. The difference unit performs subtraction to obtain the final quantization result D OUT Output

[0118] The column-level readout circuit of the present invention adopts a time-domain quantization method. Based on the current-controlled oscillator, it converts voltage / current information into frequency information at the column level, integrates its frequency to obtain the phase, and quantizes the phase to complete analog-to-digital conversion. Since the area of the current-controlled oscillator is small, it can be implemented in a single-column column-level circuit, and thus the integration time can be further extended to improve the signal-to-noise ratio. The present invention multiplexes the source follower tubes of the infrared focal plane pixel-level circuit, and combines with the column-level circuit to form a pseudo-differential transconductance module, which converts the voltage difference between the pixel voltage signal transmitted from the pixel array and the reference voltage into a current difference, and then sends it into two current-controlled oscillators. Through fixed-time integration, the oscillation periods of the two current-controlled oscillators are respectively counted, the phase values are sampled, and the difference is calculated to complete quantization

[0119] Based on the above column-level readout circuit, an embodiment of the present invention further provides an infrared imager, which includes: a current detector and any one of the above column-level readout circuits

[0120] Through the above examples, the column-level readout circuit of the present invention adopts time-domain quantization of the voltage inside the pixel at the column level based on the current-controlled oscillator, and has a self-calibration function based on sampling errors, with technical advantages such as low power consumption, small occupied area, good monotonicity, and high signal-to-noise ratio, and has high practicability

[0121] It should be noted that in this article, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitations, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including that element

[0122] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the spirit of the present invention and the scope protected by the claims. All of these are within the protection scope of the present invention.< / m> < / n>

Claims

1. A column-level readout circuit, characterized in that The column-level readout circuit includes: a transconductance module, a first current-controlled oscillator, a second current-controlled oscillator, a first Gray code counting unit, a second Gray code counting unit, a first phase sampling unit, a second phase sampling unit, a first self-calibration unit, a second self-calibration unit, and a difference unit; The first current-controlled oscillator and the second current-controlled oscillator have the same structure and function, the first Gray code counting unit and the second Gray code counting unit have the same structure and function, the first phase sampling unit and the second phase sampling unit have the same structure and function, and the first self-calibration unit and the second self-calibration unit have the same structure and function; The transconductance module receives the pixel voltage and the reference voltage from the pixel array, generates a first current and a second current, and outputs the first current to the first current-controlled oscillator and the second current to the second current-controlled oscillator; For the first current-controlled oscillator: receive the first current, generate a first pulse output, and transmit the first pulse output to the first Gray code counting unit; For the first Gray code counting unit: perform an operation on the first pulse output to obtain a first counting result and transmit it to the first self-calibration unit; For the first phase sampling unit: sample the phase of each stage of the ring oscillator in the first current-controlled oscillator to obtain first phase information and transmit it to the first self-calibration unit; For the first self-calibration unit: based on the first phase information, calibrate the first counting result to obtain a first accurate code value and transmit it to the difference unit; The difference unit subtracts the second accurate code value from the second self-calibration unit from the first accurate code value and outputs the difference result as a quantization result outside the chip.

2. The column-level readout circuit according to claim 1, characterized in that, The transconductance module converts the voltage difference between the pixel voltage and the reference voltage into the first current and the second current with a current difference.

3. The column-level readout circuit according to claim 2, characterized in that The transconductance module includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a resistor; The first MOS transistor and the second MOS transistor are respectively two input pair transistors of the transconductance module. The gate of the first MOS transistor receives the pixel voltage, and the gate of the second MOS transistor receives the reference voltage; The fifth MOS transistor and the sixth MOS transistor are respectively connected to a current source to provide two current biases. The gates of the fifth MOS transistor and the sixth MOS transistor both receive a first bias voltage; The sixth MOS transistor, the second MOS transistor, and the fourth MOS transistor are connected in series in sequence. One end of the resistor is connected to the series connection point of the sixth MOS transistor and the second MOS transistor, and the other end of the resistor is connected to the pixel array; The third MOS transistor and the fourth MOS transistor are common-gate transistors, which are used to isolate the influence of the first fluid-controlled oscillator and the second fluid-controlled oscillator on the two input pair transistors. The third MOS transistor and the fourth MOS transistor respectively output the first current and the second current to the first fluid-controlled oscillator and the second fluid-controlled oscillator. The gates of the third MOS transistor and the fourth MOS transistor both receive a second bias voltage.

4. The column-level readout circuit according to claim 1, characterized in that Each stage of the ring oscillator includes two output terminals; the first phase sampling unit includes: multiple groups of SAFF flip-flops, a parity bit flip-flop, and a count value flip-flop; Each group of SAFF flip-flops includes: two SAFF flip-flops. The two SAFF flip-flops respectively sample the phases of the two output terminals of each stage of the ring oscillator. Each SAFF flip-flop uses an external Sample signal as an enable signal and performs phase sampling when the Sample signal is valid; The signal output by each SAFF flip-flop is transmitted to a phase decoder, so that the phase decoder decodes it into the first phase information corresponding to each stage of the ring oscillator; The parity bit flip-flop and the count value flip-flop are both SAFF flip-flops; The parity bit flip-flop samples the parity bit in the first Gray code counting unit, obtains the sampled parity bit signal and transmits it to the first self-calibration unit. The parity bit flip-flop uses the Sample signal as an enable signal and samples the parity bit in the first Gray code counting unit when the Sample signal is valid; The count value flip-flop samples the first counting result, obtains the binary code value and the parity signal corresponding to the first counting result and transmits them to the first self-calibration unit. The count value flip-flop uses the Sample signal as an enable signal and samples the first counting result when the Sample signal is valid.

5. The column-level readout circuit according to claim 4, wherein, The first self-calibration unit includes: an OR gate, an exclusive NOR gate, an AND gate, and an adder; The OR gate receives the first phase information corresponding to each stage of the ring oscillator and outputs a phase check bit signal to the AND gate; The exclusive NOR gate receives the sampled parity bit signal and the parity signal and outputs a count check bit signal to the AND gate; The AND gate outputs a self-calibration bit signal to the adder, and the adder uses the self-calibration bit signal as an enable signal; The adder uses the binary code value corresponding to the first counting result and the power supply voltage as input signals, and the adder outputs the first accurate code value.

6. The column-level readout circuit according to claim 4, wherein The first Gray code counting unit includes: an asynchronous Gray code counter; The lowest bit of the asynchronous Gray code counter is used as the sampled parity bit, and the second lowest bit of the asynchronous Gray code counter is used as the lowest bit of the count value of the asynchronous Gray code counter. The function of the sampled parity bit is: as a 1 / 2 bit to judge the counting state of the asynchronous Gray code counter at the current moment. Among them, when the asynchronous Gray code counter is at the edge of a transition, the sampled parity bit is a definite value, and the counting state of the asynchronous Gray code counter at the current moment is judged by combining the count value at the current moment; The counting state calibrates the first counting result in combination with the corresponding relationship between the current count value and the first phase information corresponding to each stage of the ring oscillator. Among them, if the counting state is that the counting is in the last N phases, and the phase sampling at the current moment samples the first N phases, then the asynchronous Gray code counter at the current moment is in a state where it has not flipped yet, and the calibration adds one to the first counting result to obtain the first accurate code value.

7. The column-level readout circuit according to claim 6, wherein The specific steps for the post-sampling check bit to determine the counting state of the asynchronous Gray code counter at the current moment in combination with the current count value include: If the value of the post-sampling check bit is 0 and the count value at the current moment is even, then the counting state at the current moment is: the counting is in the first N phases; If the value of the post-sampling check bit is 1 and the count value at the current moment is even, then the counting state at the current moment is: the counting is in the last N phases; If the value of the post-sampling check bit is 0 and the count value at the current moment is odd, then the counting state at the current moment is: the counting is in the last N phases; If the value of the post-sampling check bit is 1 and the count value at the current moment is odd, then the counting state at the current moment is: the counting is in the first N phases.

8. The column-level readout circuit according to claim 6, wherein For any flow control oscillator, there is: The oscillation frequency J of the flow control oscillator CCO is modulated by the magnitude of the current I flowing into the flow control oscillator, i.e.: CCO ​ f CCO = K CCO I CCO I f0 where K CCO is the frequency modulation sensitivity of the current-controlled oscillator, and f0 represents the intercept when the current I CCO = 0. The current-controlled oscillator integrates the output phase information of each stage of the ring oscillator within the time T0 as follows: Among them is the initial phase of each stage of the ring oscillator, and the total integration phase during the integration process is obtained from the count value and phase value at the end of the oscillation of the current-controlled oscillator: Where N is the number of delay stages of the flow control oscillator, K is the count value of the asynchronous Gray code counter, and N0 is the remaining number of phase bits sampled by the phase sampling. is the quantized unit phase. is the unquantized residual phase. According to the charge conservation, the total integrated charge quantity is: I CCO ×T0 = (2N × K + N0) × Q u +Q ε where Q u is the average charge consumed when oscillating a phase and Q ε is the residual charge that is not quantized. By quantizing the total integrated phase within time T0, quantization of the input current is achieved in the time domain.

9. The column-level readout circuit according to claim 3, wherein it is provided that The overall transconductance of the transconductance module is G m , then there is: ΔI CCO -G m ×ΔV IN where Gm = 1 / R, R represents the resistance value of the resistor, and ΔV IN = V REF - V IN , V REF represents the voltage value of the reference voltage, and V IN represents the voltage value of the pixel voltage. Then, the current difference I CCO1，2 between the first current and the second current generated by the transconductance module is expressed as: I CCO1，2 = I0 ± ΔI CCO Among them, I0 represents the current value provided by the current source, and ΔI CCO represents the current value flowing through the resistor.

10. An infrared imager, characterized in that, The infrared imager includes: a current detector and a column-level readout circuit according to any one of claims 1-9.

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