Dual-mode flash-sar adc conversion circuit and method

Abstract

The application relates to a dual-mode FLASH-SAR ADC conversion circuit and method, the circuit comprising a FLASH ADC module, a SAR ADC module, a clock control module and an encoding module. In reference mode one, the FLASH ADC module is a single-end structure, the FLASH ADC module samples the voltage division of a first reference voltage in a conversion stage, the positive and negative ends of the FLASH ADC module are connected with the voltage division of the first reference voltage and an input signal respectively in a sampling stage, and all the sampling capacitors in the SAR ADC module sample the input signal. In reference mode two, the FLASH ADC module is a differential capacitor structure, the FLASH ADC module samples the voltage division of a second reference voltage in a conversion stage, the positive and negative ends of the FLASH ADC module are connected with the second reference voltage and the input signal respectively in a sampling stage, and half of the sampling capacitors in the SAR ADC module sample the input signal. The ADC circuit resources are greatly saved, and the application cost is saved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of analog-digital conversion circuit, and relates to a dual-mode FLASH-SAR ADC conversion circuit and method. BACKGROUND

[0002] Analog-digital converters can be divided into full-parallel (FLASH) ADC, pipeline ADC, successive approximation (SAR) ADC and oversampling ADC according to different structures and working principles, and ADCs with different structures have advantages in speed and power consumption, etc. The FLASH ADC has the advantages of simple structure, parallel processing of multiple data and relatively fast speed, but has the disadvantages of high power consumption, high mismatch and low precision, which makes it difficult to be applied to high-precision large-scale integrated circuits. The SAR ADC enters the field of vision due to the advantages of low voltage and low power consumption, but with the continuous progress of technology, it is difficult for the SAR ADC to meet the requirements of speed and precision at the same time.

[0003] In order to solve the above problems, the mixed structure ADC composed of FLASH ADC and SAR ADC combines the advantages of the two, which can realize faster speed and higher precision. However, in the process of implementing the application, the inventors found that most FLASH-SAR ADCs have only one working mode, which limits the use range of the ADC. In different occasions, different ADCs need to work together, and there is still a technical problem of large consumption of ADC circuit resources. SUMMARY

[0004] In view of the problems in the above-mentioned traditional method, the application provides a dual-mode FLASH-SAR ADC conversion circuit and a dual-mode FLASH-SAR ADC conversion method, which are more adaptable and can effectively save ADC circuit resources.

[0005] In order to achieve the above purpose, the embodiments of the application adopt the following technical solutions:

[0006] On the one hand, a FLASH-SAR ADC conversion circuit is provided, which comprises a FLASH ADC module, a SAR ADC module, a clock control module and an encoding module,

[0007] The input end of the encoding module is connected with the FLASH ADC module and the SAR ADC module respectively, the clock control module is connected with the FLASH ADC module and the SAR ADC module respectively, the FLASH ADC module is used for inputting an input signal and a mode selection signal, and the SAR ADC module is used for inputting the input signal and the mode selection signal; the mode selection signal is used for setting the working mode of the FLASH ADC module and the SAR ADC module as reference mode one or reference mode two;

[0008] In the reference mode one, the reference voltage of the circuit is the first reference voltage, the FLASH ADC module is a single-ended structure, the FLASH ADC module samples the voltage division of the first reference voltage in the conversion stage, the positive and negative terminals of the FLASH ADC module are connected to the voltage division of the first reference voltage and the input signal respectively in the sampling stage, and all the sampling capacitors in the SAR ADC module sample the input signal; wherein the first reference voltage is not more than the power supply voltage, and the voltage range of the input signal is [0, the first reference voltage];

[0009] In the reference mode two, the reference voltage of the circuit is the second reference voltage, the FLASH ADC module is a differential capacitor structure, the FLASH ADC module samples the voltage division of the second reference voltage in the conversion stage, the positive and negative terminals of the FLASH ADC module are connected to the second reference voltage and the input signal respectively in the sampling stage, and half of the sampling capacitors in the SAR ADC module sample the input signal; wherein the second reference voltage is not more than half of the power supply voltage, and the voltage range of the input signal is [0, 2 times the second reference voltage].

[0010] On the other hand, a dual-mode FLASH-SAR ADC conversion method is also provided, which is applied to a dual-mode FLASH-SAR ADC conversion circuit, and the method comprises:

[0011] When the input mode selection signal sets the dual-mode FLASH-SAR ADC conversion circuit to work in the reference mode one, the FLASH ADC module of the dual-mode FLASH-SAR ADC conversion circuit samples the voltage division of the first reference voltage in the conversion stage, the positive and negative terminals of the FLASH ADC module are connected to the voltage division of the first reference voltage and the input signal respectively in the sampling stage, and all the sampling capacitors in the SAR ADC module of the dual-mode FLASH-SAR ADC conversion circuit sample the input signal; wherein the first reference voltage is not more than the power supply voltage, and the voltage range of the input signal is [0, the first reference voltage];

[0012] When the input mode selection signal sets the dual-mode FLASH-SAR ADC conversion circuit to work in the reference mode two, the FLASH ADC module samples the voltage division of the second reference voltage in the conversion stage, the positive and negative terminals of the FLASH ADC module are connected to the second reference voltage and the input signal respectively in the sampling stage, and half of the sampling capacitors in the SAR ADC module sample the input signal; wherein the second reference voltage is not more than half of the power supply voltage, and the voltage range of the input signal is [0, 2 times the second reference voltage];

[0013] The conversion output result of the dual-mode FLASH-SAR ADC conversion circuit is obtained according to the conversion result of the FLASH ADC module and the conversion result of the SAR ADC module.

[0014] One of the above technical solutions has the following advantages and beneficial effects:

[0015] The dual-mode FLASH-SAR ADC conversion circuit and method described above, by adopting the dual-mode architecture composed of the FLASH ADC module, the SAR ADC module, the clock control module and the encoding module, simultaneously supports two working modes. When the mode selection signal selection circuit works in reference mode one, the circuit uses the first reference voltage input, the FLASH ADC module is a single-ended structure, the FLASH ADC module samples the voltage division of the first reference voltage in the conversion stage, the positive and negative terminals of the FLASH ADC module are connected to the voltage division of the first reference voltage and the input signal respectively in the sampling stage, and all the sampling capacitors of the SAR ADC module sample the input signal, thereby efficiently supporting the conversion work in the first reference voltage input scenario. When the mode selection signal selection circuit works in reference mode two, the circuit uses the second reference voltage input, the FLASH ADC module is a differential capacitor structure, the FLASH ADC module samples the voltage division of the second reference voltage in the conversion stage, the positive and negative terminals of the FLASH ADC module are connected to the second reference voltage and the input signal respectively in the sampling stage, and half of the sampling capacitors of the SAR ADC module sample the input signal, thereby also efficiently supporting the conversion work in the second reference voltage input scenario. In this way, the core circuit can be reused to support two working modes, to meet different requirements of different working occasions as much as possible, and the ADC circuit resources can be greatly saved, and the application cost can be saved. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 The architecture block diagram of the dual-mode FLASH-SAR ADC conversion circuit in one embodiment is shown in the figure.

[0018] Figure 2 The structure schematic diagram of the FLASH ADC mode one in one embodiment is shown in the figure.

[0019] Figure 3 The structure schematic diagram of the FLASH ADC mode two in one embodiment is shown in the figure.

[0020] Figure 4 Schematic diagram of a single comparator in a FLASH ADC in one embodiment;

[0021] Figure 5 Schematic diagram of a single comparator in a FLASH ADC in another embodiment;

[0022] Figure 6 Schematic diagram of a CDAC high sampling capacitor dual-mode sampling principle in a design example SAR ADC in one embodiment;

[0023] Figure 7 Schematic diagram of a design example SAR ADC structure in one embodiment;

[0024] Figure 8 Schematic diagram of a CDAC dual-mode sampling principle in a design example in one embodiment; (a) is a sampling principle of reference mode one, (b) is a sampling principle of reference mode two. DETAILED DESCRIPTION

[0025] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the present application.

[0026] It should be noted that the reference to "embodiments" herein means that the specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase is shown at various places in the specification does not necessarily mean the same embodiment, nor is it an independent or alternative embodiment to other embodiments.

[0027] Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations. It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element and integrated as a whole, or there can be a middle element. The terms "one end", "the other end" and similar expressions used herein are only for the purpose of illustration.

[0028] The embodiments of the present application will be described in detail below with reference to the drawings.

[0029] In one embodiment, the embodiment of the present application provides a dual-mode FLASH-SAR ADC conversion circuit, which comprises a FLASH ADC module, a SAR ADC module, a clock control module and an encoding module. The input end of the encoding module is connected with the FLASH ADC module and the SAR ADC module respectively, the clock control module is connected with the FLASH ADC module and the SAR ADC module respectively, the FLASH ADC module is used for connecting an input signal and a mode selection signal, the SAR ADC module is used for connecting the input signal and the mode selection signal; and the mode selection signal is used for setting the working mode of the FLASH ADC module and the SAR ADC module as reference mode one or reference mode two.

[0030] In the reference mode one, the reference voltage of the circuit is a first reference voltage, the FLASH ADC module is a single-end structure, the FLASH ADC module samples the voltage division of the first reference voltage in the conversion stage, the positive and negative ends of the FLASH ADC module are connected with the voltage division of the first reference voltage and the input signal respectively in the sampling stage, and all the sampling capacitors in the SAR ADC module sample the input signal; wherein the first reference voltage is not more than the power supply voltage, and the voltage range of the input signal is [0, the first reference voltage]. In the reference mode two, the reference voltage of the circuit is a second reference voltage, the FLASH ADC module is a differential capacitor structure, the FLASH ADC module samples the voltage division of the second reference voltage in the conversion stage, the positive and negative ends of the FLASH ADC module are connected with the second reference voltage and the input signal respectively in the sampling stage, and half of the sampling capacitors in the SAR ADC module sample the input signal; wherein the second reference voltage is not more than half of the power supply voltage, and the voltage range of the input signal is [0, 2 times the second reference voltage].

[0031] The dual-mode FLASH-SAR ADC conversion circuit adopts a dual-mode architecture composed of a FLASH ADC module, a SAR ADC module, a clock control module, and an encoding module, simultaneously supports two working modes, when the mode selection signal selection circuit works in reference mode one, the circuit uses a first reference voltage input, the FLASH ADC module is a single-ended structure, the FLASH ADC module samples the voltage division of the first reference voltage in the conversion stage, the positive and negative terminals of the FLASH ADC module are connected to the voltage division of the first reference voltage and the input signal respectively in the sampling stage, and all the sampling capacitors of the SAR ADC module sample the input signal, thereby efficiently supporting the conversion work in the first reference voltage input scenario. When the mode selection signal selection circuit works in reference mode two, the circuit uses a second reference voltage input, the FLASH ADC module is a differential capacitor structure, the FLASH ADC module samples the voltage division of the second reference voltage in the conversion stage, the positive and negative terminals of the FLASH ADC module are connected to the second reference voltage and the input signal respectively in the sampling stage, and half of the sampling capacitors of the SAR ADC module sample the input signal, thereby also efficiently supporting the conversion work in the second reference voltage input scenario. In this way, the core circuit can be reused to support two working modes, different requirements of different working occasions can be met as much as possible, the ADC circuit resources can be greatly saved, and the application cost can be saved.

[0032] It can be understood that the structural block diagram of the circuit is as shown in Figure 1 , wherein Vin is an input signal, the reference clock and the reference current are input externally, the mode selection signal is also input through an external register, different working modes are selected by inputting different mode selection signals. BUFFER is a buffer, FLASH_OUT is the output of the FLASH ADC module, SAR_OUT is the output of the SAR ADC module, DOUT is the output of the encoding module, and VCM is a common-mode voltage.

[0033] The reference voltage in reference mode one is VREF, the voltage range of the input signal Vin is 0-V REF , and V REF ≤VDD. V REF is the VREF value. VDD is the power voltage of the entire conversion circuit.

[0034] The reference voltage in reference mode two is Vref, the voltage range of the input signal Vin is 0-2*V ref , and Vref≤VDD / 2. V ref is the Vref value.

[0035] Specifically, for an N-bit FALSH-SAR ADC conversion circuit, the FALSH ADC module controls the conversion of high H bits, and the output result can be in the form of a temperature code or a binary code; the SAR ADC module controls the conversion of low L bits, and the output result is generally in the form of a binary code, and is output as an N-bit binary code after being encoded by the encoding module. N is a given number of bits, H+L=N.

[0036] The FLASH ADC module includes a resistor string voltage division circuit, a comparator circuit, a switched capacitor circuit, etc., compares the voltage of an input signal and the resistor string voltage division, and obtains a result, which is the output result of the FLASH ADC, as the high H bits of the ADC. A specific circuit can be as shown in reference mode one Figure 2 , or as shown in reference mode two Figure 3 . Among them, COMP is a comparator, Vout is a comparison output voltage, V The resistance string is divided to reference voltage, i = 1, 2, …, 31.

[0037] The FALSH ADC module works in single-ended structure, and the voltage range of the input signal is 0-V REF , so the input signal and the resistance string divided voltage can be directly compared, as shown in Figure 2 , and the output is the result in the form of temperature code.

[0038] In the second reference mode, the input range of the input signal Vin is 0-2*V ref , and the reference voltage is V ref , which cannot be directly compared with the resistance string divided voltage. The common method is to divide the input signal by 2, and then compare it with the resistance string divided voltage. Dividing the input signal by 2 is usually implemented by using a double-capacitor structure, and the charge loss in the process of dividing the input signal by 2 will cause errors and affect the comparison result. This process is complicated, requires many circuit resources, and for an H-bit FLASH ADC, the step of the resistance string divided voltage is , and dividing the input signal by 2 will reduce the signal power and degrade the signal-to-noise ratio of the ADC output.

[0039] Further, in the second reference mode, before the comparator of the FLASH ADC module compares and outputs, the FLASH ADC module subtracts the input signal from the reference voltage, and then sends the difference to the comparator of the FLASH ADC module for comparison and output.

[0040] Specifically, to solve the above problems, the present example also makes improvements, as shown in Figure 3 , in this second reference mode, the advantages of differential are integrated into the single-ended structure. First, the input signal is subtracted from the reference voltage to obtain , and the difference V X is in the range of- V ref ~ V ref , then the difference V X is compared with the resistance string divided voltage , and the same result as the above scheme is obtained. In this comparison process, the two capacitors are switched in differential form (i.e., the differential capacitor structure shown in Figure 3 ), which can suppress the influence of common-mode noise, and the step of the resistance string divided voltage is Compared with the traditional scheme, the step is larger, and it is easier to get the correct comparison result, and the design difficulty of the comparator is reduced; at the same time, the step is larger, and the probability of comparison error is reduced; the signal range of the comparator input is changed from 0- V ref to- V ref V ref , the input range is larger, the comparator speed is accelerated, and the signal-to-noise ratio (SNR) is improved. The above-mentioned reference mode design is also suitable for use in FLASH-SAR ADC with double-ended capacitor structure and full-differential structure.

[0041] In one embodiment, as Figure 4 shown, the comparator of the FLASH ADC module includes a comparator preamplifier stage PRE-COMP, a latch LATCH, an RS latch, a first pre-charge capacitor C1, a second pre-charge capacitor C3, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4.

[0042] The positive input end of the comparator preamplifier stage PRE-COMP is connected to one end of the first pre-charge capacitor C1, and the other end of the first pre-charge capacitor C1 is used to access the input signal Vin or connect the resistor string voltage dividing circuit. The negative input end of the comparator preamplifier stage PRE-COMP is connected to one end of the second pre-charge capacitor C3, and the other end of the second pre-charge capacitor C3 is used to access the reference voltage or connect the resistor string voltage dividing circuit. The positive output end of the comparator preamplifier stage PRE-COMP is connected to the positive input end of the latch through the third switch S3, and the negative output end of the comparator preamplifier stage PRE-COMP is connected to the negative input end of the latch through the fourth switch S4. The latch is connected in cascade with the RS latch. One end of the first switch S1 is connected to the positive input end of the comparator preamplifier stage PRE-COMP, and the other end of the first switch S1 is connected to the positive output end of the comparator preamplifier stage PRE-COMP. One end of the second switch S2 is connected to the negative input end of the comparator preamplifier stage PRE-COMP, and the other end of the second switch S2 is connected to the negative output end of the comparator preamplifier stage PRE-COMP.

[0043] Further, the embodiment provides a circuit design of a comparator module, which is a core circuit of a FLASH ADC module, which can efficiently support the above-mentioned working timing and also support multiple reference voltage input reference modes. As Figure 4 shown is a circuit structure design schematic diagram of a single comparator module in the FLASH ADC module, and other comparator structures can be the same as this.

[0044] ​Specifically, during the ADC sampling phase, the SAR ADC module samples the input signal Vin, while the first switch S1 and the second switch S2 are kept open, the third switch S3 and the fourth switch S4 are closed, the comparator pre-amplifier stage PRE-COMP compares and amplifies the input signal Vin, and then sends the output to the latch LATCH and the RS latch for processing in sequence. At the clock edge at the end of the sampling phase, the RS latch outputs the result as the conversion result of the FLASH ADC. When the first switch S1 and the second switch S2 are closed, a common-mode voltage is provided for the pre-charge capacitor. The switches connected to the terminals are used to realize switching control of different reference inputs.

[0045] After the ADC sampling is completed, the RS latch of the FLASH ADC module has given a quantized digital code (H bits), and a quantized voltage V Flash is obtained. residue = Vin-V Flash . The SAR ADC module performs fine quantization on the residual voltage V residue to obtain a low-bit digital code (N-H bits). After the conversion result of the FLASH ADC module is sent out, the comparator pre-amplifier stage PRE-COMP of the FLASH ADC module enters a reset phase during the time of fine quantization of the corresponding SAR ADC, and samples the reference voltage connected through the second pre-charge capacitor C3 to prepare for the next conversion.

[0046] Through the above circuit design of the comparator module, the above working timing can be efficiently supported with less circuit design amount, and the conversion efficiency is improved while the production cost of the converter chip is reduced.

[0047] In one embodiment, as shown in Figure 5 , the comparator of the FLASH ADC module further includes a first ground capacitor C2, a second ground capacitor C4, and branch switches SW1 to SW6. One end of the first ground capacitor C2 is connected to the positive input terminal of the comparator pre-amplifier stage PRE-COMP, and the other end of the first ground capacitor C2 is grounded. One end of the second ground capacitor C4 is connected to the negative input terminal of the comparator pre-amplifier stage PRE-COMP, and the other end of the second ground capacitor C4 is grounded. One end of the branch switch SW1 is connected to the other end of the first pre-charge capacitor C1, and the other end of the branch switch SW1 is used to connect the input signal Vin. One end of the branch switch SW2 is connected to the other end of the first pre-charge capacitor C1, and the other end of the branch switch SW2 is used to connect the positive resistor of the resistor string voltage dividing circuit.

[0048] One end of the branch switch SW3 is connected to the other end of the second pre-charge capacitor C3, the other end of the branch switch SW3 is used to access the reference voltage, one end of the branch switch SW4 is connected to the other end of the second pre-charge capacitor C3, the other end of the branch switch SW4 is used to connect the negative end resistor of the resistor string voltage division circuit, one end of the branch switch SW5 is connected to the other end of the second pre-charge capacitor C3, the other end of the branch switch SW5 is used to connect the positive end resistor of the resistor string voltage division circuit, one end of the branch switch SW6 is connected to the other end of the second pre-charge capacitor C3, and the other end of the branch switch SW6 is used to connect the positive end resistor of the resistor string voltage division circuit.

[0049] Further, in the embodiment, a first ground capacitor C2 and a second ground capacitor C4 are also arranged in the circuit of the comparator module of the FLASH ADC module, and branch switches SW1 to SW6 are arranged for each input, wherein the first ground capacitor C2 and the second ground capacitor C4 are used to reduce the common mode voltage change and reduce the adverse effect of the common mode voltage change on the operation of the comparator module; the switches on the access terminals in the formula are respectively expanded into corresponding branch switches SW. Figure 3 The branch switches SW1 to SW6 can accurately and efficiently access the input signal Vin, the reference voltage, and the resistor string voltage division of the reference voltage for the comparator module in different working stages, so as to support the comparison output work of the pre-amplifier stage PRE-COMP, the latch LATCH, and the RS latch.

[0050] Through the further optimization design of the circuit of the comparator module of the FLASH ADC module, the conversion performance of the FLASH ADC module can be further improved.

[0051] In one embodiment, the S AR ADC module is a segmented S AR ADC circuit. It can be understood that the S AR ADC module can also include a DAC module, a comparator module, and a S AR control logic module, etc. This paper mainly improves the S AR ADC architecture, that is, designs the DAC. The DAC module is divided into two parts, wherein the first part is a high-H-bit corresponding switch capacitor part, which is controlled by the FLASH conversion result to switch; the second part is a low-L-bit corresponding switch capacitor part, which is controlled by the S AR logic according to the comparison result of the comparator.

[0052] In one embodiment, the S AR ADC module is a non-segmented S AR ADC circuit. It can be understood that the DAC module circuit can be a traditional non-segmented structure, or a segmented structure (for example, but not limited to, two segments, three segments, or four segments). The circuit adopts a lower plate sampling, so the lower plate of the capacitor needs at least three switches for connecting the input voltage, the reference voltage, and the reference ground respectively. According to different sampling methods, the required switches and the voltage to be accessed by the lower plate can be adjusted.

[0053] In reference mode one, all sampling capacitors sample the input signal; further, the output form of the FLASH ADC module is a temperature code.

[0054] In reference mode two, the high-order capacitor is split as shown in Figure 6 , half of the sampling capacitors sample the input signal, and then the final result is obtained by successive approximation comparison in the SAR ADC switching mode.

[0055] The FLASH ADC output is a single-ended result, so the result of the FLASH ADC only needs to be given to the N-terminal CDAC of the SAR ADC, and the corresponding P-terminal high-order capacitor only needs to be kept at ground. Then, the low-order SAR ADC switches in a differential form, the advantages of differential structure are integrated into single-ended ADC, and the influence of common-mode noise on the result is suppressed.

[0056] The above is the architecture of the dual-mode FLASH-SAR ADC, which integrates the advantages of differential structure into single-ended structure, can obtain better performance, and improves the dynamic parameter indicators of the ADC.

[0057] In an embodiment, the SAR ADC module is a two-stage SAR ADC circuit with symmetric comparators at both ends. The circuit structure is simple and efficient, and the application cost is lower.

[0058] In an embodiment, the dual-mode FLASH-SAR ADC conversion circuit is a 12-bit FLASH-SAR ADC, a 14-bit FLASH-SAR ADC, or a 16-bit FLASH-SAR ADC, which has stronger applicability.

[0059] The skilled person in the art can also apply the above technical solutions to 13-bit FLASH-SAR ADC, 15-bit FLASH-SAR ADC, 10-bit FLASH-SAR ADC, or 11-bit FLASH-SAR ADC, etc. to support the above corresponding functions.

[0060] In an embodiment, an optional design application example is provided to better understand the above scheme. It should be noted that the example is only illustrative and not the only limitation of the above scheme in actual application. The skilled person can realize different design applications according to the design concept of the above scheme.

[0061] The design is a 12-bit single-ended dual-mode FLASH-SAR ADC conversion circuit, which supports two reference modes:

[0062] Reference mode one: the reference voltage is VREF, the voltage range of the input signal is 0-VREF, and VREF≤VDD is required.

[0063] Reference mode two: the reference voltage is Vref, the voltage range of the input signal is 0-2•Vref, and Vref≤VDD / 2 is required.

[0064] This example adopts a combination mode of dividing a 12-bit ADC into high 5 bits (H=5) and low 7 bits (L=7), that is, a FLASH ADC module is responsible for coarse quantization of the high five-bit part, and a SAR ADC module is responsible for fine quantization of the low seven-bit part.

[0065] The FLASH ADC module mainly includes a resistor string voltage division circuit composed of 32 resistors and 31 comparator circuits. The core circuit of a single FLASH ADC module is as shown in Figure 4

[0066] Among them, four capacitors are the same (four capacitors are used in this example, according to the FLASH ADC module structure diagram in the disclosure content, two capacitors (C1 and C3) can realize the function of the FLASH ADC, and the two ground capacitors (C2 and C4) added in this example are to reduce the common-mode voltage of the comparator input), and the capacitance is assumed to be C. VREF (Vref) is the reference voltage, V and V <n>The voltage division of VREF by a resistor string of 32 resistors is expressed by the general formula:

[0067] ;

[0068] And P and N satisfy: The working principle of the FLASH ADC module is different under different reference modes, and the two cases are as follows:

[0069] 1. In reference mode one, the reference voltage is VREF, and the input signal range is 0-VREF:

[0070] In this reference mode, the negative input end (N end) 302 of the comparator participates in the circuit work, and 301 is disconnected. That is, the circuit negative input end (N end) of the comparator module of the FLASH ADC module only needs to be connected to V< / n> Sampling is enough, V <n>SW3 and SW4 corresponding to VREF branch are in the normally closed state.

[0071] In the FLASH ADC reset phase, SW2 and SW6 are high, the corresponding potential is connected to the lower plate of the capacitor; at this time, S1 is high, the input and output terminals of the comparator pre-amplifier stage PRE-COMP are short-circuited, and a common-mode voltage is provided for the pre-charging capacitor and At this time, the charges stored in the P and N terminals of the comparator pre-amplifier stage PRE-COMP are respectively:

[0072] ;

[0073] ;

[0074] wherein, C 1 represents the capacitance value of the capacitor C1, C 2 represents the capacitance value of the capacitor C2, C 3 represents the capacitance value of the capacitor C3, C 4 represents the capacitance value of the capacitor C4. In the FLASH ADC conversion phase, SW1 and SW5 are high, the sampling input Vin and the voltage V< / n> Access to the lower plate of the capacitor, at this time S1 is low, the input and output of the comparator pre-amplifier stage PRE-COMP disconnects and compares the differential signal input to the input of the pre-amplifier stage PRE-COMP. At this time, the P and N terminals of the comparator pre-amplifier stage PRE-COMP store charges respectively:

[0075] ;

[0076] ;

[0077] wherein, V in represents the value of Vin. According to the law of conservation of charge, , , the above formula is obtained:

[0078] ;

[0079] ;

[0080] The comparator is a full differential structure, so , subtracting the two equations and simplifying gives:

[0081] ;

[0082] According to the above derived relationship, the input voltage Vin and the reference voltage V the size relationship. When the voltage is greater than the reference voltage V , the comparator output is 1, and vice versa when the input voltage Vin is less than the reference voltage V , the comparator output is 0.

[0083] 2. In reference mode two, the reference voltage is Vref, the input range is 0-2•Vref, and Vref≤VDD / 2 is required:

[0084] In this reference mode, the negative input end (N end) 301 of the comparator module of the FLASH ADC module participates in the circuit work, and time-divisionally compares Vref and V <n>Sampling, 302 off, i.e. V< / n> Branch corresponding switch SW5 and SW6 are in the normally closed state.

[0085] In the FLASH ADC reset phase, SW2 and SW4 are high, the corresponding potential is connected to the lower plate of the capacitor; S1 is high, the input and output of the comparator preamplifier PRE-COMP are shorted, providing a common-mode voltage for the pre-charged capacitor At this time, the P-end and N-end capacitors store charges respectively:

[0086] ;

[0087] ;

[0088] In the FLASH ADC conversion phase, SW1 and SW3 are high, the external input Vin and the reference voltage Vref are connected to the lower plate of the capacitor, S1 is low, the input and output of the comparator preamplifier PRE-COMP are disconnected to compare and amplify the differential signal. At this time, the P-end and N-end capacitors store charges respectively:

[0089] ;

[0090] ;

[0091] Where, V ref Vref represents the value of Vref. According to the law of conservation of charge, and , together with the above formula:

[0092] ;

[0093] ;

[0094] The comparator is a full differential structure, so , subtracting the two equations and simplifying:

[0095] ;

[0096] In reference mode two, FLASH ADC is in full differential mode, and the input voltage Vin of ADC is in the range of 0~2• V ref , the "Vref" obtained by moving down Vref in FLASH ADC is used as the new input voltage, and the corresponding range is- V ref ~ V ref , the new reference voltage in FLASH ADC is ​​", the corresponding range is also- V ref V ref In this comparison process, the two end capacitors are switched in differential form, which can suppress the influence of common-mode noise, and the resistance string voltage division step is Compared with the traditional scheme, the step is larger, and it is easier to get the correct comparison result, which reduces the design difficulty of the comparator; at the same time, the step is larger, the thermal noise is smaller, and the probability of comparison error is reduced; the signal range of the comparator input is changed from 0-V ref to- V ref V ref The input range is larger, the comparator speed is faster, and the signal-to-noise ratio (SNR) is improved.

[0097] According to the differential idea, the comparator compares the new input voltage " with the new reference voltage ". When , it indicates that the new input voltage is greater than the new reference voltage, and the comparator output is 1. Conversely, when , it indicates that the new input voltage is less than the new reference voltage, and the comparator output is 0. Here, the differential idea is integrated into the single-ended structure, and the output result is obtained by using the differential comparator, which can suppress the common-mode noise to obtain better performance.

[0098] The two reference modes will be closed when the sampling clock falls along the switch S2, and the comparator pre-amplification level result will be sent to the LATCH level for further comparison and amplification, and finally sent to the RS latch to latch, which remains unchanged throughout the SAR ADC fine quantization process.

[0099] The SAR ADC module is responsible for low seven-bit quantization and supports the conversion of the above two reference modes, and the structure diagram can be as shown in Figure 7 . The SAR ADC module has a two-section structure, and the P end and the N end are symmetrical. The high-bit capacitor array 402 has a total of 8 bits (7+1, one bit is a redundant bit capacitor 404), which are 64C, 32C, 16C, 8C, 4C, 4C, 2C and C, including a redundant bit capacitor 404 with a value of 4C. The low-bit capacitor array 401 has 6 bits (5+1), which are 16C, 8C, 4C, 2C, C and C, and the last C is a terminal compensation capacitor and does not participate in conversion. The bridge capacitor 405 is .

[0100] ​​The SAR ADC module adopts high 6-bit 402 lower plate sampling, and is a single-ended sampling structure, that is, only the N end (the negative input end of the comparator) of the 402 DAC corresponds to the sampling capacitor pair to sample the input signal; the P end (the positive input end of the comparator) of the 402 DAC corresponds to the sampling capacitor lower plate to ground (GND) during sampling. The remaining capacitors 401 are connected to the common-mode voltage VCM at the lower plate during sampling and do not participate in sampling. The compensation capacitor 406 is connected to the common-mode voltage VCM at the lower plate.

[0101] This DAC also supports the previous two reference modes, and the sampling capacitor part 402 needs to be designed more specially, as shown in Figure 5 , each bit of capacitor is evenly divided into two parts, and is recombined into two groups, one group of capacitor lower plate sampling switch (switch controlling the connection between capacitor lower plate and input) is controlled by switch Switch1, and the other group of sampling switch is controlled by switch Switch2, and in the group controlled by switch Switch2, a control ground switch needs to be added to each capacitor corresponding switch.

[0102] In reference mode one, all capacitors sample the input signal, that is, switches Switch1 and Switch2 are high (high level is effective), at this time the sampling capacitor has 128C, and the sampled charge quantity is 128C• V in , the input voltage range is 0~VREF.

[0103] In reference mode two, switch Switch1 is high and switch Switch2 is low, only the group of capacitors corresponding to switch Switch1 is sampled, and the group of capacitors corresponding to switch Switch2 is grounded during sampling, and the ground control switch GND_CLK is turned on, all are grounded and do not participate in sampling, at this time the sampling capacitor is only 64C, and the sampled charge quantity is only 64C•Vin, in the subsequent ADC quantization process, all 128C capacitors in 402 participate, and the charge quantity sampled by the sampling capacitor 64C capacitor will be distributed to 128C, and the equivalent sampled voltage U=Q / C=64C• V in / 128C=0.5• V in . Because the subsequent ADC quantization takes Vref as the reference, the input voltage range can be realized as 0~2• V ref , the sampling schematic diagrams of the two modes are shown in Figure 8 , wherein (a) is the sampling of reference mode one, and (b) is the sampling of reference mode two.

[0104] Figure 7 The middle and high five bits correspond to the capacitor 403. In order to correspond to the output of the FLASH ADC module, all capacitors are divided into 62 groups with 2C as a basic unit, in which a group controlled by the switch Switch 1 has 31 capacitors, and a group controlled by the switch Switch 2 has 31 capacitors. The conversion control signals of the two groups are controlled by the 31-bit temperature code given by the FALSH ADC module (that is, one temperature code controls the capacitor of 4C).

[0105] In the SAR ADC quantization stage, the temperature code output by the FLASH ADC module is converted into five digital codes D13, D12, D11, D10 and D9 for convenience. The design is single-ended sampling, and the P terminal is sampled and held to ground. Therefore, the output result of the FLASH ADC module only controls the N terminal high five bits of the CDAC in the SAR ADC module, and the P terminal high five bits of the CDAC is always kept to ground.

[0106] According to the charge conservation, the voltage difference at the output end of the DAC is derived as follows for each switch switching of the low bits in the reference mode one:

[0107] ;

[0108] ;

[0109] wherein k = 4-j, k = 2, 3…9. j is the DAC output voltage in the jth conversion. When the comparison result of the j-1 bit is 0, the minus is used in the above formula; j When the comparison result of the j-1 bit is 1, the plus is used in the above formula. According to the comparison result of the j-1 bit, the next bit is switched in the same way as above until the quantization of the low bits is completed. j According to the charge conservation, the voltage difference at the output end of the DAC is derived as follows for each switch switching of the low bits in the reference mode two: j j ;

[0110] ;

[0111] wherein k = 4-j, = 2, 3…9.

[0112] is the DAC output voltage in the jth conversion. When the comparison result of the j-1 bit is 0, the minus is used in the above formula; When the comparison result of the j-1 bit is 1, the plus is used in the above formula. According to the comparison result of the j-1 bit, the next bit is switched in the same way as above until the quantization of the low bits is completed.

[0113] j j j j ​​​​​​​The comparison result is used to control the next bit to switch in the same way as the above until the low bit result is quantized completely. In the sampling of the second reference mode, only half of the sampling capacitors are used for sampling, but in the conversion, the FLASH ADC output digital code controls all the capacitors to convert.

[0114] The above is the example design of the embodiment according to the above invention content. For the rest of the non-core modules of the FLASH-SAR ADC, the traditional circuit is designed to realize the function of the FLASH-SAR ADC, which is not described in detail in this embodiment.

[0115] In one embodiment, the embodiment of the application also provides a FLASH-SAR ADC conversion method applied to a dual-mode FLASH-SAR ADC conversion circuit, which comprises steps S12 to S16:

[0116] S12, when the input mode selection signal sets the dual-mode FLASH-SAR ADC conversion circuit to work in the first reference mode, the FLASH ADC module of the dual-mode FLASH-SAR ADC conversion circuit samples the voltage division of the first reference voltage in the conversion stage, the positive and negative terminals of the FLASH ADC module are connected to the voltage division of the first reference voltage and the input signal respectively in the sampling stage, and all the sampling capacitors in the SAR ADC module of the dual-mode FLASH-SAR ADC conversion circuit sample the input signal; wherein the first reference voltage does not exceed the power supply voltage, and the voltage range of the input signal is [0, the first reference voltage];

[0117] S14, when the input mode selection signal sets the dual-mode FLASH-SAR ADC conversion circuit to work in the second reference mode, the FLASH ADC module samples the voltage division of the second reference voltage in the conversion stage, the positive and negative terminals of the FLASH ADC module are connected to the second reference voltage and the input signal respectively in the sampling stage, and half of the sampling capacitors in the SAR ADC module sample the input signal; wherein the second reference voltage does not exceed half of the power supply voltage, and the voltage range of the input signal is [0, 2 times the second reference voltage];

[0118] S16, the conversion output result of the dual-mode FLASH-SAR ADC conversion circuit is obtained according to the conversion result of the FLASH ADC module and the conversion result of the SAR ADC module.

[0119] It can be understood that the explanation and description of each step in this embodiment can be understood in the same way as the corresponding part of the above dual-mode FLASH-SAR ADC conversion circuit embodiment, which is not repeated here.

[0120] The FLASH-SAR ADC conversion method described above, through the dual-mode architecture composed of the FLASH ADC module, the SAR ADC module, the clock control module and the encoding module, simultaneously supports two working modes. When the mode selection signal selection circuit works in reference mode one, the circuit uses the first reference voltage input, the FLASH ADC module is a single-ended structure, the FLASH ADC module samples the voltage division of the first reference voltage in the conversion stage, the positive and negative terminals of the FLASH ADC module are connected to the voltage division of the first reference voltage and the input signal respectively in the sampling stage, and all the sampling capacitors of the SAR ADC module sample the input signal, thereby efficiently supporting the conversion work in the first reference voltage input scenario. When the mode selection signal selection circuit works in reference mode two, the circuit uses the second reference voltage input, the FLASH ADC module is a differential capacitor structure, the FLASH ADC module samples the voltage division of the second reference voltage in the conversion stage, the positive and negative terminals of the FLASH ADC module are connected to the second reference voltage and the input signal respectively in the sampling stage, and half of the sampling capacitors of the SAR ADC module sample the input signal, thereby also efficiently supporting the conversion work in the second reference voltage input scenario. In this way, the core circuit can be reused to support two working modes, to meet different needs of different working occasions as much as possible, to greatly save ADC circuit resources, and to save application cost.

[0121] It can be understood that the explanation and description of the embodiments of the FLASH-SAR ADC conversion method described above can be understood in the same way by referring to the corresponding explanation and description in the embodiments of the dual-mode FLASH-SAR ADC conversion circuit described above, and will not be repeated here. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application. The above embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of variations and improvements can be made, which all belong to the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims. ​

Claims

1. A dual-mode FLASH-SAR ADC conversion circuit, characterized in that, It includes a FLASH ADC module, a SAR ADC module, a clock control module, and an encoding module; The input terminals of the encoding module are connected to the FLASH ADC module and the SAR ADC module, respectively. The clock control module is connected to the FLASH ADC module and the SAR ADC module, respectively. The FLASH ADC module is used to receive the input signal and the mode selection signal, and the SAR ADC module is used to receive the input signal and the mode selection signal. The mode selection signal is used to set the operating mode of the FLASH ADC module and the SAR ADC module to reference mode one or reference mode two. In the reference mode, the circuit reference voltage is a first reference voltage. The FLASH ADC module has a single-ended structure. During the conversion phase, the FLASH ADC module samples the voltage divider of the first reference voltage. During the sampling phase, the positive and negative terminals of the FLASH ADC module are respectively connected to the voltage divider of the first reference voltage and the input signal. All sampling capacitors in the SARADC module sample the input signal. The first reference voltage does not exceed the power supply voltage, and the voltage range of the input signal is [0, first reference voltage]. In the second reference mode, the reference voltage of the circuit is the second reference voltage. The FLASH ADC module has a differential capacitor structure. During the conversion phase, the FLASH ADC module samples the voltage division of the second reference voltage. During the sampling phase, the positive and negative terminals of the FLASH ADC module are respectively connected to the second reference voltage and the input signal. Half of the sampling capacitor in the SARADC module samples the input signal. The second reference voltage does not exceed half of the power supply voltage, and the voltage range of the input signal is [0, 2 times the second reference voltage].

2. The dual-mode FLASH-SAR ADC conversion circuit according to claim 1, characterized in that, The comparator of the FLASH ADC module includes a comparator preamplifier stage, a latch, an RS latch, a first precharge capacitor, a second precharge capacitor, a first switch, a second switch, a third switch, and a fourth switch. The positive input terminal of the comparator pre-amplifier stage is connected to one end of the first pre-charge capacitor, and the other end of the first pre-charge capacitor is used to connect to the input signal or to the resistor series voltage divider circuit. The negative input terminal of the comparator pre-amplifier stage is connected to one end of the second pre-charge capacitor, and the other end of the second pre-charge capacitor is used to connect to the reference voltage or to the resistor series voltage divider circuit. The positive output of the comparator preamplifier stage is connected to the positive input of the latch via the third switch, and the negative output of the comparator preamplifier stage is connected to the negative input of the latch via the fourth switch. The latch is cascaded with the RS latch. One end of the first switch is connected to the positive input terminal of the comparator preamplifier stage, and the other end of the first switch is connected to the positive output terminal of the comparator preamplifier stage; one end of the second switch is connected to the negative input terminal of the comparator preamplifier stage, and the other end of the second switch is connected to the negative output terminal of the comparator preamplifier stage.

3. The dual-mode FLASH-SAR ADC conversion circuit according to claim 2, characterized in that, The comparator of the FLASH ADC module also includes a first ground capacitor, a second ground capacitor, and branch switches SW1 to SW6. One end of the first ground capacitor is connected to the positive input terminal of the comparator pre-amplification stage, and the other end of the first ground capacitor is grounded. One end of the second ground capacitor is connected to the negative input terminal of the comparator pre-amplification stage, and the other end of the second ground capacitor is grounded. One end of the branch switch SW1 is connected to the other end of the first pre-charge capacitor, and the other end of the branch switch SW1 is used to connect to the input signal. One end of the branch switch SW2 is connected to the other end of the first pre-charge capacitor, and the other end of the branch switch SW2 is used to connect to the positive terminal resistor of the resistor series voltage divider circuit. One end of branch switch SW3 is connected to the other end of the second pre-charge capacitor, and the other end of branch switch SW3 is used to connect to the reference voltage. One end of branch switch SW4 is connected to the other end of the second pre-charge capacitor, and the other end of branch switch SW4 is used to connect to the negative resistor of the resistor series voltage divider circuit. One end of branch switch SW5 is connected to the other end of the second pre-charge capacitor, and the other end of branch switch SW5 is used to connect to the positive resistor of the resistor series voltage divider circuit. One end of branch switch SW6 is connected to the other end of the second pre-charge capacitor, and the other end of branch switch SW6 is used to connect to the positive resistor of the resistor series voltage divider circuit.

4. The dual-mode FLASH-SAR ADC conversion circuit according to claim 2 or 3, characterized in that, In the second reference mode, before the comparator of the FLASH ADC module outputs the comparison, the FLASH ADC module calculates the difference between the input signal and the reference voltage, and then divides the difference by a resistor series of the reference voltage and sends it to the comparator of the FLASH ADC module for comparison and output.

5. The dual-mode FLASH-SAR ADC conversion circuit according to claim 1, characterized in that, The SAR ADC module is a segmented SAR ADC circuit.

6. The dual-mode FLASH-SAR ADC conversion circuit according to claim 1, characterized in that, The SAR ADC module is a non-segmented SAR ADC circuit.

7. The dual-mode FLASH-SAR ADC conversion circuit according to claim 1, characterized in that, The output of the FLASH ADC module is in the form of temperature codes.

8. The dual-mode FLASH-SAR ADC conversion circuit according to claim 5, characterized in that, The SAR ADC module is a two-stage SAR ADC circuit with symmetrical ends to the comparator.

9. The dual-mode FLASH-SAR ADC conversion circuit according to claim 1, characterized in that, The dual-mode FLASH-SAR ADC conversion circuit is a 12-bit FLASH-SAR ADC, a 14-bit FLASH-SAR ADC, or a 16-bit FLASH-SAR ADC.

10. A dual-mode FLASH-SAR ADC conversion method, characterized in that, The method, applied to the dual-mode FLASH-SAR ADC conversion circuit according to any one of claims 1 to 9, comprises: When the input mode selection signal sets the dual-mode FLASH-SAR ADC conversion circuit to operate in reference mode one, during the conversion phase, the FLASH ADC module of the dual-mode FLASH-SAR ADC conversion circuit samples the voltage divider of the first reference voltage. During the sampling phase, the positive and negative terminals of the FLASH ADC module are respectively connected to the voltage divider of the first reference voltage and the input signal. All the sampling capacitors in the SAR ADC module of the dual-mode FLASH-SAR ADC conversion circuit sample the input signal. The first reference voltage does not exceed the power supply voltage, and the voltage range of the input signal is [0, first reference voltage]. When the input mode selection signal sets the dual-mode FLASH-SAR ADC conversion circuit to operate in reference mode two, during the conversion phase, the FLASH ADC module samples the voltage divider of the second reference voltage. During the sampling phase, the positive and negative terminals of the FLASH ADC module are respectively connected to the second reference voltage and the input signal. Half of the sampling capacitor in the SAR ADC module samples the input signal. The second reference voltage does not exceed half of the power supply voltage, and the voltage range of the input signal is [0, 2 times the second reference voltage]. The conversion output of the dual-mode FLASH-SAR ADC conversion circuit is obtained based on the conversion results of the FLASH ADC module and the SAR ADC module.

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