An ADC driver interface circuit

Abstract

The application relates to the technical field of integrated circuits, and discloses an ADC driving interface circuit, which comprises a programmable gain amplification circuit, an RC filter circuit and a front-end sampling circuit, the amplification circuit comprises a voltage drop control current controlled by a voltage drop control switch; the RC filter circuit comprises a first resistor, a second resistor and a first capacitor, one end of the first resistor and one end of the second resistor are respectively connected to the voltage drop control current, the first capacitor is coupled between the other end of the first resistor and the other end of the second resistor, and the first resistor and the second resistor are respectively connected to the voltage drop control switch in parallel; the front-end sampling circuit comprises a second capacitor and a third capacitor, one end of the second capacitor is coupled to the other end of the first resistor through a first-stage delay control switch, and one end of the third capacitor is coupled to the other end of the second resistor through the first-stage delay control switch. When the application improves the voltage drop rate of the ADC during ADC sampling, the linearity of a large signal is optimized, and a good compromise between noise and linearity can be achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to an ADC driving interface circuit. BACKGROUND

[0002] In signal chain communication or measurement system applications, both sensitivity and linearity of input signal are required to be very high. Specifically, when an external input is a small signal, the sensitivity of a receive (RX) channel should be high, and when the external input is a large signal, the linearity of the receive channel should be good. Usually, in order to meet the requirement of high precision, a low-noise programmable gain amplifier (PGA) is integrated before a high-precision analog-to-digital converter (ADC) in the receive channel. The PGA is required to be programmable in gain, provide a high dynamic range, and have small noise, and when it is connected with the ADC, it also needs to provide the driving capability required by the ADC. If the PGA is directly connected with the ADC, the PGA is required to have very high noise and linearity. It is difficult to make a good compromise among power consumption, area, noise, and linearity in the design of the receive channel. SUMMARY

[0003] The present application aims to provide an ADC driving interface circuit, which provides an interface circuit of a PGA and an ADC, and takes into account both low-noise design for a small signal and high-linearity design for a large signal. The ADC driving interface circuit can not only meet the noise and linearity of the entire RX channel, but also greatly reduces the design requirement of the PGA, saves the area, power consumption, and design complexity of the entire channel, and thus well balances the sensitivity and linearity in sensor or signal chain communication applications.

[0004] The present application discloses an ADC driving interface circuit, comprising:

[0005] a programmable gain amplification circuit, the programmable gain amplification circuit comprising a slew rate control current controlled by a slew rate control switch;

[0006] an RC filter circuit, the RC filter circuit comprising a first resistor, a second resistor, and a first capacitor, one end of the first resistor and one end of the second resistor being connected with the slew rate control current, the first capacitor being coupled between the other end of the first resistor and the other end of the second resistor, the first resistor and the second resistor being connected with the slew rate control switch in parallel at both ends, respectively;

[0007] a front-end sampling circuit, the front-end sampling circuit comprising a second capacitor and a third capacitor, wherein one end of the second capacitor is coupled to the other end of the first resistor via a first stage delay control switch, the other end of the second capacitor is coupled to a second stage delay control switch, and both ends of the second capacitor are coupled to a common voltage via a second stage control switch and a first stage control switch, respectively, wherein one end of the third capacitor is coupled to the other end of the second resistor via a first stage delay control switch, the other end of the third capacitor is coupled to a second stage delay control switch, and both ends of the second capacitor are coupled to a common voltage via a second stage control switch and a first stage control switch, respectively.

[0008] In one preferred embodiment, the programmable gain amplification circuit further comprises:

[0009] an operational amplifier, the operational amplifier receiving a differential positive input voltage and a differential negative input voltage, respectively;

[0010] a floating bias, the floating bias connected to an output of the operational amplifier and dynamically adjusting the positive input voltage and the negative input voltage;

[0011] first to fourth PMOS transistors, sources of the first to fourth PMOS transistors are connected to a voltage source, gates of the first and third PMOS transistors are connected to the adjusted positive input voltage, gates of the second and fourth PMOS transistors are connected to the adjusted positive input voltage via the slew control switch, drains of the first and second PMOS transistors are connected to the first resistor, and drains of the third and fourth PMOS transistors are connected to the second resistor;

[0012] first to fourth NMOS transistors, sources of the first to fourth NMOS transistors are connected to a ground, gates of the first and third NMOS transistors are connected to the adjusted negative input voltage, gates of the second and fourth NMOS transistors are connected to the adjusted negative input voltage via the slew control switch, drains of the first to fourth NMOS transistors are connected to drains of the first to fourth PMOS transistors, respectively, drains of the first and second NMOS transistors are connected to the first resistor, and drains of the third and fourth NMOS transistors are connected to the second resistor.

[0013] In one preferred embodiment, the opening and closing of the slew control switch is controlled by a slew control signal, the opening and closing of the first stage control switch is controlled by a first stage control signal, the opening and closing of the second stage control switch is controlled by a second stage control signal, and the first stage control signal is enabled prior to the second stage control signal.

[0014] In a preferred embodiment, the slew control signal is enabled at the same time as the first stage control signal.

[0015] In a preferred embodiment, the slew control signal is enabled for a shorter time than the first stage control signal.

[0016] In a preferred embodiment, the opening and closing of the first stage delay control switch is controlled by a first stage delay control signal, which is enabled at the same time as the first stage control signal, and is turned off later than the first stage control signal.

[0017] In a preferred embodiment, the opening and closing of the second stage delay control switch is controlled by a second stage delay control signal, which is enabled at the same time as the second stage control signal, and is turned off later than the second stage control signal.

[0018] Compared with the prior art, the present application has at least the following beneficial effects:

[0019] 1) An additional slew enhancement switch is added to the output OPAMP of the RC filter network and the PGA, which improves the slew rate of the ADC during sampling, thereby optimizing the linearity of large signals.

[0020] 2) After the slew enhancement switch is added to the RC filter network, high linearity can be achieved without increasing the power consumption of the PGA under large signals, thereby ensuring low power consumption design of the entire channel.

[0021] 3) The circuit of the present application is simple and has small hardware overhead, and can well compromise between noise and linearity.

[0022] A large number of technical features are described in the specification of the present application, which are distributed in various technical solutions. If all possible combinations of technical features (i.e. technical solutions) of the present application are listed, the specification will be too long. In order to avoid this problem, each technical feature disclosed in the above summary of the present application, each technical feature disclosed in the following various embodiments and examples, and each technical feature disclosed in the drawings can be freely combined to form various new technical solutions (which should be considered as having been described in the specification), unless such combination of technical features is technically infeasible. For example, features A+B+C are disclosed in one example, features A+B+D+E are disclosed in another example, features C and D are equivalent technical means that play the same role and can only be used in one, and feature E can be combined with feature C in technology. Therefore, the solution of A+B+C+D should not be considered as having been described because it is technically infeasible, and the solution of A+B+C+E should be considered as having been described. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a structural schematic diagram of an ADC driving interface circuit according to an embodiment of the present application.

[0024] Figure 2 is a more detailed structural schematic diagram of an ADC driving interface circuit according to an embodiment of the present application.

[0025] Figure 3 is a schematic diagram of the control timing of an ADC driving interface circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] In the following description, many technical details are presented in order to make the reader better understand the present application. However, those skilled in the art can understand that the technical solutions claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments.

[0027] The following briefly describes some innovative points of the embodiments of the present application:

[0028] The application provides an ADC driving interface circuit with high linearity. In a signal chain path, a programmable gain amplifier is integrated to improve the signal sensitivity and resolution of the signal chain path. When the programmable gain amplifier is connected with an ADC, two problems need to be solved, one is low noise, and the other is linearity of a large signal. Many solutions currently seen add an RC filter circuit to reduce the power consumption and requirements of the PGA OPAMP, but under a large signal input, the addition of the RC filter leads to slow setting time and damaged linearity. In order to compensate, current needs to be increased, which does not achieve the purpose of reducing power consumption. The interface circuit provided by the application is placed between the PGA and the ADC circuit, which can reduce the noise of the entire path, optimize the linearity of the large signal of the path, and reduce the bandwidth and power consumption requirements of the PGA OPAMP.

[0029] In order to make the purpose, technical scheme and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0030] One embodiment of the present application relates to an ADC driving interface circuit, which has a structure as shown in Figure 1 The programmable gain amplification circuit 100 includes a slew rate control current I_slew controlled by a slew rate control switch. The RC filter circuit 200 includes a first resistor R1, a second resistor R2 and a first capacitor C1, one end of the first resistor R1 and one end of the second resistor R2 are connected to the slew rate control current I_slew, the first capacitor C1 is coupled between the other end of the first resistor R1 and the other end of the second resistor R2, and the first resistor R1 and the second resistor R2 are connected in parallel with the slew rate control switch. The front-end sampling circuit 200 includes a second capacitor C2A and a third capacitor C2B, wherein one end of the second capacitor C2A is coupled to the other end of the first resistor R1 via a first stage delay control switch, the other end of the second capacitor C2A is coupled to a second stage delay control switch, and the two ends of the second capacitor C2A are coupled to a common voltage VCM via a second stage control switch and a first stage control switch, respectively, wherein one end of the third capacitor C2B is coupled to the other end of the second resistor R2 via a first stage delay control switch, the other end of the third capacitor C2B is coupled to a second stage delay control switch, and the two ends of the third capacitor C2B are coupled to a common voltage VCM via a second stage control switch and a first stage control switch, respectively.

[0031] In one embodiment, the opening and closing of the slew control switch is controlled by a slew control signal Ph1_slew, the opening and closing of the first stage control switch is controlled by a first stage control signal Ph1, the opening and closing of the second stage control switch is controlled by a second stage control signal Ph2, the opening and closing of the first stage delay control switch is controlled by a first stage delay control signal Ph1_d, and the opening and closing of the second stage delay control switch is controlled by a second stage delay control signal Ph2_d. In one embodiment, the first stage control signal Ph1 is enabled prior to the second stage control signal Ph2. In one embodiment, the slew control signal Ph1_slew is enabled at the same time as the first stage control signal Ph1. In one embodiment, the slew control signal Ph1_slew is enabled for a shorter time than the first stage control signal Ph1. For example, the slew control signal Ph1_slew can be a short pulse signal.

[0032] In one embodiment, the first stage delay control signal Ph1_d is enabled at the same time as the first stage control signal Ph1, and is turned off later than the first stage control signal Ph1. In one embodiment, the second stage delay control signal Ph2_d is enabled at the same time as the second stage control signal Ph2, and is turned off later than the second stage control signal Ph2.

[0033] Reference is made to Figure 1 As shown, when ph1 and ph1_d are enabled, the capacitor C1 charges the capacitors C2A and C2B. When ph2 and ph2_d are enabled, the voltage across the capacitors C2A and C2B is detected by the subsequent circuit.

[0034] In one embodiment, reference is made to Figure 2 As shown, the programmable gain amplification circuit 100 further comprises an operational amplifier (OPAMP) 101, a floating bias 102, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor NP1, a second NMOS transistor NP2, a third NMOS transistor NP3, and a fourth NMOS transistor NP4.

[0035] The operational amplifier 101 receives differential positive input voltage Vinp and negative input voltage Vinn, respectively. The floating bias 102 is connected to the output of the operational amplifier 101 and dynamically adjusts the positive input voltage Vinp and negative input voltage Vinn, and outputs and adjusts the positive input voltage Vfp and negative input voltage Vfn. Since the operational amplifier 101 is a class AB output, the gates of PMOS and NMOS are dynamically adjusted according to the output load, and the floating bias 102 can achieve this effect. If the gate is fixed, the output current is fixed, not floating.

[0036] The sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are connected to a voltage source, the gates of the first PMOS transistor MP1 and the third PMOS transistor MP3 are connected to the adjusted positive input voltage, the gates of the second PMOS transistor MP2 and the fourth PMOS transistor MP4 are connected to the adjusted positive input voltage Vfp via the slew control switch, the drains of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the first resistor R1, and the drains of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the second resistor R2. The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor NP1, the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor NP2, the drain of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor NP3, and the drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor NP4.

[0037] The sources of the first NMOS transistor NP1, the second NMOS transistor NP2, the third NMOS transistor NP3, and the fourth NMOS transistor NP4 are connected to a ground, the gates of the first NMOS transistor NP1 and the third NMOS transistor NP2 are connected to the adjusted negative input voltage, the gates of the second NMOS transistor NP2 and the fourth NMOS transistor NP4 are connected to the adjusted negative input voltage Vfn via the slew control switch, the drains of the first NMOS transistor NP1 and the second NMOS transistor NP2 are connected to the first resistor R2, and the drains of the third NMOS transistor NP3 and the fourth NMOS transistor NP4 are connected to the second resistor R2.

[0038] It should be understood that the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the first NMOS transistor NP1, the second NMOS transistor NP2, the third NMOS transistor NP3, and the fourth NMOS transistor NP4 constitute Figure 1 When the control signal ph1_slew is enabled, the second PMOS transistor MP2 and the fourth PMOS transistor MP4, as well as the second NMOS transistor NP2 and the fourth NMOS transistor NP4 are turned on, thereby increasing the output voltages Vop and Von and the current of the output stage of the OPAMP, thereby controlling the slew control current I_slew according to ph1_slew.

[0039] This application can greatly alleviate the slew rate and current requirements for the PGA OPAMP by adding a switch control signal ph1_slew. Figure 2 and Figure 3 As shown, ph1_slew simultaneously controls the output stage and RC network of the PGA's OPAMP. When the ADC enters sampling mode, the ADC sampling current is provided by two sources: one is provided by the first capacitor C1, which provides charge to the ADC sampling network; the other is provided by the PGA's OPAMP. Because the voltage across the second capacitor C2A and the third capacitor C2B cannot change suddenly when the ADC switches from integration mode to sampling mode, the Vxp and Vxn signals experience a relatively large jump, which causes the output of the PGA's OPAMP to be pulled low. The PGA's OPAMP enters a slew state, at which point ph1_slew is set high and held for a very short time. During this short ph1_slew time, the PGA's internal OPAMP increases current at the output stage, improving the slew rate. Simultaneously, the switch connecting resistors R1 and R2 in the RC filter network closes simultaneously, bypassing the filter resistors R1 and R2. Because the ph1_slew switch's on-resistance is very low, the time constant for the PGA OPAMP's current to charge capacitors C1, C2A, and C2B also decreases.

[0040] The ph1_slew of the present application controls the output current of the OPAMP and the time constant of the filter network at the same time, so the output of the PGA can be quickly established and enter the small signal establishment stage as soon as possible. When the ph1_slew is low, the switch is off, at which time the PGA enters the normal working mode and the RC filter network returns to normal. The RC filter network provides a low-pass filter for the signal channel, and since the first capacitor C1 continuously provides charge to the sampling network, the bandwidth requirement of the PGA buffer is also reduced, and the PGA buffer can still work under small current, saving the power consumption of the entire channel.

[0041] The pulse width of the ph1_slew needs to be compromised in linearity and noise performance. The ph1_slew switch time is long, which is good for linearity, has sufficient time to establish, but the filtering time is relatively small, and the noise performance is poor. While the ph1_slew time is too short, the linearity optimization is limited.

[0042] It should be noted that the relationship terms such as first and second in the application file of the present patent are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "including one" does not exclude the presence of another identical element in the process, method, article or equipment including the element. In the application file of the present patent, if it is mentioned that a certain action is performed according to a certain element, it means that the action is performed at least according to the element, which includes two cases: the action is performed only according to the element, and the action is performed according to the element and other elements. The expressions of multiple, multiple times, multiple varieties, etc. include 2, 2 times, 2 varieties and 2 or more, 2 times or more, 2 or more varieties.

[0043] The term "coupled to" and its derivatives can be used herein. "Coupled" can mean that two or more elements are in direct physical or electrical contact. However, "coupled" can also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other, and can mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0044] This specification includes combinations of the various embodiments described herein. References to an embodiment, or embodiments, e.g., "the embodiment" or "some embodiments" or "one embodiment" or "an exemplary embodiment", do not necessarily refer to the same embodiment; however, such embodiments are not mutually exclusive, unless otherwise indicated. It should be noted that the use of "or" herein is meant to encompass both a exclusive or and an inclusive or, unless otherwise indicated or required by the context.

[0045] All documents mentioned in this specification are hereby incorporated by reference in their entirety to provide additional description of the application. In addition, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes and can not have been selected to delineate or circumscribe the patent rights of the application. Accordingly, the scope of the application is in accordance with the claims taken in their broadest interpretation.

Claims

1. An ADC driver interface circuit, characterized in that: include: a programmable gain amplifier circuit, the programmable gain amplifier circuit including a slew control current controlled by a slew control switch; an RC filter circuit, the RC filter circuit comprising a first resistor, a second resistor, and a first capacitor, one end of the first resistor and one end of the second resistor being respectively connected to the slew control current, the first capacitor being coupled between the other ends of the first resistor and the other ends of the second resistor, and a slew control switch being connected in parallel across the first resistor and the second resistor; A front-end sampling circuit includes a second capacitor and a third capacitor, wherein one end of the second capacitor is coupled to the other end of the first resistor via a first-stage delay control switch, the other end of the second capacitor is coupled to the second-stage delay control switch, and both ends of the second capacitor are coupled to a common voltage via the second-stage control switch and the first-stage control switch, respectively; wherein one end of the third capacitor is coupled to the other end of the second resistor via the first-stage delay control switch, the other end of the third capacitor is coupled to the second-stage delay control switch, and both ends of the second capacitor are coupled to the common voltage via the second-stage control switch and the first-stage control switch, respectively.

2. The ADC driver interface circuit according to claim 1, wherein: The programmable gain amplifier circuit further includes: an operational amplifier, wherein the operational amplifier receives a differential positive input voltage and a differential negative input voltage respectively; a floating bias connected to the output of the operational amplifier and dynamically adjusting the positive input voltage and the negative input voltage; first to fourth PMOS transistors, wherein sources of the first to fourth PMOS transistors are connected to a voltage source, gates of the first and third PMOS transistors are connected to the regulated positive input voltage, gates of the second and fourth PMOS transistors are connected to the regulated positive input voltage via the slew control switch, drains of the first and second PMOS transistors are connected to the first resistor, and drains of the third and fourth PMOS transistors are connected to the second resistor; First to fourth NMOS transistors, sources of the first to fourth NMOS transistors are connected to the ground, gates of the first and third NMOS transistors are connected to the adjusted negative input voltage, gates of the second and fourth NMOS transistors are connected to the adjusted negative input voltage via the slew control switch, drains of the first to fourth NMOS transistors are respectively connected to the drains of the first to fourth PMOS transistors, drains of the first and second NMOS transistors are connected to the first resistor, and drains of the third and fourth NMOS transistors are connected to the second resistor.

3. The ADC driving interface circuit according to claim 1, wherein: The opening and closing of the slew control switch is controlled by a slew control signal, the opening and closing of the first-stage control switch is controlled by a first-stage control signal, and the opening and closing of the second-stage control switch is controlled by a second-stage control signal, and the first-stage control signal is enabled before the second-stage control signal.

4. The ADC driving interface circuit according to claim 3, wherein: The slew control signal is enabled at the same time as the first stage control signal is enabled.

5. The ADC driving interface circuit according to claim 4, characterized in that: The time during which the slew control signal is enabled is shorter than the time during which the first stage control signal is enabled.

6. The ADC driving interface circuit according to claim 3, characterized in that: The opening and closing of the first-stage delay control switch is controlled by a first-stage delay control signal, which is enabled simultaneously with the first-stage control signal and is closed later than the first-stage control signal.

7. The ADC driving interface circuit according to claim 3, characterized in that: The opening and closing of the second-stage delay control switch is controlled by a second-stage delay control signal, which is enabled simultaneously with the second-stage control signal and is turned off later than the second-stage control signal.

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