Image Processing System and Its Method

Abstract

An embodiment of the present application provides an image processing system and a method thereof. The image processing system includes a processing module, an interconnect bus, and N target chips, where N is a positive integer; the processing module is configured to obtain an image to be processed; the processing module is further configured to, through the interconnect bus, call M target chips to perform image processing on the image to be processed according to the image processing sequence of the image to be processed, so as to obtain a target image; the M target chips are at least part of the N target chips, and M is a positive integer less than or equal to N.

Description

Technical Field

[0001] This application belongs to the field of communication technologies, and particularly relates to an image processing system and a method thereof. Background Art

[0002] With the development of electronic technologies, more users use electronic devices to shoot videos and photos. At the same time, with the improvement of user requirements, the requirements for the image processing capabilities of electronic devices are getting higher and higher. In related technologies, by adding external chips or integrating more chips, the image processing capabilities of electronic devices are improved. Specifically, the application processor (AP) in the electronic device is set to be communicatively connected to multiple newly added chips, and the newly added chips are used to process images.

[0003] However, the above-mentioned newly added chips communicate based on the Mobile Industry Processor Interface (MIPI) protocol. This results in that during the process of processing images by multiple chips, the multiple chips can only process images in sequence according to their positional relationships with the application processor. That is to say, the processing order of images among the multiple chips is fixed, which leads to great limitations in the image processing method, thereby reducing the image processing efficiency and making it difficult to improve the image processing capabilities of electronic devices. Summary of the Invention

[0004] An object of embodiments of this application is an image processing system and a method thereof, which can solve the problem of low image processing efficiency.

[0005] In a first aspect, embodiments of this application provide an image processing system, which includes a processing module and N target chips, where N is a positive integer;

[0006] The processing module is configured to obtain an image to be processed;

[0007] The processing module is further configured to, through an interconnect bus, call M of the target chips to perform image processing on the image to be processed according to the image processing order corresponding to the image to be processed, so as to obtain a target image; the M target chips are at least part of the N target chips, and M is a positive integer less than or equal to N.

[0008] In a second aspect, embodiments of this application provide an image processing method, which is applied to an image processing system. The image processing system includes a processing module and N target chips, where N is a positive integer. The method includes:

[0009] The processing module obtains an image to be processed;

[0010] The processing module calls M target chips to perform image processing on the to-be-processed image through an interconnection bus according to the image processing sequence corresponding to the to-be-processed image, so as to obtain a target image; the M target chips are at least part of the N target chips, and M is a positive integer less than or equal to N.

[0011] In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor, a memory, and a program or instruction stored in the memory and executable on the processor. When the program or instruction is executed by the processor, the steps of the method described in the second aspect are implemented.

[0012] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the second aspect are implemented.

[0013] In a fifth aspect, an embodiment of the present application provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the method described in the second aspect.

[0014] In a sixth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the method described in the second aspect.

[0015] The image processing system in the embodiment of the present application includes a processing module and N target chips, where N is a positive integer; the processing module is used to obtain a to-be-processed image; the processing module is further used to call M target chips to perform image processing on the to-be-processed image through an interconnection bus according to the image processing sequence corresponding to the to-be-processed image, so as to obtain a target image; the M target chips are at least part of the N target chips, and M is a positive integer less than or equal to N. In the embodiment of the present application, the processing module can call the target chips in sequence through the interconnection bus. That is to say, in the embodiment of the present application, multiple target chips are called according to the image processing sequence corresponding to the to-be-processed image, rather than calling multiple target chips based on the positional relationship of the target chips, thereby improving the image processing efficiency and further improving the image processing ability of the electronic device. Description of the Drawings

[0016] Figure 1 is a schematic diagram of an image processing system in the related art;

[0017] Figure 2 is one of the schematic diagrams of the image processing system provided by the embodiment of the present application;

[0018] Figure 3 is a flowchart of the image processing method provided by the embodiment of the present application;

[0019] Figure 4 It is the second schematic diagram of the image processing system provided by the embodiment of the present application;

[0020] Figure 5 It is the schematic diagram of the data processing system provided by the embodiment of the present application;

[0021] Figure 6 It is the structural diagram of the electronic device provided by the embodiment of the present application;

[0022] Figure 7 It is the hardware structural diagram of the electronic device provided by the embodiment of the present application. Specific embodiments

[0023] Next, the technical solutions in the embodiments of the present application will be clearly described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0024] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally indicates an "or" relationship between the associated objects before and after.

[0025] Next, the image processing method provided by the embodiment of the present application will be described in detail in conjunction with the accompanying drawings, through specific embodiments and their application scenarios.

[0026] In the prior art, please refer to Figure 1 , such as Figure 1 shown, the image processing system includes a processing module and three target chips, namely Figure 1 chip 1, chip 2, and chip 3 in , the processing module includes an application processor and a memory, the application processor is communicatively connected to each target chip, chip 1 is also communicatively connected to chip 2, and chip 2 is also communicatively connected to chip 3.

[0027] It should be understood that the above target chips can be chips integrated in the image processing system or chips externally connected to the image processing system. The above target chips can also be of other quantities. Each target chip performs different image processing functions on the image. For example, Chip 1 performs noise reduction processing, Chip 2 performs AI acceleration processing, and Chip 3 performs digital signal processing.

[0028] During the process of using Figure 1 the shown image processing system to perform image processing on the image to be processed, multiple target chips can only be called in sequence to perform image processing on the image to be processed according to the positional relationship between these 3 target chips. For example, first call Chip 2 to perform image processing on the image to be processed, and then call Chip 3 to perform image processing on the image processed by Chip 2. However, in some scenarios, it may be required to first perform digital signal processing on the image to be processed and then perform AI acceleration processing on the image to be processed. In this implementation scenario, Figure 1 the shown image processing system cannot call Chip 3 first and then call Chip 2, which results in great limitations in the image processing method, thereby reducing the image processing efficiency and making it difficult to improve the image processing ability of the electronic device.

[0029] To solve the above existing technical problems, an embodiment of the present application provides an image processing method. This image processing method is applied to an image processing system. Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of the image processing system provided by the embodiment of the present application.

[0030] As Figure 2 shown, the image processing system includes a processing module and 4 target chips. The processing module includes an application processor and a memory. The above 4 target chips include Chip 1, Chip 2, Chip 3, and Chip 4. Among them, the processing module is communicatively connected to each chip through an interconnect bus, and the chips are independent of each other. The above Chip 1 is a Neural-network Processing Units (NPU), the above Chip 2 is a Graphics Processing Unit (GPU), the above Chip 3 is a preImage Signal Processing (pre-ISP) chip, and the above Chip 4 is a postImage Signal Processing (post-ISP) chip. It should be understood that the above chips can be chips integrated in the image processing system or chips externally connected to the image processing system.

[0031] Among them, the network processor is used to process the data of the image, and the above data processing includes but is not limited to packet processing, protocol analysis, and routing lookup. The graphics processor is used to perform graphic processing on the image, and the above graphic processing includes but is not limited to image construction and image rendering. The above front-end image signal processing chip is used to perform front-end image signal processing on the image, and the above front-end image signal processing includes but is not limited to noise reduction processing and demosaicing processing. The above back-end image signal processing chip is used to perform back-end image signal processing on the image, and the above back-end image signal processing includes but is not limited to super-resolution processing and high dynamic range processing.

[0032] It should be understood that the number of target chips in the image processing system is N, and N is a positive integer. For the purpose of clearly elaborating the technical solution in the embodiments of the present application, the number of target chips is set to 4. In other optional embodiments, the number of target chips can be other numbers. It should be understood that the above target chips can also be other types of image processing chips. Figure 2 The target chips shown are only one example and do not specifically limit the type of target chips.

[0033] It should be noted that in Figure 2 the shown image processing system, the entire image processing system adopts a tree structure. The processing module can be regarded as the root node in the tree structure, and through the processing module, data storage, data interconnection, and access between each target chip in the image processing system are realized; each target chip can be regarded as a node in the tree structure, and the node is connected to the root node through an interconnection bus. Among them, all nodes in the tree structure share the storage resources in the memory. In other words, in Figure 2 the shown image processing system, the target chips do not need to be configured with dedicated external storage resources, thereby saving the cost of the image processing system.

[0034] It should be noted that in Figure 2 the shown image processing system, the target chips access the memory through the interconnection bus, and the application processor calls the target chips through the interconnection bus. The target chips can indirectly access other target chips through the application processor, that is, the target chips send an access request to the application processor through the interconnection bus, and the application processor sends the access request to another target chip through the interconnection bus, thereby realizing the indirect access between two target chips.

[0035] Please refer to Figure 3 , Figure 3 which is the flowchart of the image processing method provided by the embodiments of the present application. The image processing method provided by the embodiments of the present application includes the following steps:

[0036] S301, the processing module obtains the image to be processed.

[0037] The image to be processed described above can be a captured image or an image received for image processing.

[0038] S302. The processing module calls M target chips through an interconnect bus to perform image processing on the image to be processed according to the image processing sequence of the image to be processed, and obtains a target image.

[0039] It should be understood that the image processing sequence of the image to be processed can be determined according to the data content of the image to be processed.

[0040] For example, when the image to be processed is an original image, it is necessary to first use the NPU to perform data processing on the image to be processed, use the GPU to perform graphics processing on the image to be processed, then use the pre-ISP to perform front-end image signal processing on the image to be processed, and finally use the post-ISP to perform back-end image signal processing on the image to be processed to obtain a target image.

[0041] When the image to be processed is an image that has undergone graphics processing, it is necessary to first use the pre-ISP to perform front-end image signal processing on the image to be processed, and then use the post-ISP to perform back-end image signal processing on the image to be processed to obtain a target image.

[0042] Optionally, the image processing sequence of the above-mentioned image to be processed can also be set by the user customarily.

[0043] In this step, the processing module calls M target chips through an interconnect bus to perform image processing on the image to be processed according to the image processing sequence corresponding to the image to be processed, and obtains a target image. Among them, the target chip is a chip integrated in the image processing system or an externally attached chip, M target chips are at least part of the N target chips, and M is a positive integer less than or equal to N.

[0044] For the convenience of understanding, the following is combined with Figure 2 for an example:

[0045] When the image to be processed is an original image, it is necessary to perform data processing, graphics processing, front-end image signal processing, and back-end image signal processing on the image to be processed in sequence. In Figure 2In the illustrated image processing system, the application processor sends the image to be processed to Chip 1 via the interconnect bus. Chip 1 processes the data of the image to be processed and sends the processed image back to the application processor via the interconnect bus. The application processor sends the processed image to Chip 2 via the interconnect bus. Chip 2 performs graphic processing on the image and sends the graphically processed image back to the application processor via the interconnect bus. The application processor sends the image after image processing to Chip 3 via the interconnect bus. Chip 3 performs front-end image signal processing on the image and sends the image after front-end image signal processing back to the application processor via the interconnect bus. The application processor sends the image after front-end image signal processing to Chip 4 via the interconnect bus. Chip 4 performs back-end image signal processing on the image and sends the image after back-end image signal processing back to the application processor via the interconnect bus to obtain the target image.

[0046] In the embodiment of the present application, the processing module can sequentially call the target chips via the interconnect bus. That is to say, in the embodiment of the present application, multiple target chips are called according to the image processing sequence of the image to be processed, rather than based on the positional relationship of the target chips, thereby improving the image processing efficiency and further improving the image processing ability of the electronic device.

[0047] Optionally, the processing module calls M target chips to perform image processing on the image to be processed via the interconnect bus according to the image processing sequence of the image to be processed, and obtaining the target image includes:

[0048] The processing module calls one of the M target chips to perform image processing on the image to be processed via the interconnect bus according to the image processing sequence of the image to be processed each time.

[0049] When the processing module calls the first chip among the M target chips via the interconnect bus, the image sent back by the first chip via the interconnect bus is determined as the target image, and the first chip is the last chip in the call sequence among the M target chips.

[0050] In this embodiment, after the first chip performs image processing on the image to be processed, the processed image is sent back to the processing module via the interconnect bus, and the processing module determines the image sent back by the first chip as the target image.

[0051] Exemplarily, in Figure 2In the illustrated image processing system, if the image to be processed is an image after graphics processing, the image processing sequence corresponding to the image to be processed is front-end image signal processing and back-end image signal processing. The application processor sends the image to be processed to Chip 3 through the interconnect bus. Chip 3 performs front-end image signal processing on the image to be processed and sends the processed image back to the application processor through the interconnect bus. The application processor sends the image after front-end image signal processing to Chip 4 through the interconnect bus. Chip 4 is the last chip in the call sequence, that is, the first chip. Chip 4 performs back-end image signal processing on the image and sends the processed image back to the application processor through the interconnect bus to obtain the target image.

[0052] Optionally, the processing module, through the interconnect bus, according to the image processing sequence of the image to be processed, each time calls one of the M target chips to perform image processing on the image to be processed, including:

[0053] In one call process, the processing module sends the image to be processed and a first call instruction through the interconnect bus; the first call instruction is determined based on the address information of the second chip to be called, and the second chip is one of the M target chips;

[0054] The second chip performs image processing on the image to be processed and sends the processed image back to the processing module through the interconnect bus.

[0055] An optional implementation is that the image processing system can be built based on the Peripheral Component Interconnect Express (PCIE) protocol. Please refer to Figure 4 , the image processing system built based on the PCIE protocol is as Figure 4 shown. Figure 4 In the illustrated image processing system, the application processor is communicatively connected to the memory, the application processor is communicatively connected to the interconnect bus, the interconnect bus is communicatively connected to each target chip, and the target chips are independent of each other. Figure 4 The illustrated image processing system includes 3 target chips. It should be understood that the above target chips can also be other numbers, and this is only an example here.

[0056] In the image processing system built based on the PCIE protocol, each node, that is, the target chip, can be abstracted as a memory node. Data interaction and read / write access between the chip, the application processor, and the memory are performed in the memory manner, which can achieve seamless switching between the target chip, the application processor, and the memory and improve the deployment efficiency of the target chip.

[0057] Among them, the interconnect bus can be understood as a PCIE bus, which has a pcie switch state and a bypass state. When the interconnect bus is in the pcie switch state, the target chip communicates with the application processor through the interconnect bus; when the interconnect bus is in the bypass state, the target chip directly communicates with the application processor, and the interconnect bus does not process the data sent by the chip or the data sent by the application processor.

[0058] In Figure 4 the illustrated image processing system, the application processor and each target chip have PCIE data interfaces. As Figure 4 shown, the application processor has a PCIE-RC interface, and the target chip has a PCIE-EP interface. As Figure 4 shown, the target chip, the application processor, and the memory have corresponding address information, and each address information occupies 2 bit positions. The address information corresponding to chip 1 is from address A to address B, the address information corresponding to chip 2 is from address C to address D, the address information corresponding to chip 3 is from address E to address F, the address information corresponding to the application processor is from address H to address I, and the address information corresponding to the memory is from address M to address N.

[0059] In other embodiments, the image processing system can also be constructed based on the Rapid IO protocol.

[0060] In this embodiment, the processing module sends the image to be processed and the first call instruction through the interconnect bus. Among them, the above first call instruction is determined based on the address information of the second chip to be called, that is, the first call instruction includes the address information of the second chip to be called. The image to be processed is sent to the second chip to be called indicated by the first call instruction through the interconnect bus. The second chip performs image processing on the image to be processed and sends the processed image back to the processing module through the interconnect bus, thereby realizing a process of calling a chip once.

[0061] In this embodiment, the processing module in the image processing system calls the second chip based on the address information of the second chip, thereby abstracting the second chip as address information. By adding or deleting address information in the image processing system, the second chip can be added or deleted, improving the deployment efficiency of the chip.

[0062] Optionally, the processing module calls one of the M target chips through the interconnect bus to perform image processing on the image to be processed according to the image processing order of the image to be processed, including:

[0063] The processing module sends a second calling instruction through the interconnection bus; the second calling instruction is determined based on address information of a third chip to be called, and the third chip is one of the M target chips;

[0064] The third chip reads the image to be processed stored in the processing module through the interconnection bus in response to the second calling instruction;

[0065] The third chip performs image processing on the image to be processed, and transmits the processed image back to the processing module through the interconnection bus.

[0066] In this embodiment, the processing module sends a second call instruction through the interconnection bus, wherein the second call instruction is determined based on the address information of the called third chip, that is, the second call instruction includes the address information of the called third chip. The second call instruction is sent to the called third chip through the interconnection bus, and the third chip reads the image to be processed stored in the processing module through the interconnection bus, performs image processing on the image to be processed, and transmits the processed image back to the processing module through the interconnection bus, thereby realizing a process of calling the third chip once.

[0067] In this embodiment, in addition to processing the image sent by the processing module, the target chip can also read the image to be processed stored in the processing module through the interconnection bus and perform image processing on the image to be processed stored in the processing module, thereby enriching the image processing method.

[0068] In other embodiments, Figure 2 and Figure 4 The architecture of the image processing system shown can also be applied to the process of data processing. Figure 5 , Figure 5 What is shown is a data processing system, the architecture of which is consistent with the above-mentioned image processing system. The data processing system includes an application processor, an interconnection bus, a memory, and multiple external processors. The application processor is communicatively connected to the memory, and the application processor is communicatively connected to each external processor through the interconnection bus. The above-mentioned external processors can be abstracted as nodes.

[0069] When the amount of data to be processed is large, the application processor can call the external processor through the interconnection bus to process the data. Each external processor processes part of the data to be processed in the form of a data queue, thereby reducing the time for processing the data to be processed and improving the efficiency of data processing.

[0070] The image processing system provided by the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0071] As shown Figure 2 in FIG. 1, the image processing system 200 includes a processing module 201 and N target chips 202;

[0072] The processing module 201 is configured to obtain an image to be processed;

[0073] The processing module 201 is further configured to call M of the target chips 202 through an interconnection bus to perform image processing on the image to be processed according to the image processing sequence of the image to be processed, so as to obtain a target image.

[0074] In the embodiment of the present application, the processing module 201 can sequentially call the target chips 202 through the interconnection bus. That is to say, in the embodiment of the present application, multiple target chips 202 are called according to the image processing sequence of the image to be processed, rather than based on the positional relationship of the target chips 202, thereby improving the image processing efficiency and further improving the image processing ability.

[0075] Optionally, the processing module 201 is further configured to perform image processing on the image to be processed by calling one of the M target chips 202 through the interconnection bus according to the image processing sequence of the image to be processed;

[0076] The processing module 201 is further configured to, when calling the first chip among the M target chips 202 through the interconnection bus, determine the image returned by the first chip through the interconnection bus as the target image.

[0077] Optionally, the processing module 201 is further configured to send the image to be processed and a first call instruction through the interconnection bus;

[0078] The second chip is configured to perform image processing on the image to be processed and return the processed image to the processing module 201 through the interconnection bus.

[0079] In this embodiment, the processing module 201 in the image processing system calls the second chip based on the address information of the second chip, thereby abstracting the second chip as address information. By adding or deleting address information in the image processing system 200, the second chip can be added or deleted, improving the chip deployment efficiency.

[0080] Optionally, the processing module 201 is further configured to send a second call instruction through the interconnection bus;

[0081] The third chip is configured to read the image to be processed stored in the processing module 201 through the interconnection bus in response to the second call instruction;

[0082] The third chip is further configured to perform image processing on the image to be processed, and send the processed image back to the processing module 201 through the interconnection bus.

[0083] The image processing system in the embodiments of the present application may be an electronic device, or a component in an electronic device, such as an integrated circuit or a chip. The electronic device may be a terminal or other devices other than the terminal. Exemplarily, the electronic device may be a mobile phone, a tablet computer, a laptop computer, a handheld computer, a vehicle-mounted electronic device, a Mobile Internet Device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), etc. It may also be a server, a Network Attached Storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine, etc. The embodiments of the present application do not make specific limitations.

[0084] The image processing system in the embodiments of the present application may be a device with an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems. The embodiments of the present application do not make specific limitations.

[0085] The image processing system provided by the embodiments of the present application can implement Figure 3 each process implemented by the method embodiments. To avoid repetition, it will not be described in detail here.

[0086] Optionally, as Figure 6 shown, the embodiments of the present application further provide an electronic device 600, including a processor 601, a memory 602, a program or instruction stored on the memory 602 and executable on the processor 601. When the program or instruction is executed by the processor 601, it implements each process of the above image processing method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be described in detail here.

[0087] It should be noted that the electronic device in the embodiments of the present application includes the above-mentioned mobile electronic devices and non-mobile electronic devices.

[0088] Figure 7 It is a schematic hardware structure diagram of an electronic device for implementing the embodiments of the present application.

[0089] The electronic device 700 includes, but is not limited to, components such as a radio frequency unit 701, a network module 702, an audio output unit 703, an input unit 704, a sensor 705, a display unit 706, a user input unit 707, an interface unit 708, a memory 709, and a processor 710, etc.

[0090] Those skilled in the art can understand that the electronic device 700 may further include a power supply (such as a battery) for powering each component. The power supply can be logically connected to the processor 710 through a power management system, so as to implement functions such as management of charging, discharging, and power consumption management through the power management system. Figure 7 The structure of the electronic device shown does not limit the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0091] Among them, the input unit 704 is further configured to obtain an image to be processed;

[0092] The processor 710 is further configured to, through an interconnection bus, call M target chips to perform image processing on the image to be processed according to the image processing sequence of the image to be processed, so as to obtain a target image.

[0093] Among them, the processor 710 is further configured to, through the interconnection bus, each time call one of the M target chips to perform image processing on the image to be processed according to the image processing sequence of the image to be processed;

[0094] In the case of calling the first chip among the M target chips through the interconnection bus, determine the image returned by the first chip through the interconnection bus as the target image.

[0095] Among them, the processor 710 is further configured to send the image to be processed and a first call instruction through the interconnection bus during one call process;

[0096] The second chip performs image processing on the image to be processed and returns the processed image to the processing module through the interconnection bus.

[0097] Among them, the processor 710 is further configured to send a second call instruction through the interconnection bus;

[0098] The third chip responds to the second call instruction and reads the image to be processed stored in the processing module through the interconnection bus;

[0099] The third chip performs image processing on the image to be processed, and transmits the processed image back to the processing module through the interconnection bus.

[0100] In the embodiments of the present application, the processing module can sequentially call target chips through the interconnection bus. That is to say, in the embodiments of the present application, multiple target chips are called according to the image processing sequence corresponding to the image to be processed, rather than calling multiple target chips based on the positional relationship of the target chips, thereby improving the image processing efficiency and further improving the image processing ability of the electronic device.

[0101] It should be understood that in the embodiments of the present application, the input unit 704 may include a graphics processing unit (GPU) 7041 and a microphone 7042. The graphics processing unit 7041 processes the image data of static pictures or videos obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 706 may include a display panel 7061, and the display panel 7071 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 707 includes at least one of a touch panel 7071 and other input devices 7072. The touch panel 7071 is also called a touch screen. The touch panel 7071 may include two parts: a touch detection device and a touch controller. The other input devices 7072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, power on / off keys, etc.), a trackball, a mouse, and a joystick, which will not be elaborated here.

[0102] The memory 709 can be used to store software programs and various data. The memory 709 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data. Among them, the first storage area may store an operating system, application programs or instructions required for at least one function (such as a sound playback function, an image playback function, etc.). In addition, the memory 709 may include a volatile memory or a non-volatile memory, or the memory 709 may include both a volatile memory and a non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synch link dynamic random access memory (SLDRAM), and a direct rambus random access memory (DRRAM). The memory 709 in the embodiments of the present application includes, but is not limited to, these and any other suitable types of memories.

[0103] The processor 710 may include one or more processing units; optionally, the processor 710 integrates an application processor and a modem processor. Among them, the application processor mainly processes operations related to the operating system, user interface, and application programs, etc., and the modem processor mainly processes wireless communication signals, such as a baseband processor. It can be understood that the above modem processor may not be integrated into the processor 710 either.

[0104] The embodiments of the present application also provide a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, it implements each process of the above embodiment of the image processing method and can achieve the same technical effect. To avoid repetition, it will not be elaborated here.

[0105] Among them, the processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media such as computer read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0106] Another embodiment of the present application provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement each process of the above embodiment of the image processing method and can achieve the same technical effects. To avoid repetition, it will not be elaborated here.

[0107] It should be understood that the chip mentioned in the embodiments of the present application may also be referred to as a system-on-chip, system chip, chip system, or system-on-chip.

[0108] The embodiments of the present application provide a computer program product. The program product is stored in a storage medium and is executed by at least one processor to implement each process of the above embodiment of the image processing method and can achieve the same technical effects. To avoid repetition, it will not be elaborated here.

[0109] It should be noted that in this article, the term "including", "comprising", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such a process, method, article, or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article, or device including that element. In addition, it should be pointed out that the methods and devices in the embodiments of the present application are not limited to performing functions in the order shown or discussed. They may also include performing functions in a substantially simultaneous manner or in the reverse order according to the functions involved. For example, the described method may be executed in a different order than described, and various steps may be added, omitted, or combined. Additionally, the features described with reference to certain examples may be combined in other examples.

[0110] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described embodiment methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation manner. Based on such an understanding, the technical solution of the present application, in essence or the part that contributes to the prior art, can be embodied in the form of a computer software product. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions for causing a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of the present application.

[0111] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific implementation manners. The above specific implementation manners are merely illustrative rather than restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them belong to the protection scope of the present application.

Claims

1. An image processing system, characterized in that, It includes a processing module and N target chips, where N is a positive integer; The processing module is configured to obtain an image to be processed; The processing module is further configured to, through an interconnection bus, in accordance with the image processing sequence corresponding to the image to be processed, sequentially call M of the N target chips to perform image processing on the image to be processed, so as to obtain a target image; the M target chips are at least part of the N target chips, and M is a positive integer less than or equal to N.

2. The image processing system according to claim 1, wherein The processing module is further configured to, through the interconnection bus, in accordance with the image processing sequence corresponding to the image to be processed, each time call one of the M target chips to perform image processing on the image to be processed; The processing module is further configured to, in the case of calling the first chip among the M target chips through the interconnection bus, determine the image returned by the first chip through the interconnection bus as the target image, where the first chip is the last chip in the calling sequence among the M target chips.

3. The image processing system according to claim 2, wherein The processing module is further configured to send the image to be processed and a first calling instruction through the interconnection bus; the first calling instruction is determined based on the address information of the second chip to be called, and the second chip is one of the M target chips; The second chip is configured to perform image processing on the image to be processed and send the processed image back to the processing module through the interconnection bus.

4. The image processing system according to claim 2, characterized in that, The processing module is further configured to send a second calling instruction through the interconnection bus; the second calling instruction is determined based on the address information of the third chip to be called, and the third chip is one of the M target chips; The third chip is configured to, in response to the second calling instruction, read the image to be processed stored in the processing module through the interconnection bus; The third chip is further configured to perform image processing on the image to be processed and send the processed image back to the processing module through the interconnection bus.

5. An image processing method, characterized in that, Applied to an image processing system, the image processing system includes a processing module and N target chips, where N is a positive integer, and the method includes: The processing module obtains an image to be processed; The processing module, through an interconnection bus, in accordance with the image processing sequence corresponding to the image to be processed, sequentially calls M target chips to perform image processing on the image to be processed, so as to obtain a target image; the M target chips are at least part of the N target chips, and M is a positive integer less than or equal to N.

6. The method according to claim 5, wherein The processing module, through the interconnection bus, in accordance with the image processing sequence corresponding to the image to be processed, sequentially calls M target chips to perform image processing on the image to be processed, so as to obtain a target image includes: The processing module, through the interconnection bus, in accordance with the image processing sequence corresponding to the image to be processed, each time calls one of the M target chips to perform image processing on the image to be processed; When the processing module calls the first chip among the M target chips through the interconnect bus, the image returned by the first chip through the interconnect bus is determined as the target image, and the first chip is the last chip in the call order among the M target chips.

7. The method according to claim 6, wherein The processing module processes the to-be-processed image by calling one target chip among the M target chips each time through the interconnect bus according to the image processing order corresponding to the to-be-processed image, including: During one call process, the processing module sends the to-be-processed image and a first call instruction through the interconnect bus; the first call instruction is determined based on the address information of the second chip to be called, and the second chip is one of the M target chips; The second chip processes the to-be-processed image and returns the processed image to the processing module through the interconnect bus.

8. The method according to claim 6, wherein The processing module processes the to-be-processed image by calling one target chip among the M target chips each time through the interconnect bus according to the image processing order corresponding to the to-be-processed image, including: The processing module sends a second call instruction through the interconnect bus; the second call instruction is determined based on the address information of the third chip to be called, and the third chip is one of the M target chips; The third chip responds to the second call instruction and reads the to-be-processed image stored by the processing module through the interconnect bus; The third chip processes the to-be-processed image and returns the processed image to the processing module through the interconnect bus.

9. An electronic device, characterized in that, It includes a processor, a memory, and a program or instruction stored on the memory and executable on the processor. When the program or instruction is executed by the processor, the steps of the image processing method described in any one of claims 5-8 are implemented.

10. A readable storage medium, characterized in that, A program or instruction is stored on the readable storage medium. When the program or instruction is executed by a processor, the steps of the image processing method described in any one of claims 5-8 are implemented.

Images