A stacked circuit structure and a method for preparing the same

Abstract

The present invention belongs to the technical field related to integrated circuit packaging, and discloses a stacked circuit structure and a preparation method thereof. The method includes the following steps: (1) Prepare patterned circuits on two opposite surfaces of a ceramic plate, and prepare an intercommunication channel on the ceramic plate, where the intercommunication channel connects the two patterned circuits; semiconductor devices are mounted on the patterned circuits; (2) Prepare a plurality of isolation layers and multiple layers of circuits in sequence on one of the patterned circuits to obtain the stacked circuit structure; the isolation layers and the circuits are arranged alternately; semiconductor devices are mounted on the circuits, the semiconductor devices are embedded in the corresponding isolation layers, and the isolation layers are provided with intercommunication channels, and the intercommunication channels connect adjacent two layers of circuits. The present invention forms a stacked circuit structure through a magnetron sputtering process, simplifying the original manufacturing process steps of multi-layer circuits.

Description

Technical Field

[0001] The present invention belongs to the technical field related to integrated circuit packaging, and more specifically, relates to a stacked circuit structure and a preparation method thereof. Background Art

[0002] As one of the pillar industries in the development of today's society, the electronic information industry has greatly changed people's way of life. Under the guidance of Moore's Law, the functions of various electronic products are developing towards high computing speed, high performance, and high integration. Among them, the integrated circuit components play a core role. The characteristic size of the devices is continuously reduced, and the gate delay is correspondingly reduced, but the time delay problem caused by inter-module interconnection becomes increasingly prominent. During the packaging process of chips and micro-nano structures on the substrate, on the one hand, it is limited by the size of the substrate, and on the other hand, it is limited by the need for circuit connection. Often, a large increase in the length of the interconnection lines is selected to meet the functional requirements. Therefore, by using the multi-layer stacking method to design the circuit structure and the placement strategy of semiconductor components, the traditional two-dimensional layout can be extended to a three-dimensional layout, greatly increasing the degree of freedom of circuit design, reducing parasitic capacitance, improving the overall signal exchange performance of the circuit, and meeting the requirements of related applications.

[0003] At present, there are mainly two types of structures for multi-layer three-dimensional integrated circuits: 1. Embedded redistribution layer (RDL); 2. Bonding and interconnection using through-silicon vias (TSV). The redistribution technology is widely used in the production of printed circuit boards (PCBs). By designing the connection lines of components in multiple layers, the purpose of increasing the device density on the surface of the circuit board is achieved. Its process maturity is high and the cost is low. However, since the redistribution layer can only be used for circuit layout and cannot place independent components, it greatly limits the further improvement of its device density. The bonding technology using through-silicon vias to fabricate three-dimensional integrated circuit structures is a rapidly developing integrated circuit process structure at present. It realizes the electrical and mechanical interconnection of different layers of circuits by etching vias on the silicon wafer and filling the vias. However, its process difficulty is large and the cost is high, and it is not feasible for circuit structures with general precision requirements. On the other hand, while the performance of the three-dimensional structure is improved, the heat generation is greatly increased, and there are relatively difficult heat dissipation problems when using a silicon substrate. Summary of the Invention

[0004] In view of the above deficiencies or improvement requirements of the prior art, the present invention provides a stacked circuit structure and a preparation method thereof. A ceramic plate is used as the substrate of the stacked circuit structure, which improves the overall heat dissipation performance of the device; both sides of the ceramic substrate are electroplated and patterned, and interconnections are formed through material-formed vias, and the preparation is simple. Among them, the direct writing process and the spin coating process are organically combined to quickly coat the insulating glue to form an isolation layer, which increases the reliability and thermal conductivity of the device. The laser drilling technology is used to selectively punch through the isolation layer and retain the interconnection pads, and then the electroplating deposition process is carried out to form an interconnection channel, which not only reduces the cost of interlayer interconnection but also speeds up the overall manufacturing speed of the device. The stacked circuit structure is formed by the magnetron sputtering process, which simplifies the original multi-layer circuit manufacturing process steps.

[0005] To achieve the above object, according to one aspect of the present invention, a preparation method of a stacked circuit structure is provided, and the method includes the following steps:

[0006] (1) Prepare patterned circuits on two opposite surfaces of the ceramic plate, and prepare through-hole channels on the ceramic plate, and the through-hole channels connect the two patterned circuits; semiconductor devices are mounted on the patterned circuits;

[0007] (2) Prepare a plurality of isolation layers and multi-layer circuits in sequence on one of the patterned circuits to obtain the stacked circuit structure; the isolation layers and the circuits are arranged alternately; semiconductor devices are mounted on the circuits, the semiconductor devices are embedded in the corresponding isolation layers, and the isolation layers are provided with through-hole channels, and the through-hole channels connect adjacent two layers of circuits; The isolation layer is prepared by combining direct writing and spin coating, and includes the following steps:

[0008] First, according to the layout positions of the semiconductor components on each layer of the circuit, plan the moving path of the direct writing nozzle from the edge of the circuit to the center of the circuit;

[0009] After that, perform an L-shaped coating on the edge of the circuit, and the two L-shaped routes share the starting point;

[0010] Then, heat and cure the coated insulating glue to obtain a temporary enclosure at the edge of the circuit;

[0011] After that, apply glue along the outer edge of the raised semiconductor device on the circuit and pause for 0.05 s to 0.1 s at the corner points;

[0012] Then, perform direct writing and coating of insulating glue on the circuit layer line part, and perform inward "return" literal sweeping direct writing from the edge of the layer circuit;

[0013] After that, directly write insulating glue on the central part of the circuit to obtain the isolation layer.

[0014] Further, an isolation layer is provided between the patterned circuit and the circuit adjacent to the patterned circuit, and the patterned circuit board is connected to the corresponding circuit.

[0015] Further, the copper layer thickness of the patterned circuit on the ceramic substrate is 30 to 100 um; the material of the ceramic plate is one of aluminum nitride, alumina, beryllium oxide or silicon nitride, and the thickness is 100 to 500 um.

[0016] Further, the insulating adhesive is selected from one of PI, epoxy resin, and silicone resin.

[0017] Further, the insulating adhesive is cured by heating, the curing temperature is 100°C to 350°C, and the curing time is 1 h to 3 h.

[0018] Further, the interconnect vias of different layers of circuits are completed by laser drilling and electroplating. The selected laser is a carbon dioxide laser with a laser wavelength of 10.6 um, which can selectively ablate only the isolation layer.

[0019] Further, the electroplating seed layer is served by the lower layer circuit pad exposed after punching through the isolation layer.

[0020] Further, the temperature is sequentially raised to 70°C, 150°C, 250°C, and 350°C in a vacuum reflow furnace and heated for 30 minutes each to cure the insulating adhesive to obtain the isolation layer.

[0021] According to another aspect of the present invention, a stacked circuit structure is provided, and the stacked circuit structure is prepared by using the preparation method of the stacked circuit structure as described above.

[0022] Generally speaking, compared with the prior art by the above technical solutions conceived by the present invention, the stacked circuit structure and its preparation method provided by the present invention mainly have the following beneficial effects:

[0023] 1. The present invention uses a ceramic plate as the substrate of the stacked circuit structure. The ceramic plate has excellent high thermal conductivity and relatively mature drilling and copper plating processes; the excellent thermal conductivity of the ceramic can increase the heat dissipation intensity of the device itself; on the other hand, direct copper plating on the ceramic surface has high patterning accuracy and can match the accuracy of the soft mask magnetron sputtering circuit.

[0024] 2. The present invention uses a direct writing process in combination with spin coating for applying the insulating glue of the isolation layer. By leveraging the high-precision control of the direct writing process to control the amount of the basic insulating glue and the extrusion position, and taking advantage of the mobility of the direct writing process, first, the outer contour of the layer circuit is fixed to prevent excessive ejection of the insulating glue. Specialized treatment is carried out around the semiconductor components. On the one hand, the uneven topography generated by the mounted devices can be modified and filled. On the other hand, according to the scattering situation of the insulating glue at the corner points in the spin coating process, pauses are made at the corner points to make the spin coating more uniform, saving the insulating glue used. Since the cost of the insulating glue is often high, this will significantly improve the overall economy of the process. In the spin coating process, it is only necessary to flatten the one coated by direct writing at a low rotation speed, and then combined with the spin coating process, insulating glue is additionally applied at the center to adjust the thickness and surface flatness of the insulating glue. The organic combination of the two processes reduces the process cost and shortens the process time.

[0025] 3. The present invention uses a laser drilling process to achieve the interlayer connection of the stacked circuit. The selected laser is a carbon dioxide laser with a wavelength of 10.6 um, which can enable the polymer material to rapidly absorb, while the base metal pad has almost no absorption effect on the laser of this wavelength band. Combining with the design of placing the pad under the isolation layer in the present invention, a selective effect of almost no damage to the underlying metal is achieved, ensuring the interconnection effect after subsequent hole filling. On the other hand, the relatively high energy conversion rate and working power of the carbon dioxide laser result in a very high drilling efficiency.

[0026] 4. The present invention uses electroplating to fill the interconnection channels, and cleverly utilizes the formed interconnection pads under the interconnection channels as electroplating seed layers to achieve the positioning growth of the interconnection metal. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a cross-sectional view of a stacked circuit structure provided by the present invention;

[0028] Figure 2 is a flowchart of a preparation method of a stacked circuit structure provided by the present invention;

[0029] Figure 3 is Figure 1 a schematic diagram of laser selective ablation of the interconnection channel structure in the stacked circuit structure in

[0030] In all the drawings, the same reference numerals are used to represent the same elements or structures, where: 1 - the first semiconductor device, 2 - the first patterned circuit, 3 - the second semiconductor device, 4 - the first interconnection channel, 5 - the first isolation layer, 6 - the second patterned circuit, 7 - the third semiconductor device, 8 - the second isolation layer, 9 - the second interconnection channel, 10 - the ceramic plate, 11 - the third interconnection channel, 12 - the fourth semiconductor device. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0032] In order to overcome the defects of existing multi-layer three-dimensional integrated circuits in terms of difficult heat dissipation and complex processes, and in response to the high component density requirements brought about by high-performance and multi-functional monolithic integration, the present invention provides a preparation method for a stacked circuit structure, which solves the problems of insufficient heat dissipation capacity and complex processes of existing multi-layer three-dimensional integrated circuit structures, and at the same time greatly improves the component density, is compatible with existing integrated circuit production lines, and realizes a stacked circuit process that can be used for rapid production.

[0033] Please refer to Figure 1 、 Figure 2 and Figure 3 , the preparation method mainly includes the following steps:

[0034] Step 1, prepare patterned circuits and third interconnection holes 11 on the two opposite surfaces of the ceramic plate 10, and respectively mount a fourth semiconductor device 12 and a third semiconductor device 7 on the two opposite sides of the ceramic plate 10. The third interconnection holes 11 connect the fourth semiconductor device 12 and the third semiconductor device 7.

[0035] Among them, the copper layer thickness of the patterned circuit on the ceramic substrate is 30-100 um; the material of the ceramic plate 10 is one of aluminum nitride, alumina, beryllium oxide or silicon nitride, and the thickness is 100-500 um.

[0036] The material of the ceramic plate 10 as the substrate can preferably be aluminum nitride, with a thermal expansion coefficient of 4.4X10 -6 / °C and a thermal conductivity of 180 W / (m·k), and the thickness is 350 um. The ceramic plate 10 serves as a circuit substrate, with an electroplated copper layer circuit on the surface. The upper surface and the lower surface are interconnected by electroplated filling holes. The circuit and the holes are integrally formed by direct electroplating. Among them, the upper surface is provided with a device mounting area for applying solder paste to connect with semiconductor devices. At the same time, there are reserved pads for interlayer connection. The lower surface places a device power supply module and high-power semiconductor devices, and is connected to an external circuit and a heat dissipation device at the same time. The thickness of the electroplated metal copper layer in this embodiment is 100 um.

[0037] Step 2, directly write and spin-coat an insulating glue in sequence on the side of the ceramic plate 10 where the third semiconductor device 7 is located, and then heat and cure it to form a second isolation layer 8.

[0038] The insulating glue is selected from one of PI (polyimide), epoxy resin, and silicone resins. After being coated on the ceramic plate 10 and cured at a process temperature of 100 - 350°C, an insulating layer with a thickness of 200um - 300um is formed. The insulating glue is cured by heating up, with a curing temperature of 100°C - 350°C and a curing time of 1h - 3h.

[0039] The coating method of the insulating glue is a direct writing technology combined with a spin coating process, which significantly reduces the use of insulating glue and shortens the process time compared with the single spin coating process. It is realized by the following steps:

[0040] (1) First, according to the placement of the circuit structure components in each layer, plan the movement path of the direct writing process nozzle from the edge of the layer circuit to the center of the layer circuit.

[0041] (2) First, perform an "L"-shaped coating on the edge of the circuit layer. Referring to the required thickness of the insulating layer, control the glue outlet air pressure. Utilizing the start-stop characteristics of the direct writing process, the starting points of the two "L"-shaped routes are shared to ensure uniform distribution of the insulating glue on each side and corner points.

[0042] (3) Perform short-term pre-curing heating on the edge insulating glue. Utilizing the high solid content characteristic of the configured insulating glue, control the heating time within 5 - 10 minutes and the temperature at 70 degrees Celsius (taking polyimide insulating glue as an example) to form a temporary enclosure at the edge of the layer circuit.

[0043] (4) Apply glue along the outer edge of the protruding component parts on the circuit layer, such as chips, capacitors, and resistors. Consider implementing a rounded corner transition at the component corner points and pause for 0.05s - 0.1s at the corner points according to the viscosity of the insulating glue.

[0044] (5) Then, perform direct writing and coating of the insulating glue on the circuit layer line part, i.e., the part with a low vertical height, and perform an inward "return" character sweep direct writing from the edge of the layer circuit.

[0045] (6) Raise the direct writing nozzle, apply a certain amount of insulating glue to the center part of the circuit layer according to the required thickness, and perform spin coating at a low speed of 300r / min for 30 seconds (taking high-viscosity polyimide glue as an example).

[0046] (7) Let the circuit layer after spin coating stand still. Again, perform direct writing of a small amount of insulating glue on the center part of the circuit layer and perform spin coating at 500r / min for 30 seconds (taking high-viscosity polyimide glue as an example) to obtain a highly flat insulating glue surface and complete the direct writing and spin coating process.

[0047] Step three, perform laser drilling on the second isolation layer 8, and the obtained through holes penetrate the second isolation layer 8.

[0048] The interconnect vias between different layers are completed by a laser drilling process. The selected laser is a carbon dioxide laser. The power and moving speed are designed according to the thickness of the insulating layer to achieve complete penetration of the isolation layer without affecting the underlying metal pads. The isolation layer formed by punching through the insulating glue is drilled through by laser. The laser wavelength is 10.6um, which can selectively ablate only the isolation layer. After forming the interconnect vias, electroplating is used for filling to achieve interlayer electrical connection.

[0049] Step Four: Electroplate the through-holes to obtain the second interconnected via 9.

[0050] Among them, the electroplating seed layer is served by the underlying circuit pads exposed after punching through the isolation layer.

[0051] Step Five: Thinning the second isolation layer 8.

[0052] According to the design requirements and the size of the mounted semiconductor device, the insulating layer is appropriately thinned to be 10 - 20um higher than the semiconductor components by grinding and polishing.

[0053] Step Six: Prepare the second patterned circuit 6 on the second isolation layer 8 and mount the second semiconductor device 3.

[0054] Step Seven: Prepare the first isolation layer 5 on the second patterned circuit 6 and prepare the first interconnected via 4 on the first isolation layer 5.

[0055] Step Eight: Prepare the circuit with the required number of layers in the above manner to obtain the stacked circuit structure; the outermost circuit away from the ceramic plate 10 is the first patterned circuit 2, and the first semiconductor device 1 is mounted on the first patterned circuit 2.

[0056] Apply solder paste to the circuit pad positions, mount the semiconductor devices, and reflow the solder paste to complete the in-layer circuit. Repeat the steps of applying and curing the insulating glue, laser drilling, electroplating filling, sputtering the circuit on the insulating layer, and mounting the semiconductor devices to fabricate a stacked circuit with an unspecified number of layers.

[0057] The processes for fabricating the interlayer connection lines and the circuit on the insulating layer include the following steps:

[0058] (1) Fill the interconnect vias obtained by laser drilling by electroplating. The electroplating seed layer is served by the underlying circuit pads exposed after punching through the isolation layer.

[0059] (2) Attach a soft mask made by laser processing of PVC material on the insulating layer according to the circuit requirements.

[0060] (3) Sputter metallic copper onto the mask by magnetron sputtering. Control the sputtering time according to the required thickness of the circuit. After sputtering is completed, tear off the soft mask to obtain the required circuit on the insulating layer.

[0061] The present invention also provides a stacked circuit structure prepared by using the preparation method of the stacked circuit structure as described above. The stacked circuit structure includes a ceramic plate 10 and multiple layers of circuits arranged in a layered manner from bottom to top. Patterned circuits are formed on both opposite sides of the ceramic plate 10 and are connected to each other. Semiconductor devices are mounted on the patterned circuits. The multiple layers of circuits are arranged at intervals, semiconductor devices are mounted on each circuit, and adjacent circuits are connected through through-holes. An isolation layer is provided between adjacent circuits, the semiconductor devices are embedded in the isolation layer, and corresponding through-holes are formed in the isolation layer. An isolation layer is also provided between the circuit and the patterned circuit of the ceramic plate 10, and the corresponding semiconductor devices are also embedded in the corresponding isolation layer.

[0062] The following several embodiments are used to further elaborate on the present invention in detail.

[0063] Embodiment 1

[0064] In this embodiment, the insulating layer adhesive is selected as PI (polyimide), with a viscosity of 3000 cp to 5000 cp and a coefficient of thermal expansion of 3.5X10 -5 / ℃.

[0065] The formation of the isolation layer includes the following steps:

[0066] 1) Ultrasonically clean the surface of the ceramic plate and the metal layer with acetone and deionized water, and then perform a drying treatment.

[0067] 2) Rapidly extrude PI (polyimide) through a direct writing printing device and coat it according to the strategy described above. The air pressure is controlled at 50 kPa. At the same time, the ceramic plate moves in cooperation on the stage, so that the insulating glue in each area is dispersed evenly according to the extrusion strategy and a small amount of excess glue is thrown out.

[0068] 3) According to the requirements of the heating and curing curve of the PI (polyimide) product, sequentially raise the temperature to 70 °C, 150 °C, 250 °C, and 350 °C in a vacuum reflux furnace and heat for 30 minutes each to completely imidize the polyimide solution.

[0069] During the process of using a carbon dioxide laser with a wavelength of 10.6 μm, the upper isolation layer composed of a high polymer has a very high laser absorption rate and can be rapidly ablated and evaporated under the action of the laser. However, the pads in the magnetron sputtering layer patterned circuit made of metal have a very low laser absorption rate for this wavelength band and are not affected by the laser action.

[0070] After adjusting the laser power to 5W and controlling the feeding rate and pulse frequency of the laser, a via hole with a diameter of 300 μm is obtained, which can control to only penetrate the isolation layer without affecting the underlying metal. At the same time, due to the blocking effect of the patterned circuit metal layer, the isolation layer can be protected from being affected during the process of laser drilling on the isolation layer.

[0071] After the laser drilling is completed, first use the grinding process to thin the solidified isolation layer so that its thickness is slightly higher than the underlying semiconductor device by 10 - 20 μm, reducing the overall thickness of the device. Then, use the copper pads in the exposed patterned circuit as the electroplating seed layer. After removing burrs and slag, place the stacked circuit device as a whole in a copper salt solution for electroplating copper to complete the filling of the blind holes.

[0072] The production method of the stacked patterned circuit is the magnetron sputtering method. First, perform plasma etching on the thinned isolation layer to increase the bonding force with the metal. Then, select copper with chromium metal as the adhesion layer as the sputtered metal, and the thickness is 1 μm - 2 μm.

[0073] Example 2

[0074] In this example, a chromium target is selected as the adhesion layer for sputtering the copper layer patterned circuit, and the sputtering atmosphere is in a high - vacuum cavity. The realization of the patterned circuit production includes the following steps:

[0075] 1) Clean the surface of the isolation layer with acetone and etch it through a plasma etching machine to obtain a pure surface without impurities and with high metal bonding force. Then, attach a soft mask of the patterned circuit made of PVC soft film material to the isolation layer.

[0076] 2) Magnetron sputter the adhesion layer material chromium (purity 99.9%), and the sputtering time is 20 minutes.

[0077] 3) Replace the sputtering target and magnetron sputter copper (purity 99.99%), and the sputtering time is 40 minutes.

[0078] 4) Tear off the PVC soft mask to obtain the required patterned circuit layer.

[0079] The circuit forms an isolation layer by directly writing and spin - coating an insulating glue for curing between layers, forms an inter - layer electrical interconnection by laser drilling and electroplating filling, forms a patterned circuit by magnetron sputtering on the isolation layer, and smears solder to mount semiconductor devices. Finally, each layer of the circuit has independent functions and can communicate and interconnect with each other, obtaining a stacked circuit with more layers.

[0080] Those skilled in the art can easily understand that the above - mentioned are only the preferred embodiments of the present invention, and are not used to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A preparation method of a stacked circuit structure, characterized in that, the method comprises the following steps: (1) Prepare patterned circuits on two opposite surfaces of a ceramic plate, and prepare through holes on the ceramic plate, the through holes connecting the two patterned circuits; semiconductor devices are mounted on the patterned circuits; (2) Prepare a plurality of isolation layers and multiple layers of circuits in sequence on one of the patterned circuits to obtain the stacked circuit structure; the isolation layers and the circuits are arranged alternately; semiconductor devices are mounted on the circuits, the semiconductor devices are embedded in the corresponding isolation layers, and the isolation layers are provided with through holes, the through holes connecting adjacent two layers of circuits; The isolation layer is prepared by combining direct writing and spin coating, including the following steps: First, according to the layout positions of the semiconductor components on each layer of circuit, plan the moving path of the direct writing nozzle from the edge of the circuit to the center of the circuit; After that, perform an L-shaped coating on the edge of the circuit, and the two L-shaped routes share the starting point; Then, heat and cure the coated insulating glue to obtain a temporary enclosure at the edge of the circuit; After that, apply glue along the outer edge of the convex semiconductor device on the circuit and pause for 0.05 s to 0.1 s at the corner points; Then, perform direct writing coating of insulating glue on the circuit layer line part, and perform inward back surface sweeping direct writing from the edge of the layer circuit; After that, directly write insulating glue on the central part of the circuit, thereby obtaining the isolation layer.

2. The preparation method of the stacked circuit structure according to claim 1, characterized in that: An isolation layer is provided between the patterned circuit and the circuit adjacent to the patterned circuit, and the patterned circuit board is connected to the corresponding circuit.

3. The preparation method of the stacked circuit structure according to claim 1, characterized in that: The copper layer thickness of the patterned circuit on the ceramic plate is 30 - 100 um; the material of the ceramic plate is one of aluminum nitride, alumina, beryllium oxide or silicon nitride, and the thickness is 100 - 500 um.

4. The preparation method of the stacked circuit structure according to claim 1, characterized in that: The insulating glue is selected from one of PI, epoxy resin, and silicone resin.

5. The preparation method of the stacked circuit structure according to claim 4, characterized in that: The insulating glue is cured by heating, the curing temperature is 100°C - 350°C, and the curing time is 1 h - 3 h.

6. The preparation method of the stacked circuit structure according to claim 1, characterized in that: The interconnecting holes of different layers of circuits are completed by laser drilling technology and electroplating. The selected laser is a carbon dioxide laser, the laser wavelength is 10.6 um, and it can selectively ablate only the isolation layer.

7. The preparation method of the stacked circuit structure according to claim 6, characterized in that: The electroplating seed layer is served by the lower layer circuit pad exposed after punching through the isolation layer.

8. The preparation method of the stacked circuit structure according to claim 1, characterized in that: In a vacuum reflow furnace, raise the temperature to 70°C, 150°C, 250°C, and 350°C in sequence and heat for 30 minutes each, so that the insulating glue is cured to obtain the isolation layer.

9. A stacked circuit structure, characterized in that: The stacked circuit structure is prepared by using the preparation method of the stacked circuit structure according to any one of claims 1-8.

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