electronic circuits

Abstract

The present application provides an electronic circuit, which includes a first transistor coupled between a first node and a supply voltage and controlled by the first node, a second transistor coupled between a second node and the supply voltage and controlled by the first node, a third transistor coupled between a third node and the supply voltage and controlled by a fourth node, a fourth transistor coupled between a fourth node and the supply voltage and controlled by the fourth node, a fifth transistor coupled between the first node and a fifth node and controlled by a reference voltage, a sixth transistor coupled between the second node and the ground terminal and controlled by the third node, a seventh transistor coupled between the fourth node and the ground terminal and controlled by the second node, a first resistor coupling the fifth node to the ground terminal, and a second resistor coupling the third node to the ground terminal.

Description

Technical Field

[0001] The present invention relates to an electronic circuit, and more particularly to an electronic circuit for generating a reference current with a low temperature coefficient. Background Art

[0002] Nowadays, many applications are found in automotive and medical electronic products, and a current reference circuit with high accuracy and low temperature coefficient (Low TC) is very important. Figure 1 A circuit diagram showing an electronic circuit according to the prior art. Figure 1 As shown, the electronic circuit 100 includes an operational amplifier 110 , a first N-type transistor N1 , a first P-type transistor P1 , a second P-type transistor P2 , a third P-type transistor P3 , and a reference resistor RF.

[0003] Operational amplifier 110 compares bandgap voltage VBG, which has a low temperature coefficient, with resistor voltage VR, and controls first N-type transistor N1 to increase or decrease first current I1. First P-type transistor P1, second P-type transistor P2, and third P-type transistor P3 form a current mirror to mirror first current I1 to generate second current I2 and reference current IREF. When resistor voltage VR equals bandgap voltage VBG and reference resistor RF has a zero temperature coefficient, the temperature coefficient of reference current IREF is determined by the temperature coefficient of bandgap voltage VBG.

[0004] However, operational amplifier 110 requires a large amount of circuit area and consumes a lot of current. Therefore, using an operational amplifier to generate a high-precision reference current with a low temperature coefficient is bound to be costly. In order to reduce the cost of generating a low temperature coefficient reference current, it is necessary to optimize the electronic circuit that generates the low temperature coefficient reference current. Summary of the Invention

[0005] The present invention provides an electronic circuit for generating a high-precision, low-temperature-coefficient reference current. Because the electronic circuit does not require an operational amplifier, it significantly reduces circuit area and power consumption, and can operate independently without a current source. Furthermore, by matching transistors and canceling the temperature coefficients of resistors, the temperature coefficient of the reference current is determined by the reference voltage. Furthermore, the electronic circuit can operate at lower supply voltages and can convert the bandgap voltage to other voltages by selecting resistor values.

[0006] In view of this, the present invention provides an electronic circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first resistor, and a second resistor. The first transistor comprises a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a first node, the source terminal is coupled to a supply voltage, and the gate terminal is coupled to the first node. The second transistor comprises a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a second node, the source terminal is coupled to the supply voltage, and the gate terminal is coupled to the first node. The third transistor comprises a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a third node, the source terminal is coupled to the supply voltage, and the gate terminal is coupled to a fourth node. The fourth transistor comprises a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the fourth node, the source terminal is coupled to the supply voltage, and the gate terminal is coupled to the fourth node. The fifth transistor includes a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the first node, the source terminal is coupled to a fifth node, and the gate terminal receives a reference voltage. The sixth transistor includes a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the second node, the source terminal is coupled to a ground terminal, and the gate terminal is coupled to the third node. The seventh transistor includes a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the fourth node, the source terminal is coupled to the ground terminal, and the gate terminal is coupled to the second node. The first resistor is coupled between the fifth node and the ground terminal. The second resistor is coupled between the third node and the ground terminal.

[0007] According to one embodiment of the present invention, the electronic circuit further includes an eighth transistor and a ninth transistor. The eighth transistor includes a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a reference node, the source terminal is coupled to the supply voltage, and the gate terminal is coupled to the first node. The ninth transistor includes a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the reference node, the source terminal is coupled to the supply voltage, and the gate terminal is coupled to the fourth node.

[0008] According to an embodiment of the present invention, the first transistor, the second transistor, the third transistor, the fourth transistor, the eighth transistor and the ninth transistor are P-type transistors, and the fifth transistor, the sixth transistor and the seventh transistor are N-type transistors.

[0009] According to one embodiment of the present invention, the electronic circuit further includes a third resistor coupled between the reference node and the ground terminal, wherein an output voltage is generated at the reference node, wherein a temperature coefficient of the output voltage is determined by the reference voltage.

[0010] According to one embodiment of the present invention, the eighth transistor and the ninth transistor generate a reference current at the reference node, wherein a temperature coefficient of the reference current is determined by a temperature coefficient of the reference voltage. The first transistor, the second transistor, and the eighth transistor are arranged concentrically, and the third transistor, the fourth transistor, and the ninth transistor are arranged concentrically.

[0011] According to one embodiment of the present invention, the base terminal of the fifth transistor is coupled to the fifth node, and the base terminal of the sixth transistor is coupled to the ground terminal, wherein the fifth transistor is formed in a first P-type well coupled to the fifth node, and the sixth transistor is formed in a second P-type well coupled to the ground terminal, wherein the first P-type well and the second P-type well are arranged in a concentric manner.

[0012] According to one embodiment of the present invention, the first resistor includes a first sub-resistor and a second sub-resistor. The first sub-resistor has a first positive temperature coefficient, and the second sub-resistor has a first negative temperature coefficient. The first sub-resistor and the second sub-resistor are connected in series to form the first resistor.

[0013] According to one embodiment of the present invention, the ratio of the resistance value of the above-mentioned first sub-resistor to the resistance value of the above-mentioned second sub-resistor is a first resistance ratio, and the ratio of the above-mentioned first positive temperature coefficient to the above-mentioned first negative temperature coefficient is a first temperature coefficient ratio, wherein the above-mentioned first resistance ratio is the inverse of the above-mentioned first temperature coefficient ratio, so as to reduce the temperature coefficient of the above-mentioned first resistor.

[0014] According to one embodiment of the present invention, the second resistor includes a third sub-resistor and a fourth sub-resistor. The third sub-resistor has a second positive temperature coefficient, and the fourth sub-resistor has a second negative temperature coefficient. The third sub-resistor and the fourth sub-resistor are connected in series to form the second resistor.

[0015] According to one embodiment of the present invention, the ratio of the resistance value of the third sub-resistor to the resistance value of the fourth sub-resistor is a second resistance ratio, and the ratio of the second positive temperature coefficient to the second negative temperature coefficient is a second temperature coefficient ratio, wherein the second resistance ratio is the inverse of the second temperature coefficient ratio, so as to reduce the temperature coefficient of the second resistor.

[0016] The present invention also provides an electronic circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first resistor, and a second resistor. The first transistor comprises a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a first node, the source terminal is coupled to a ground terminal, and the gate terminal is coupled to the first node. The second transistor comprises a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a second node, the source terminal is coupled to the ground terminal, and the gate terminal is coupled to the first node. The third transistor comprises a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a third node, the source terminal is coupled to the ground terminal, and the gate terminal is coupled to a fourth node. The fourth transistor comprises a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the fourth node, the source terminal is coupled to the ground terminal, and the gate terminal is coupled to the fourth node. The fifth transistor includes a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the first node, the source terminal is coupled to a fifth node, and the gate terminal receives a reference voltage. The sixth transistor includes a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the second node, the source terminal is coupled to a supply voltage, and the gate terminal is coupled to the third node. The seventh transistor includes a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the fourth node, the source terminal is coupled to the supply voltage, and the gate terminal is coupled to the second node. The first resistor is coupled between the fifth node and the supply voltage. The second resistor is coupled between the third node and the supply voltage.

[0017] According to one embodiment of the present invention, the electronic circuit further includes an eighth transistor and a ninth transistor. The eighth transistor includes a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a reference node, the source terminal is coupled to the ground terminal, and the gate terminal is coupled to the first node. The ninth transistor includes a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the reference node, the source terminal is coupled to the ground terminal, and the gate terminal is coupled to the fourth node.

[0018] According to an embodiment of the present invention, the first transistor, the second transistor, the third transistor, the fourth transistor, the eighth transistor and the ninth transistor are N-type transistors, and the fifth transistor, the sixth transistor and the seventh transistor are P-type transistors.

[0019] According to one embodiment of the present invention, the electronic circuit further includes a third resistor coupled between the reference node and the supply voltage, wherein an output voltage is generated at the reference node, wherein a temperature coefficient of the output voltage is determined by the reference voltage.

[0020] According to one embodiment of the present invention, the eighth transistor and the ninth transistor generate a reference current at the reference node, wherein a temperature coefficient of the reference current is determined by a temperature coefficient of the reference voltage. The first transistor, the second transistor, and the eighth transistor are arranged concentrically, and the third transistor, the fourth transistor, and the ninth transistor are arranged concentrically.

[0021] According to one embodiment of the present invention, the base terminal of the fifth transistor is coupled to the fifth node, and the base terminal of the sixth transistor is coupled to the supply voltage, wherein the fifth transistor is formed in a first N-type well coupled to the fifth node, and the sixth transistor is formed in a second N-type well coupled to the supply voltage, wherein the first N-type well and the second N-type well are arranged in a concentric manner.

[0022] According to one embodiment of the present invention, the first resistor includes a first sub-resistor and a second sub-resistor. The first sub-resistor has a first positive temperature coefficient, and the second sub-resistor has a first negative temperature coefficient. The first sub-resistor and the second sub-resistor are connected in series to form the first resistor.

[0023] According to one embodiment of the present invention, the ratio of the resistance value of the above-mentioned first sub-resistor to the resistance value of the above-mentioned second sub-resistor is a first resistance ratio, and the ratio of the above-mentioned first positive temperature coefficient to the above-mentioned first negative temperature coefficient is a first temperature coefficient ratio, wherein the above-mentioned first resistance ratio is the inverse of the above-mentioned first temperature coefficient ratio, so as to reduce the temperature coefficient of the above-mentioned first resistor.

[0024] According to one embodiment of the present invention, the second resistor includes a third sub-resistor and a fourth sub-resistor. The third sub-resistor has a second positive temperature coefficient, and the fourth sub-resistor has a second negative temperature coefficient. The third sub-resistor and the fourth sub-resistor are connected in series to form the second resistor.

[0025] According to one embodiment of the present invention, the ratio of the resistance value of the third sub-resistor to the resistance value of the fourth sub-resistor is a second resistance ratio, and the ratio of the second positive temperature coefficient to the second negative temperature coefficient is a second temperature coefficient ratio, wherein the second resistance ratio is the inverse of the second temperature coefficient ratio, so as to reduce the temperature coefficient of the second resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 a circuit diagram showing an electronic circuit according to the prior art;

[0027] Figure 2 A circuit diagram showing an electronic circuit according to an embodiment of the present invention;

[0028] Figure 3 Showing the present invention Figure 2 a top view of the layout of the electronic circuit;

[0029] Figure 4 A circuit diagram showing an electronic circuit according to another embodiment of the present invention;

[0030] Figure 5 A circuit diagram showing an electronic circuit according to another embodiment of the present invention;

[0031] Figure 6 Showing the present invention Figure 5 a top view of the layout of the electronic circuit; and

[0032] Figure 7 A circuit diagram showing an electronic circuit according to another embodiment of the present invention.

[0033] Figure Number:

[0034] 100, 200, 400: Electronic circuits

[0035] 110: Operational Amplifier

[0036] 300,500: Layout

[0037] N1: first N-type transistor

[0038] P1: first P-type transistor

[0039] P2: Second P-type transistor

[0040] P3: The third P-type transistor

[0041] RF: Reference resistance

[0042] VBG: Bandgap voltage

[0043] VR: resistance voltage

[0044] I1: first current

[0045] I2: Second current

[0046] IB1: First bias current

[0047] IB2: Second bias current

[0048] IB3: Third bias current

[0049] IB4: Fourth bias current

[0050] IB5: Fifth bias current

[0051] IREF: Reference current

[0052] T1: first transistor

[0053] T2: Second transistor

[0054] T3: The third transistor

[0055] T4: The fourth transistor

[0056] T5: The fifth transistor

[0057] T6: Sixth transistor

[0058] T7: Seventh transistor

[0059] T8: The eighth transistor

[0060] T9: Ninth transistor

[0061] R1: first resistor

[0062] R2: Second resistor

[0063] R3: The third resistor

[0064] RPTC1: First positive temperature coefficient resistor

[0065] RPTC2: Second positive temperature coefficient resistor

[0066] RNTC1: First negative temperature coefficient resistor

[0067] RNTC2: Second negative temperature coefficient resistor

[0068] N1: first node

[0069] N2: Second node

[0070] N3: The third node

[0071] N4: The fourth node

[0072] N5: The fifth node

[0073] NREF: Reference Node

[0074] VDD: supply voltage

[0075] VREF: reference voltage

[0076] VSS: Ground

[0077] VGS,T5: Fifth gate-source voltage

[0078] VGS,T6: Sixth gate-source voltage

[0079] VSG,T5: Fifth source-gate voltage

[0080] VSG,T6: Sixth source-gate voltage

[0081] PW1: The first P-type well

[0082] PW2: Second P-type well

[0083] NW1: First N-type well

[0084] NW2: Second N-type well DETAILED DESCRIPTION

[0085] The following description is of embodiments of the present invention. Its purpose is to illustrate the general principles of the present invention and should not be construed as limiting the present invention, the scope of which shall be determined by the scope of the claims.

[0086] It is understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are merely used to distinguish different elements, components, regions, layers, and / or parts. Thus, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present application.

[0087] It is noteworthy that the content disclosed below can provide multiple embodiments or examples for practicing the different features of the present invention. The special component examples and arrangements described below are only used to briefly and concisely explain the spirit of the present invention and are not used to limit the scope of the present invention. In addition, the following description may reuse the same component symbols or text in multiple examples. However, the purpose of reuse is only to provide a simplified and clear description and is not used to limit the relationship between the multiple embodiments and / or configurations discussed below. In addition, the description of a feature connected to, coupled to and / or formed on another feature described in the following description may actually include multiple different embodiments, including direct contact between these features, or including other additional features formed between these features, etc., so that these features are not in direct contact.

[0088] Figure 2 A circuit diagram showing an electronic circuit according to an embodiment of the present invention is shown. Figure 2 As shown, the electronic circuit 200 includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 , a first resistor R1 , and a second resistor R2 .

[0089] The first transistor T1 includes a drain terminal, a source terminal, and a gate terminal. The drain terminal is coupled to the first node N1, the source terminal is coupled to the supply voltage VDD, and the gate terminal is coupled to the first node N1. In other words, the first transistor T1 is coupled in a diode configuration. The second transistor T2 includes a drain terminal, a source terminal, and a gate terminal. The drain terminal is coupled to the second node N2, the source terminal is coupled to the supply voltage VDD, and the gate terminal is coupled to the first node N1.

[0090] The third transistor T3 includes a drain terminal, a source terminal, and a gate terminal. The drain terminal is coupled to the third node N3, the source terminal is coupled to the supply voltage VDD, and the gate terminal is coupled to the fourth node N4. The fourth transistor T4 includes a drain terminal, a source terminal, and a gate terminal. The drain terminal is coupled to the fourth node N4, the source terminal is coupled to the supply voltage VDD, and the gate terminal is coupled to the fourth node N4. In other words, the fourth transistor T4 is coupled in a diode configuration.

[0091] The fifth transistor T5 includes a drain terminal, a source terminal, and a gate terminal. The drain terminal is coupled to the first node N1, the source terminal is coupled to the fifth node N5, and the gate terminal receives a reference voltage VREF. According to one embodiment of the present invention, the reference voltage VREF is a bandgap reference voltage generated by a bandgap circuit, wherein the bandgap voltage has a low temperature coefficient.

[0092] The sixth transistor T6 includes a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the second node N2, the source terminal is coupled to the ground terminal VSS, and the gate terminal is coupled to the third node N3. The seventh transistor T7 includes a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the fourth node N4, the source terminal is coupled to the ground terminal VSS, and the gate terminal is coupled to the second node N2. The first resistor R1 is coupled between the fifth node N5 and the ground terminal VSS, and the second resistor R2 is coupled between the third node N3 and the ground terminal VSS.

[0093] like Figure 2 As shown, the electronic circuit 200 further includes an eighth transistor T8 and a ninth transistor T9. The eighth transistor T8 includes a drain terminal, a source terminal, and a gate terminal. The drain terminal is coupled to the reference node NREF, the source terminal is coupled to the supply voltage VDD, and the gate terminal is coupled to the first node N1. The ninth transistor T9 includes a drain terminal, a source terminal, and a gate terminal. The drain terminal is coupled to the reference node NREF, the source terminal is coupled to the supply voltage VDD, and the gate terminal is coupled to the fourth node N4.

[0094] According to one embodiment of the present invention, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor T8, and the ninth transistor T9 are all P-type transistors, and the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all N-type transistors. According to one embodiment of the present invention, the first transistor T1, the second transistor T2, and the eighth transistor T8 form a current mirror, and the third transistor T3, the fourth transistor T4, and the ninth transistor T9 form a current mirror.

[0095] According to some embodiments of the present invention, the aspect ratio of the second transistor T2 may be N times that of the first transistor T1, and the aspect ratio of the eighth transistor T8 may be M times that of the first transistor T1. Therefore, the second bias current IB2 is N times the first bias current IB1, and the fourth bias current IB4 is M times the first bias current IB1. According to some embodiments of the present invention, the aspect ratio of the ninth transistor T9 may be P times the aspect ratio of the third transistor T3. Therefore, the fifth bias current IB5 is P times the third bias current IB3.

[0096] For simplicity of description, the following description assumes that the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor T8, and the ninth transistor T9 all have the same aspect ratio, and the fifth transistor T5 and the sixth transistor T6 also have the same aspect ratio. This is for simplicity and is not intended to be limiting in any way. In other words, the following description assumes that the first bias current IB1 is equal to the second bias current IB2 and the fourth bias current IB4, and the third bias current IB3 is equal to the fifth bias current IB5.

[0097] According to one embodiment of the present invention, when the fifth transistor T5 is turned on according to the reference voltage VREF, the fifth transistor T5 generates a first bias current IB1. The first bias current IB1 is expressed as Formula 1, where the fifth gate-source voltage of the fifth transistor T5 is VGS,T5:

[0098]

[0099] According to one embodiment of the present invention, when the aspect ratios of the first transistor T1 and the second transistor T2 are the same, the second bias current IB2 flowing through the sixth transistor T6 is equal to the first bias current IB1. The second bias current IB2 flows through the sixth transistor T6 to generate a sixth gate-source voltage VGS,T6 and a third bias current IB3 at the third node N3. The third bias current IB3 is expressed as follows:

[0100]

[0101] According to one embodiment of the present invention, when the first bias current IB1 is equal to the second bias current IB2 and the fourth bias current IB4 and the third bias current IB3 is equal to the fifth bias current IB5, the reference current IREF generated at the reference node NREF is as shown in Formula 3:

[0102]

[0103] According to one embodiment of the present invention, when the aspect ratios and threshold voltages of the fifth transistor T5 and the sixth transistor T6 match each other and the resistance values ​​of the first resistor R1 and the second resistor R2 are both equal to the resistance value R, the reference current IREF can be simplified as shown in Formula 4:

[0104]

[0105] According to one embodiment of the present invention, to ensure that the fifth gate-source voltage VGS,T5 is equal to the sixth gate-source voltage VGS,T6, the base terminal of the fifth transistor T5 is coupled to the fifth node N5, so that the fifth transistor T5 and the sixth transistor T6 have the same threshold voltage. Furthermore, to ensure that the aspect ratios of the fifth transistor T5 and the sixth transistor T6 match, the layout of the fifth transistor T5 and the sixth transistor T6 must be carefully considered, as will be described in detail below.

[0106] According to one embodiment of the present invention, when the resistance value R has a zero temperature coefficient, that is, when the resistance value R does not vary with temperature, the temperature coefficient of the reference current IREF is determined by the temperature coefficient of the reference voltage VREF. According to one embodiment of the present invention, the reference voltage VREF is a bandgap reference voltage generated by a bandgap circuit. Therefore, the reference voltage VREF has a very low temperature coefficient. In addition, the resistance value R has a zero temperature coefficient. Therefore, the temperature coefficient of the reference current IREF is determined by the temperature coefficient of the reference voltage VREF.

[0107] like Figure 2 As shown, the first resistor R1 further includes a first positive temperature coefficient resistor RPTC1 and a first negative temperature coefficient resistor RNTC1. The first positive temperature coefficient resistor RPTC1 has a first positive temperature coefficient, and the first negative temperature coefficient resistor RNTC1 has a first negative temperature coefficient. The first positive temperature coefficient resistor RPTC1 and the first negative temperature coefficient resistor RNTC1 are connected in series to form the first resistor R1.

[0108] According to one embodiment of the present invention, the resistance of the first positive temperature coefficient resistor RPTC1 increases as temperature rises, while the resistance of the first negative temperature coefficient resistor RNTC1 decreases as temperature rises. According to one embodiment of the present invention, the ratio of the resistance of the first positive temperature coefficient resistor RPTC1 to the resistance of the first negative temperature coefficient resistor RNTC1 is the inverse of the ratio of the first positive temperature coefficient to the first negative temperature coefficient, such that the temperature coefficient of the first resistor R1 decreases to zero.

[0109] Similarly, the second resistor R2 further includes a second positive temperature coefficient resistor RPTC2 and a second negative temperature coefficient resistor RNTC2. The second positive temperature coefficient resistor RPTC2 has a second positive temperature coefficient, and the second negative temperature coefficient resistor RNTC2 has a second negative temperature coefficient. The second positive temperature coefficient resistor RPTC2 and the second negative temperature coefficient resistor RNTC2 are connected in series to form the second resistor R2.

[0110] According to one embodiment of the present invention, the resistance of the second positive temperature coefficient resistor RPTC2 increases as temperature increases, while the resistance of the second negative temperature coefficient resistor RNTC2 decreases as temperature increases. According to one embodiment of the present invention, the ratio of the resistance of the second positive temperature coefficient resistor RPTC2 to the resistance of the second negative temperature coefficient resistor RNTC2 is the inverse of the ratio of the second positive temperature coefficient to the second negative temperature coefficient, thereby reducing the temperature coefficient of the second resistor R2 to zero.

[0111] like Figure 2 As shown, the seventh transistor T7 is used to stabilize the third bias current IB3. According to one embodiment of the present invention, when the third bias current IB3 increases, the sixth gate-source voltage VGS,T6 increases, thereby lowering the voltage at the second node N2. This reduces the conduction level of the seventh transistor T7, thereby increasing the voltage at the fourth node N4. The third transistor T3 reduces the third bias current IB3 in response to the increased voltage at the fourth node N4.

[0112] According to another embodiment of the present invention, when the third bias current IB3 decreases, the sixth gate-source voltage VGS,T6 decreases, thereby increasing the voltage at the second node N2. This increases the conduction level of the seventh transistor T7, thereby decreasing the voltage at the fourth node N4. The third transistor T3 increases the third bias current IB3 in response to the decreased voltage at the fourth node N4. In other words, the negative feedback circuit formed by the third transistor T3, the fourth transistor T4, and the seventh transistor T7 effectively stabilizes the voltage at the third node N3 and the third bias current IB3.

[0113] Figure 3 Showing the present invention Figure 2 The following description of the layout diagram 300 will be combined with Figure 2 The electronic circuit 200 is shown in FIG.

[0114] According to some embodiments of the present invention, because the first transistor T1, the second transistor T2, and the eighth transistor T8 form a current mirror, the first transistor T1, the second transistor T2, and the eighth transistor T8 must be matched to maintain the ratio between the first bias current IB1, the second bias current IB2, and the fourth bias current IB4. Furthermore, the third transistor T3, the fourth transistor T4, and the ninth transistor T9 must be matched to maintain the ratio between the third bias current IB3 and the fifth bias current IB5. Furthermore, the fifth transistor T5 and the sixth transistor T6 must be matched, and the ratio of the aspect ratio of the fifth transistor T5 to the aspect ratio of the sixth transistor T6 must be equal to the ratio of the aspect ratio of the first transistor T1 to the aspect ratio of the second transistor T2.

[0115] like Figure 3 As shown, in order to maintain mutual matching between the first transistor T1, the second transistor T2, and the eighth transistor T8 despite process variations, the first transistor T1, the second transistor T2, and the eighth transistor T8 are laid out in a common centroid manner. Similarly, the third transistor T3, the fourth transistor T4, and the ninth transistor T9 are also laid out in a common centroid manner.

[0116] like Figure 3 As shown in the embodiment, since the aspect ratios of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 are all the same as an example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 are arranged together.

[0117] According to an embodiment of the present invention, in order to make the fifth gate-source voltage VGS,T5 of the fifth transistor T5 and the sixth gate-source voltage VGS,T6 of the sixth transistor T6 cancel each other in Formula 4 and reduce the temperature coefficient of the reference current IREF, the aspect ratio and the threshold voltage of the fifth transistor T5 and the sixth transistor T6 must match each other. Figure 2 As shown, the base terminal of the fifth transistor T5 is coupled to the fifth node N5 to reduce the body effect of the fifth transistor T5, so that the threshold voltage of the fifth transistor T5 is substantially the same as the threshold voltage of the sixth transistor T6. In addition, since the fifth transistor T5 is an N-type transistor, Figure 3 The fifth transistor T5 is formed in the first P-well PW1.

[0118] To match the aspect ratios of the fifth transistor T5 and the sixth transistor T6, the sixth transistor T6 is also formed in the second P-well PW2. Furthermore, the first P-well PW1 and the second P-well PW2 are arranged concentrically. This allows the aspect ratios and threshold voltages of the fifth transistor T5 and the sixth transistor T6 to remain matched despite process variations. According to one embodiment of the present invention, the first P-well PW1 is coupled to the fifth node N5, and the second P-well PW2 is coupled to the ground terminal VSS.

[0119] According to an embodiment of the present invention, since the resistance value of the first resistor R1 and the resistance value of the second resistor R2 have the same resistance value R in Formula 4, Figure 3 The first resistor R1 and the second resistor R2 are also arranged in a concentric manner, so that the resistance values ​​of the first resistor R1 and the second resistor R2 remain substantially the same under process variations.

[0120] Figure 4 A circuit diagram showing an electronic circuit according to another embodiment of the present invention is shown. Figure 4 As shown, the electronic circuit 400 is compared with Figure 2 The electronic circuit 200 further includes a third resistor R3, wherein the third resistor R3 is coupled between a reference node NREF and a ground terminal VSS. According to other embodiments of the present invention, the third resistor R3, like the first resistor R1 and the second resistor R2, utilizes a resistor with a positive temperature coefficient and a resistor with a negative temperature coefficient connected in series, thereby reducing the temperature coefficient of the third resistor R3 to zero. This description is omitted here.

[0121] According to some embodiments of the present invention, the electronic circuit 400 can generate an output voltage VOUT at a reference node NREF by selecting the third resistor R3. The temperature coefficient of the output voltage VOUT is determined by the temperature coefficient of the reference voltage VREF, and the output voltage VOUT is less than the supply voltage VDD minus the source-drain voltage of the eighth transistor T8 or the ninth transistor T9. In other words, when the reference voltage VREF is a bandgap voltage generated by a bandgap circuit, the electronic circuit 400 can convert the reference voltage VREF to an output voltage VOUT of any voltage value by using the third resistor R3 having a low temperature coefficient, while maintaining stable operation of the eighth transistor T8 and the ninth transistor T9 in the saturation region. The temperature coefficient of the output voltage VOUT is determined by the temperature coefficient of the reference voltage VREF.

[0122] Figure 5 A circuit diagram showing an electronic circuit according to another embodiment of the present invention is shown. Figure 5 The electronic circuit 500 and Figure 2Compared to the electronic circuit 200, the electronic circuit 500 is similar to the electronic circuit 200. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor T8, and the ninth transistor T9 of the electronic circuit 500 are all N-type transistors, while the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 of the electronic circuit 500 are all P-type transistors. Furthermore, the first resistor R1 of the electronic circuit 500 is coupled between the supply voltage VDD and the fifth node N5, and the second resistor R2 of the electronic circuit 500 is coupled between the supply voltage VDD and the third node N3.

[0123] According to one embodiment of the present invention, when the fifth transistor T5 is turned on according to the reference voltage VREF, the fifth transistor T5 generates a first bias current IB1. The first bias current IB1 is expressed as Equation 5, where the fifth source-gate voltage of the fifth transistor T5 is VSG,T5:

[0124]

[0125] According to one embodiment of the present invention, when the first transistor T1 and the second transistor T2 have the same aspect ratio, the second bias current IB2 flowing through the sixth transistor T6 is equal to the first bias current IB1. The second bias current IB2 flows through the sixth transistor T6 to generate a sixth source-gate voltage VSG,T6 and a third bias current IB3 at the third node N3. The third bias current IB3 is expressed as Equation 6:

[0126]

[0127] According to one embodiment of the present invention, when the first bias current IB1 is equal to the second bias current IB2 and the fourth bias current IB4 and the third bias current IB3 is equal to the fifth bias current IB5, the reference current IREF generated at the reference node NREF is as shown in Formula 7:

[0128]

[0129] According to one embodiment of the present invention, when the aspect ratios and threshold voltages of the fifth transistor T5 and the sixth transistor T6 match each other and the resistance values ​​of the first resistor R1 and the second resistor R2 are both equal to the resistance value R, the reference current IREF can be simplified as shown in Formula 8:

[0130]

[0131] According to one embodiment of the present invention, to ensure that the fifth source-gate voltage VSG,T5 is equal to the sixth source-gate voltage VSG,T6, the base terminal of the fifth transistor T5 is coupled to the fifth node N5, so that the fifth transistor T5 and the sixth transistor T6 have the same threshold voltage. Furthermore, to ensure that the aspect ratios of the fifth transistor T5 and the sixth transistor T6 match, the layout of the fifth transistor T5 and the sixth transistor T6 must also be carefully considered.

[0132] like Figure 5 As shown, the first resistor R1 includes a first positive temperature coefficient resistor RPTC1 and a first negative temperature coefficient resistor RNTC1. The ratio of the resistance value of the first positive temperature coefficient resistor RPTC1 to the resistance value of the first negative temperature coefficient resistor RNTC1 is the inverse of the ratio of the first positive temperature coefficient to the first negative temperature coefficient, thereby reducing the temperature coefficient of the first resistor R1 to zero. The second resistor R2 includes a second positive temperature coefficient resistor RPTC2 and a second negative temperature coefficient resistor RNTC2. The ratio of the resistance value of the second positive temperature coefficient resistor RPTC2 to the resistance value of the second negative temperature coefficient resistor RNTC2 is the inverse of the ratio of the second positive temperature coefficient to the second negative temperature coefficient, thereby reducing the temperature coefficient of the second resistor R2 to zero.

[0133] According to one embodiment of the present invention, Figure 5 As shown, the negative feedback circuit formed by the third transistor T3, the fourth transistor T4 and the seventh transistor T7 can effectively stabilize the voltage of the third node N3 and the third bias current IB3. Figure 2 The seventh transistor T7 is described above and will not be repeated here.

[0134] Figure 6 Showing the present invention Figure 5 The following description of the layout diagram 600 will be combined with Figure 5 The electronic circuit 500 is shown in FIG.

[0135] According to some embodiments of the present invention, because the first transistor T1, the second transistor T2, and the eighth transistor T8 form a current mirror, the first transistor T1, the second transistor T2, and the eighth transistor T8 must be matched to maintain the ratio between the first bias current IB1, the second bias current IB2, and the fourth bias current IB4. Furthermore, the third transistor T3, the fourth transistor T4, and the ninth transistor T9 must be matched to maintain the ratio between the third bias current IB3 and the fifth bias current IB5. Furthermore, the fifth transistor T5 and the sixth transistor T6 must be matched, and the ratio of the aspect ratio of the fifth transistor T5 to the aspect ratio of the sixth transistor T6 must be equal to the ratio of the aspect ratio of the first transistor T1 to the aspect ratio of the second transistor T2.

[0136] like Figure 6 As shown, the first transistor T1, the second transistor T2, and the eighth transistor T8 are laid out in a concentric manner, and the third transistor T3, the fourth transistor T4, and the ninth transistor T9 are also laid out in a concentric manner, so that in the case of process variation, the ratio of the aspect ratios of the first transistor T1, the second transistor T2, and the eighth transistor T8, and the ratio of the aspect ratios of the third transistor T3, the fourth transistor T4, and the ninth transistor T9 can be maintained constant.

[0137] like Figure 6 As shown in the embodiment, since the aspect ratios of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 are all the same as an example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 are arranged together.

[0138] According to an embodiment of the present invention, in order to make the fifth source-gate voltage VSG,T5 of the fifth transistor T5 and the sixth source-gate voltage VSG,T6 of the sixth transistor T6 cancel each other in Formula 8 and reduce the temperature coefficient of the reference current IREF, the aspect ratio and the threshold voltage of the fifth transistor T5 and the sixth transistor T6 must match each other. Figure 5 As shown, the base terminal of the fifth transistor T5 is coupled to the fifth node N5 to reduce the base effect of the fifth transistor T5. In addition, since the fifth transistor T5 is a P-type transistor, Figure 6 The fifth transistor T5 is formed in the first N-type well NW1.

[0139] To match the aspect ratios of the fifth transistor T5 and the sixth transistor T6, the sixth transistor T6 is also formed in the second N-well NW2. The first N-well NW1 and the second N-well NW2 are arranged concentrically. This allows the aspect ratios and threshold voltages of the fifth transistor T5 and the sixth transistor T6 to remain matched despite process variations. According to one embodiment of the present invention, the first N-well NW1 is coupled to the fifth node N5, and the second N-well NW2 is coupled to the supply voltage VDD.

[0140] According to one embodiment of the present invention, Figure 6 As shown, the first resistor R1 and the second resistor R2 are arranged in a concentric manner, so that the resistance value of the first resistor R1 and the resistance value of the second resistor R2 remain substantially the same under process variations.

[0141] Figure 7A circuit diagram showing an electronic circuit according to another embodiment of the present invention is shown. Figure 7 As shown, the electronic circuit 700 is compared with Figure 5 The electronic circuit 500 further includes a third resistor R3, wherein the third resistor R3 is coupled between a reference node NREF and a supply voltage VDD. According to other embodiments of the present invention, the third resistor R3, like the first resistor R1 and the second resistor R2, utilizes a resistor with a positive temperature coefficient and a resistor with a negative temperature coefficient connected in series, thereby reducing the temperature coefficient of the third resistor R3 to zero. This description is omitted here.

[0142] According to some embodiments of the present invention, the electronic circuit 700 can generate an output voltage VOUT at a reference node NREF by selecting the third resistor R3. The temperature coefficient of the output voltage VOUT is determined by the temperature coefficient of the reference voltage VREF. The output voltage VOUT can be any voltage value that is not less than the source-drain voltage of the eighth transistor T8 or the ninth transistor T9 and less than the supply voltage VDD. In other words, while maintaining the eighth transistor T8 and the ninth transistor T9 operating stably in the saturation region, the output voltage VOUT can be any voltage between the supply voltage VDD and the ground terminal VSS.

[0143] The present invention provides an electronic circuit for generating a high-precision, low-temperature-coefficient reference current. Because the electronic circuit does not require an operational amplifier, it significantly reduces circuit area and power consumption, and can operate independently without a current source. Furthermore, by matching transistors and canceling the temperature coefficients of resistors, the temperature coefficient of the reference current is determined by the reference voltage. Furthermore, the electronic circuit can operate at lower supply voltages and can convert the bandgap voltage to other voltages by selecting resistor values.

[0144] Although the embodiments of the present application and their advantages have been disclosed as above, it should be understood that any person skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present application. In addition, the scope of protection of the present application is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the relevant technical field can understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of some embodiments of the present application. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to some embodiments of the present application. Therefore, the scope of protection of the present application includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present application also includes the combination of each claim and embodiment.

Claims

1. An electronic circuit, characterized in that include: a first transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a first node, the source terminal is coupled to a supply voltage, and the gate terminal is coupled to the first node; a second transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a second node, the source terminal is coupled to the supply voltage, and the gate terminal is coupled to the first node; a third transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a third node, the source terminal is coupled to the supply voltage, and the gate terminal is coupled to a fourth node; a fourth transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the fourth node, the source terminal is coupled to the supply voltage, and the gate terminal is coupled to the fourth node; a fifth transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the first node, the source terminal is coupled to a fifth node, and the gate terminal receives a reference voltage; a sixth transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the second node, the source terminal is coupled to a ground terminal, and the gate terminal is coupled to the third node; a seventh transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the fourth node, the source terminal is coupled to the ground terminal, and the gate terminal is coupled to the second node; a first resistor coupled between the fifth node and the ground; as well as A second resistor is coupled between the third node and the ground.

2. The electronic circuit according to claim 1, wherein: Also includes: an eighth transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a reference node, the source terminal is coupled to the supply voltage, and the gate terminal is coupled to the first node; as well as a ninth transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the reference node, the source terminal is coupled to the supply voltage, and the gate terminal is coupled to the fourth node.

3. The electronic circuit according to claim 2, wherein: The first transistor, the second transistor, the third transistor, the fourth transistor, the eighth transistor, and the ninth transistor are P-type transistors, and the fifth transistor, the sixth transistor, and the seventh transistor are N-type transistors.

4. The electronic circuit according to claim 3, wherein: Also includes: A third resistor is coupled between the reference node and the ground, wherein an output voltage is generated at the reference node, wherein a temperature coefficient of the output voltage is determined by the reference voltage.

5. The electronic circuit according to claim 2, wherein: The eighth transistor and the ninth transistor generate a reference current at the reference node, wherein the temperature coefficient of the reference current is determined by the temperature coefficient of the reference voltage, wherein the first transistor, the second transistor and the eighth transistor are arranged in a concentric manner, and the third transistor, the fourth transistor and the ninth transistor are arranged in a concentric manner.

6. The electronic circuit according to claim 1, wherein: The base terminal of the fifth transistor is coupled to the fifth node, and the base terminal of the sixth transistor is coupled to the ground terminal, wherein the fifth transistor is formed in a first P-type well coupled to the fifth node, and the sixth transistor is formed in a second P-type well coupled to the ground terminal, wherein the first P-type well and the second P-type well are arranged in a concentric manner.

7. The electronic circuit according to claim 1, wherein: The first resistor includes: a first sub-resistor having a first positive temperature coefficient; and A second sub-resistor has a first negative temperature coefficient, wherein the first sub-resistor and the second sub-resistor are connected in series to form the first resistor.

8. The electronic circuit according to claim 7, wherein: The ratio of the resistance value of the first sub-resistor to the resistance value of the second sub-resistor is a first resistance ratio, and the ratio of the first positive temperature coefficient to the first negative temperature coefficient is a first temperature coefficient ratio, wherein the first resistance ratio is the inverse of the first temperature coefficient ratio to reduce the temperature coefficient of the first resistor.

9. The electronic circuit according to claim 7, wherein: The second resistor includes: a third sub-resistor having a second positive temperature coefficient; and A fourth sub-resistor has a second negative temperature coefficient, wherein the third sub-resistor and the fourth sub-resistor are connected in series to form the second resistor.

10. The electronic circuit according to claim 9, characterized in that The ratio of the resistance value of the third sub-resistor to the resistance value of the fourth sub-resistor is a second resistance ratio, and the ratio of the second positive temperature coefficient to the second negative temperature coefficient is a second temperature coefficient ratio, wherein the second resistance ratio is the inverse of the second temperature coefficient ratio to reduce the temperature coefficient of the second resistor.

11. An electronic circuit, characterized in that: include: a first transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a first node, the source terminal is coupled to a ground terminal, and the gate terminal is coupled to the first node; a second transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a second node, the source terminal is coupled to the ground terminal, and the gate terminal is coupled to the first node; a third transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a third node, the source terminal is coupled to the ground terminal, and the gate terminal is coupled to a fourth node; a fourth transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the fourth node, the source terminal is coupled to the ground terminal, and the gate terminal is coupled to the fourth node; a fifth transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the first node, the source terminal is coupled to a fifth node, and the gate terminal receives a reference voltage; a sixth transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the second node, the source terminal is coupled to a supply voltage, and the gate terminal is coupled to the third node; a seventh transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the fourth node, the source terminal is coupled to the supply voltage, and the gate terminal is coupled to the second node; a first resistor coupled between the fifth node and the supply voltage; as well as A second resistor is coupled between the third node and the supply voltage.

12. The electronic circuit according to claim 11, wherein: Also includes: an eighth transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to a reference node, the source terminal is coupled to the ground terminal, and the gate terminal is coupled to the first node; as well as a ninth transistor comprising a drain terminal, a source terminal, and a gate terminal, wherein the drain terminal is coupled to the reference node, the source terminal is coupled to the ground terminal, and the gate terminal is coupled to the fourth node.

13. The electronic circuit according to claim 12, wherein: The first transistor, the second transistor, the third transistor, the fourth transistor, the eighth transistor, and the ninth transistor are N-type transistors, and the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors.

14. The electronic circuit according to claim 13, wherein: Also includes: A third resistor is coupled between the reference node and the supply voltage, wherein an output voltage is generated at the reference node, wherein a temperature coefficient of the output voltage is determined by the reference voltage.

15. The electronic circuit according to claim 12, wherein: The eighth transistor and the ninth transistor generate a reference current at the reference node, wherein the temperature coefficient of the reference current is determined by the temperature coefficient of the reference voltage, wherein the first transistor, the second transistor and the eighth transistor are arranged in a concentric manner, and the third transistor, the fourth transistor and the ninth transistor are arranged in a concentric manner.

16. The electronic circuit according to claim 11, wherein: The base terminal of the fifth transistor is coupled to the fifth node, and the base terminal of the sixth transistor is coupled to the supply voltage, wherein the fifth transistor is formed in a first N-type well coupled to the fifth node, and the sixth transistor is formed in a second N-type well coupled to the supply voltage, wherein the first N-type well and the second N-type well are arranged in a concentric manner.

17. The electronic circuit according to claim 11, wherein: The first resistor includes: a first sub-resistor having a first positive temperature coefficient; and A second sub-resistor has a first negative temperature coefficient, wherein the first sub-resistor and the second sub-resistor are connected in series to form the first resistor.

18. The electronic circuit according to claim 17, wherein: The ratio of the resistance value of the first sub-resistor to the resistance value of the second sub-resistor is a first resistance ratio, and the ratio of the first positive temperature coefficient to the first negative temperature coefficient is a first temperature coefficient ratio, wherein the first resistance ratio is the inverse of the first temperature coefficient ratio to reduce the temperature coefficient of the first resistor.

19. The electronic circuit according to claim 17, wherein: The second resistor includes: a third sub-resistor having a second positive temperature coefficient; and A fourth sub-resistor has a second negative temperature coefficient, wherein the third sub-resistor and the fourth sub-resistor are connected in series to form the second resistor.

20. The electronic circuit according to claim 19, wherein: The ratio of the resistance value of the third sub-resistor to the resistance value of the fourth sub-resistor is a second resistance ratio, and the ratio of the second positive temperature coefficient to the second negative temperature coefficient is a second temperature coefficient ratio, wherein the second resistance ratio is the inverse of the second temperature coefficient ratio to reduce the temperature coefficient of the second resistor.

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