A data path detection method, device, apparatus and storage medium

Abstract

The present disclosure provides a data path detection method, device, equipment and storage medium, which is applied to the detection process of the data path of a semiconductor integrated circuit. The data path detection method comprises: disconnecting, by a detection device, a global data line and a local data line in the data path, writing test data to the global data line in the data path through a write port of the data path, reading, by the detection device, target data of the global data line under a preset condition, and detecting defects of the data path according to the test data and the target data. By using the data path detection method in the present disclosure, even if there is a problem in the array unit of the semiconductor integrated circuit, the data path can still be tested for defects, the testing effect is better, and the overall testing time of the semiconductor integrated circuit is saved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a data path detection method, device, apparatus and storage medium. BACKGROUND

[0002] Dynamic random access memory (DRAM) is a chip with a high-density repetitive memory array unit. With the increasing demand of application end, the memory array unit is continuously miniaturized, which poses great challenges to manufacturing process.

[0003] For dynamic random access memory, if there is a problem in the internal memory array unit, it is usually difficult to test the problem, and it is impossible to determine whether it is a write data path fault, a read data path fault, or a control circuit fault, which affects the overall research and development time of the product. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] The present disclosure provides a data path detection method, device, apparatus and storage medium.

[0006] According to a first aspect of some embodiments of the present disclosure, a data path detection method is provided, the data path detection method comprising:

[0007] The detection device disconnects the connection between the global data line and the local data line in the data path;

[0008] The detection device writes test data to the global data line in the data path through the write port of the data path;

[0009] Under a preset condition, the detection device reads target data of the global data line;

[0010] The detection device detects defects of the data path according to the test data and the target data.

[0011] According to some embodiments of the present disclosure, the detection device disconnects the connection between the global data line and the local data line in the data path, comprising:

[0012] The detection device sends a first instruction to the local read-write conversion module;

[0013] The local read-write conversion module disconnects the connection between the global data line and the local data line based on the received first instruction.

[0014] According to some embodiments of the present disclosure, the detection device reads the target data of the global data line under the preset condition, including:

[0015] The detection device switches to a reading mode, and turns off a write driving circuit of the global data line, so that the global data line is floating;

[0016] After waiting for a preset time length, the detection device reads the target data of the global data line, and records and tests a timing of the data path.

[0017] According to some embodiments of the present disclosure, the detection device disconnects the global data line and the local data line in the data path, including:

[0018] The detection device sends a second instruction to the local read-write conversion module;

[0019] The local read-write conversion module disconnects the global data line and the local data line based on the received second instruction, and keeps a write driving circuit of the global data line enabled, so that data on the global data line is kept.

[0020] According to some embodiments of the present disclosure, the detection device reads the target data of the global data line under the preset condition, including:

[0021] The detection device switches to a reading mode;

[0022] The detection device reads the target data of the global data line, and records and tests a timing of the data path.

[0023] According to some embodiments of the present disclosure, the detection device detects a defect of the data path according to the test data and the target data, including:

[0024] If the test data is inconsistent with the target data, the detection device determines that the data path has a defect.

[0025] According to some embodiments of the present disclosure, the defect includes a short circuit defect or an open circuit defect.

[0026] A second aspect of the present disclosure provides a data path detection device, including:

[0027] A control module is configured to disconnect a global data line and a local data line in the data path;

[0028] A write module is configured to write test data to the global data line in the data path through a write port of the data path;

[0029] a reading module, configured to read target data of the global data line under a preset condition;

[0030] a judging module, configured to detect defects of the data path according to the test data and the target data.

[0031] According to some embodiments of the present disclosure, the control module is configured to:

[0032] send a first instruction to the local read-write conversion module to disconnect the global data line from the local data line.

[0033] According to some embodiments of the present disclosure, the control module is configured to:

[0034] switch to a reading mode, and turn off a write driving circuit of the global data line so that the global data line is floating.

[0035] The reading module is configured to:

[0036] After waiting for a preset time length, read the target data of the global data line, and record and test a timing of the data path.

[0037] According to some embodiments of the present disclosure, the control module is configured to:

[0038] send a second instruction to the local read-write conversion module to disconnect the global data line from the local data line, and keep a write driving circuit of the global data line enabled so that data on the global data line is kept.

[0039] According to some embodiments of the present disclosure, the control module is configured to:

[0040] switch to a reading mode;

[0041] The reading module is configured to:

[0042] read the target data of the global data line, and record and test a timing of the data path.

[0043] According to some embodiments of the present disclosure, the judging module is configured to:

[0044] if the test data is inconsistent with the target data, judge that the data path has defects.

[0045] A third aspect of the present disclosure provides a data path detection device, which comprises:

[0046] a processor;

[0047] a memory for storing processor-executable instructions;

[0048] The processor is configured to perform the data path detection method according to the first aspect.

[0049] According to a fourth aspect of the embodiments of the present disclosure, a non-transitory computer readable storage medium is provided, when instructions in the storage medium are executed by a processor of a terminal, the detection device is enabled to perform the data path detection method according to the first aspect.

[0050] The data path detection method, device, equipment and storage medium provided by the embodiments of the present disclosure can still test whether the data path has defects even if there is a problem in the array unit of the semiconductor integrated circuit, the testing effect is better, and the overall testing time of the semiconductor integrated circuit is saved.

[0051] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0052] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings, like reference numerals are used to represent like elements throughout. The accompanying drawings are of some embodiments of the present disclosure and not all embodiments. Other drawings can be derived from these drawings by those skilled in the art without paying creative labor.

[0053] Figure 1 is a structural diagram of a dynamic random access memory according to an exemplary embodiment.

[0054] Figure 2 is a flowchart of a data input process according to an exemplary embodiment.

[0055] Figure 3 is a circuit diagram of a write driving circuit of a data path detection device according to an exemplary embodiment.

[0056] Figure 4 is a circuit diagram of a read circuit of a data path detection device according to an exemplary embodiment.

[0057] Figure 5 is a flowchart of a data path detection method according to an exemplary embodiment.

[0058] Figure 6 is a flowchart of a data path detection method according to an exemplary embodiment.

[0059] Figure 7 is a flowchart of a data path detection device according to an exemplary embodiment.

[0060] Figure 8 is a port control map of a data path detection apparatus according to an example embodiment.

[0061] Figure 9 is a port control map of a data path detection apparatus according to an example embodiment.

[0062] Figure 10 is a port control map of a data path detection apparatus according to an example embodiment.

[0063] Figure 11 is a block diagram of a data path detection apparatus according to an example embodiment.

[0064] Figure 12 is a block diagram of a data path detection apparatus according to an example embodiment. DETAILED DESCRIPTION

[0065] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any manner without conflict.

[0066] Dynamic random access memory (DRAM) is a chip with a high-density repetitive memory array unit. As the demand of application end is improved, the memory array unit is continuously miniaturized, which brings great challenge to the manufacturing process.

[0067] In the process of developing a new process, long-time and multiple iterations are needed to ensure that the memory array unit can be read and written. For dynamic random access memory, if there is a problem in the internal memory array unit, it is usually difficult to test the problem, and it is impossible to determine whether it is a write data path fault, a read data path fault, or a control circuit fault, which affects the overall development time of the product.

[0068] To solve the above problems, the present disclosure provides a data path detection method applied to the detection process of the data path of a semiconductor integrated circuit. The data path detection method can still test whether the data path has defects even if there is a problem in the array unit of the semiconductor integrated circuit, the test effect is better, and the overall test time of the semiconductor integrated circuit is saved.

[0069] Before the technical content related to the present disclosure is described, the overall structure of a dynamic random access memory is briefly described as follows: Figure 1 As shown in FIG. 1, it is a typical structure of a dynamic random access memory, showing the process of storing write data from an external data port DQ to a memory array, and reading from the memory array to the external data port DQ. In this process, generally six steps are required:

[0070] 1. Bidirectional drive channel between Dbus and Bbus;

[0071] 2. Bidirectional drive channel between Bbus and Cbus;

[0072] 3. Bidirectional drive channel on Cbus transmission line;

[0073] 4. Bidirectional driver between Cbus and Abus;

[0074] 5. Drive channel and sense amplifier circuit between Abus and data line YIO;

[0075] 6. Drive channel and sense amplifier circuit between data line YIO and data line LIO.

[0076] The control method in the present disclosure is mainly applied in steps 5 and 6 described above. For step 5, it involves write drive circuit and read circuit, as shown in FIG. 2, which shows the circuit diagram of the write drive circuit of the drive channel involved in step 5. As shown in FIG. 3, it shows the circuit diagram of the read circuit of the drive channel involved in step 5. Figure 3 Figure 4 In the write drive circuit, the control end of the write drive circuit needs to be opened first, and then the write of the target data is performed. As shown in FIG. 4, in an example, the EQ end potential is pulled low, and the WrEn end potential is raised, which opens the write data enable in the write drive circuit. At this time, the write drive circuit can input test data through the test data port, write the test data to the data line YIO, and read the target data through the YIO and YIO_N ports. The test data port can be represented as a port connected to Abus in the structure shown in FIG. 5. In another example, if the EQ end potential is pulled high, and the WrEn end potential is lowered, the enable of writing data to the data line YIO is turned off, and the write drive circuit at this time cannot perform data writing.

[0077] In the read circuit, as shown in FIG. 6 and FIG. 7, Figure 3 Figure 1 and

[0078] In the read circuit, as shown in FIG. 6 and FIG. 7, Figure 3 and Figure 4 ​​As shown, the data lines YIO and YIO_N ports of the write driving circuit are connected to the data lines YIO and YIO_N ports of the read circuit one by one, so that the target data in the write driving circuit is read out by the ports, and can be amplified by the sense amplifier circuit 333, and then transmitted to Abus through the data port.

[0079] According to an exemplary embodiment, as Figure 5 As shown, the embodiment provides a data path detection method, including the following steps:

[0080] S110, the detection device disconnects the connection between the global data line and the local data line in the data path.

[0081] S120, the detection device writes test data to the global data line in the data path through the write port of the data path.

[0082] S130, under a preset condition, the detection device reads the target data of the global data line.

[0083] S140, the detection device detects the defects of the data path according to the test data and the target data.

[0084] The detection method in the embodiment needs to use the detection device for detection. In the detection process, the detection device is connected with the dynamic random access memory, writes signals to the dynamic random access memory or reads signals from the dynamic random access memory, so as to detect the dynamic random access memory.

[0085] In step S110, in order to clearly know whether there are defects in each part of the data path, it is necessary to disconnect the connection between all data lines and local data lines in the detection process. The global data line is the data line YIO shown in Figure 1 , and the local data line is the data line LIO shown in Figure 1 . After disconnecting the local data line and the global data line, different processing methods can be used for the global data line, such as suspending the global data line, or keeping the write driving circuit of the global data line enabled to detect the defects in the data path comprehensively.

[0086] In step S140, after the test data and the target data are obtained, whether the data path has a defect can be detected according to the test data and the target data. If the test data and the target data are inconsistent, it indicates that an error occurs in the test data writing process through the data path or an error occurs in the target data reading process through the data path, resulting in a change of the data, that is, the data path has a defect. If the test data and the target data are consistent, it indicates that everything is normal in the test data writing process through the data path and everything is normal in the target data reading process through the data path, that is, the data path has no defect.

[0087] The defect of the data path can be a short-circuit defect or an open-circuit defect, and the detection device can further determine the defect in the subsequent detection.

[0088] The data path detection method in the embodiment can disconnect the global data line and the local data line during detection, and can test whether the data path has a defect even if there is a problem in the array unit of the semiconductor integrated circuit, so that the testing effect is better and the overall testing time of the semiconductor integrated circuit is saved.

[0089] According to an example embodiment, as shown in Figure 6 The data path detection method in the embodiment includes the following steps:

[0090] S210, the detection device sends a first instruction to the local read-write conversion module.

[0091] S220, the local read-write conversion module disconnects the global data line and the local data line based on the received first instruction.

[0092] S230, the detection device writes test data to the global data line in the data path through the write port of the data path.

[0093] S240, the detection device switches to a reading mode and closes the write driving circuit of the global data line, so that the global data line is floating.

[0094] S250, after waiting for a preset time length, the detection device reads the target data of the global data line and records and tests the timing of the data path.

[0095] S260, the detection device detects the defect of the data path according to the test data and the target data.

[0096] In step S210, the local read-write conversion module is part of a dynamic random access memory, and the local read-write conversion module can connect or disconnect the global data line YIO and the local data line LIO. As Figure 2In the data input process shown in the figure, the data path can be transmitted in both directions, and the data goes through Dbus to Bbus and then to Cbus. Figure 1 As shown in the figure, input data is bidirectionally transmitted between the high eight bits <15:8> and the low eight bits <0:7> on the Cbus, and then to the Abus through the global data line YIO and the local data line LIO connected to the Abus. Figure 2 As shown, LioWrEn and LioRdEn are enable signals for the local read-write conversion module between the global data line YIO and the local data line LIO. When these enable signals change, they affect the connection between the global data line YIO and the local data line LIO. Therefore, the detection device sends a first instruction to the local read-write conversion module. Based on this instruction, the local read-write conversion module disables LioWrEn and LioRdEn, thereby severing the connection between the global data line YIO and the local data line LIO.

[0097] In step S220, when the local read-write conversion module receives the first instruction, it controls the global data line YIO of the dynamic random access memory to be disconnected from the local data line LIO. Figure 8 、 Figure 9 and Figure 10 As shown, the first instruction sent by the detection device enables tmReadYio <0> is a high potential, Figure 8 、 Figure 9 and Figure 10 In the logic circuit, LioWrEN and LioRdEN outputs are low, that is, the enable signal of the local read-write conversion circuit is invalid, thereby cutting off the connection between the global data line YIO and the local data line LIO.

[0098] In step S230, when the global data line YIO is disconnected from the local data line LIO, the detection device issues an activation command (Active cmd) to open a word line. Then, the detection device issues a write command (Write cmd) to write the test data into the global data line YIO via the data path. Figure 3 As shown, a write command pulls the potential at WrEn high and the potential at EQ low. This opens the data write path. Once the test device issues a write command (Write cmd), test data can be written through the data path.

[0099] In step S240, the detection device issues a read command (Read cmd), switches from the write mode to the read mode, turns off the write drive circuit of the global data line YIO, and makes the global data line YIO suspended. Figure 10As shown, when switching to the read mode, WrtMode is low, YioEQ outputs high, YioWrEn outputs low, and the write driving circuit of the global data line YIO is closed, so as to realize floating of the global data line YIO.

[0100] In step S250, a preset time length is waited according to the detection requirement. The preset time length is not limited in the embodiment, and can be adjusted according to the detection requirement. During the waiting process, the global data line YIO is always kept floating. Then, the detection device sends a Read cmd instruction to read the target data on the global data line YIO, and records and tests the timing of the data path, so as to prepare for subsequent analysis of the detection result.

[0101] According to an example embodiment, as shown in Figure 7 The data path detection method in the embodiment includes the following steps:

[0102] S310, the detection device sends a second instruction to the local read-write conversion module.

[0103] S320, the local read-write conversion module disconnects the global data line and the local data line based on the received second instruction.

[0104] S330, the detection device writes test data to the global data line in the data path through the write port of the data path.

[0105] S340, the detection device switches to the read mode and keeps the write driving circuit of the global data line, so that the global data line is always turned on.

[0106] S350, after waiting for a preset time length, the detection device reads the target data of the global data line, and records and tests the timing of the data path.

[0107] S360, the detection device detects defects of the data path according to the test data and the target data.

[0108] In step S310, the local read-write conversion module is part of a dynamic random access memory. The local read-write module connects the global data line YIO and the local data line LIO. Data can be written into the global data line YIO and the local data line LIO through a bidirectional data input path as shown in Figure 2 that is, data passes through Dbus to Bbus and then to Cbus, as shown in Figure 1As shown, the input data is transmitted between the high eight bits <15:8> and the low eight bits <0:7> on the Cbus, and then transmitted to the Abus through the global data line YIO and the local data line LIO connected to the Abus. The LioWrEn and LioRdEn are the enable signals of the local read-write conversion module between the global data line YIO and the local data line LIO, and the connection between the global data line YIO and the local data line LIO can be connected or disconnected by controlling the enable signals. Thus, when the second instruction sent by the detection device to the local read-write conversion module, the instruction is used to disable the LioWrEn and LioRdEn, thereby cutting off the connection between the global data line YIO and the local data line LIO.

[0109] In step S320, the local read-write conversion module receives the second instruction to make tmReadYio<0> and tmReadYio<1> both high, as shown in the logic circuit of Figure 8 、 Figure 9 and Figure 10 , the LioWrEN and LioRdEN output are low, i.e. the enable signal of the local read-write conversion circuit is invalid, thereby cutting off the connection between the global data line YIO and the local data line LIO.

[0110] In step S330, the detection device writes the test data to the global data line YIO in the data path through the write port of the data path. In the state that the global data line YIO is disconnected from the local data line LIO, the detection device will issue an activation instruction (Active cmd) to open a word line. Then, the detection device issues a write instruction (Write cmd) to write the test data to the global data line YIO through the data path. As shown in Figure 3 , the write instruction will pull the potential at WrEn high, while pulling the potential at EQ low. At this time, the write data path is opened. After the detection device issues the write instruction (Write cmd), the test data can be written through the data path.

[0111] In step S340, the detection device switches to the read mode, and keeps the write drive circuit of the global data line, so that the global data line is always on. As shown in Figure 10 , tmReadYio<1> is high, and the output of the logic circuit Figure 10 keeps the enable end YIOWrEn of the write drive circuit always high, thereby realizing that after switching to the read mode, the write drive circuit of the global data line YIO is enabled, so that the data on the global data line YIO is kept.

[0112] In step S350, after waiting for a preset time length, the detection device reads the target data on the global data line, records and tests the timing of the data path. The preset time length is not limited in this embodiment, and can be adjusted according to the detection needs. During the waiting process, YioWrEn is always valid, maintaining the data on the global data line YIO. Then, the detection device issues a Read cmd instruction to read the target data on the global data line YIO, records and tests the timing of the data path, in preparation for subsequent analysis of the detection results.

[0113] Figure 11 A block diagram of a data path detection device according to an example embodiment is shown. As shown, the device includes a control module 301, a write module 302, a read module 303, and a judgment module 304. The control module 301 is configured to disconnect the global data line from the local data line in the data path. The write module 302 is configured to write test data to the global data line YIO in the data path through the write port of the data path. The read module 303 is configured to read the target data on the global data line YIO under a preset condition. The judgment module 304 is configured to detect defects in the data path according to the test data and the target data. Figure 10

[0114] In one example embodiment, the control module 301 is configured to send a first instruction to the local read-write conversion module to disconnect the global data line YIO from the local data line. The control module 301 is configured to switch to a read mode, and turn off the write drive circuit of the global data line YIO, so that the global data line YIO is floating. The read module 303 is configured to wait for a preset time length, and then read the target data on the global data line, record and test the timing of the data path.

[0115] In another embodiment, the control module 301 is configured to send a second instruction to the local read-write conversion module to disconnect the global data line YIO from the local data line, and keep the write drive circuit of the global data line YIO enabled, so that the data on the global data line YIO is maintained. The control module 301 is configured to switch to a read mode. The read module 303 is configured to read the target data on the global data line, record and test the timing of the data path. The control module 301 can switch the read mode through the read-write conversion module, and achieve the storage of the target data. The read module 303 is configured to wait for a preset time length, and then read the target data on the global data line YIO, record and test the timing of the data path. The judgment module 304 is configured to determine that there is a defect in the data path if the test data and the target data are inconsistent.

[0116] Figure 12 ​is a block diagram of an apparatus for data path detection, i.e., a computer device 400, according to an exemplary embodiment. For example, the computer device 400 can be provided as a terminal device. Referring to Figure 12 The computer device 400 includes a processor 401, the number of which can be set to one or more as needed. The computer device 400 also includes a memory 402 for storing instructions, such as an application program, executable by the processor 401. The number of memories can be set to one or more as needed. The stored application program can be one or more. The processor 401 is configured to execute the instructions to perform the above method.

[0117] Those skilled in the art will appreciate that embodiments of the present disclosure can be provided as methods, apparatus (devices), or computer program products. Accordingly, the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure can take the form of a computer program product on one or more computer-usable storage media having computer-usable program code embodied in the medium. The computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, including but not limited to RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer, and the like. In addition, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and can include any information delivery media.

[0118] In exemplary embodiments, a non-transitory computer readable storage medium is provided, such as the memory 402 including instructions, which can be executed by the processor 401 of the apparatus 400 to complete the above method. For example, the non-transitory computer readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk and an optical data storage device, etc. When the instructions in the storage medium are executed by the processor of the terminal, the detection apparatus is enabled to perform the method shown in the data path detection method disclosed in the above embodiments.

[0119] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0120] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart block or blocks. Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0121] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0122] In this disclosure, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0123] While the preferred embodiments of the disclosure have been described, additional variations and modifications can be made to these embodiments by those skilled in the art once they have the benefit of the foregoing description. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit and scope of the disclosure. It is further understood that the disclosure can be used in various applications and that the disclosure is not limited to the applications specifically described herein. Accordingly, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the disclosure. Therefore, it is to be understood that the disclosure is intended to cover all such modifications and variations as fall within the scope of the claims and their equivalents.

Claims

1. A data path detection method, applied to the data path detection process of a semiconductor integrated circuit, characterized in that: The data path detection method comprises: The detection device disconnects the global data line and the local data line in the data path; the global data line and the local data line are connected to the local read-write conversion module; The detection device writes the test data to the global data line in the data path via the data path through the write port and the write drive circuit of the data path; Under preset conditions, the detection device reads the target data of the global data line through a read circuit, wherein the read circuit is connected to the write drive circuit; The detection device detects defects in the data path according to the test data and the target data.

2. The detection method according to claim 1, wherein The detecting device disconnects the global data line and the local data line in the data path, comprising: The detection device sends a first instruction to the local read-write conversion module; The local read-write conversion module disconnects the global data line from the local data line based on the received first instruction.

3. The detection method according to claim 2, characterized in that The detecting device reads the target data of the global data line through the reading circuit under the preset condition, including: The detection device switches to a read mode, turns off the write drive circuit of the global data line, and makes the global data line float; After waiting for a preset time period, the detection device reads the target data of the global data line, and records and tests the timing of the data path.

4. The detection method according to claim 1, wherein The detecting device disconnects the global data line and the local data line in the data path, comprising: The detection device sends a second instruction to the local read-write conversion module; The local read-write conversion module disconnects the global data line from the local data line based on the received second instruction, and keeps the write driving circuit of the global data line enabled, so that the data on the global data line is maintained.

5. The detection method according to claim 4, characterized in that The detecting device reads the target data of the global data line through the reading circuit under the preset condition, including: The detection device switches to a reading mode; The detection device reads the target data of the global data line, and records and tests the timing of the data path.

6. The detection method according to claim 1, characterized in that: The detection device detects defects in the data path according to the test data and the target data, including: If the test data is inconsistent with the target data, the detection device determines that there is a defect in the data path.

7. The detection method according to claim 1, characterized in that: The defect includes a short circuit defect or an open circuit defect.

8. A data path detection device for detecting a data path of a semiconductor integrated circuit, characterized in that: The data path detection device comprises: A control module, configured to disconnect the global data line and the local data line in the data path; wherein the global data line and the local data line are connected to a local read-write conversion module; a write module, configured to write test data to the global data line in the data path via the data path through a write port and a write driver circuit of the data path; a reading module, configured to read target data of the global data line through a reading circuit under a preset condition, wherein the reading circuit is connected to the write driving circuit; A judgment module is used to detect defects in the data path according to the test data and the target data.

9. The data path detection device according to claim 8, characterized in that: The control module is used for: A first instruction is sent to the local read-write conversion module to disconnect the global data line from the local data line.

10. The data path detection device according to claim 9, characterized in that: The control module is used for: Switching to a read mode, turning off the write drive circuit of the global data line, so that the global data line is floating; The reading module is used for: After waiting for a preset time, the target data of the global data line is read, and the timing of the data path is recorded and tested.

11. The data path detection device according to claim 8, wherein: The control module is used for: A second instruction is sent to the local read-write conversion module to disconnect the global data line from the local data line and keep the write drive circuit of the global data line enabled so that the data on the global data line is maintained.

12. The data path detection device according to claim 11, wherein: The control module is used for: Switch to read mode; The reading module is used for: The target data of the global data line is read, and the timing of the data path is recorded and tested.

13. The data path detection device according to claim 8, wherein: The judgment module is used for: If the test data is inconsistent with the target data, it is determined that there is a defect in the data path.

14. A data path detection device, comprising: processor; a memory for storing processor-executable instructions; The processor is configured to execute the method according to any one of claims 1 to 7.

15. A non-transitory computer-readable storage medium, characterized in that When the instructions in the storage medium are executed by a processor of the terminal, the detection device is enabled to perform the method according to any one of claims 1 to 7.

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