DC-DC converters

Abstract

An embodiment of the present disclosure provides a DC-DC converter, comprising: an inductor, first and second power transistors, a switch control circuit, a current detection circuit, an output capacitor, a feedback circuit, an error amplifier, and a first comparator. The switch control circuit generates first and second control signals based on a comparison signal output by the first comparator, a clock signal, a bias voltage, and input and output voltages. When the input voltage is greater than or equal to the output voltage, the voltage of the first control signal is equal to the bias voltage. When the input voltage is less than the output voltage, the first and second control signals are used to alternately turn on the first and second power transistors. The current detection circuit samples a first current flowing through the first power transistor, generates a detection voltage signal based on the sampled current, and provides it to the first comparator. The feedback circuit generates a feedback voltage signal based on the output voltage signal. The error amplifier amplifies the voltage difference between the reference voltage and the feedback voltage signal and provides the amplified voltage difference to the first comparator.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, to a DC-DC converter. Background Art

[0002] DC-DC converters are commonly used to convert DC voltages in various electronic devices. These converters include step-down (buck) and step-up (boost) converters. A step-down converter converts a higher DC voltage to a lower DC voltage. A step-up converter converts a lower DC voltage to a higher DC voltage. With the rapid development of semiconductor technology and the continuous expansion of its application areas, boost circuits are widely used in everyday life. Boost converters can be used in power amplifiers, adaptive control, and other applications. In some applications, it is desirable for a DC-DC boost converter to function properly even in scenarios where a step-down voltage is required. Summary of the Invention

[0003] The embodiments described herein provide a DC-DC converter.

[0004] According to a first aspect of the present disclosure, a DC-DC converter is provided. The DC-DC converter includes an inductor, a first power transistor, a second power transistor, a switch control circuit, a current detection circuit, an output capacitor, a feedback circuit, an error amplifier, and a first comparator. The first terminal of the inductor is coupled to an input voltage terminal. The second terminal of the inductor is coupled to the second electrode of the first power transistor and the second electrode of the second power transistor. The control electrode of the first power transistor is coupled to the first output terminal of the switch control circuit. The first electrode of the first power transistor is coupled to the output voltage terminal. The control electrode of the second power transistor is coupled to the second output terminal of the switch control circuit. The first electrode of the second power transistor is coupled to the second voltage terminal. The switch control circuit is configured to generate a first control signal and a second control signal based on a comparison signal output by the first comparator, a clock signal from a clock signal terminal, a bias voltage from a bias voltage terminal, an input voltage from an input voltage terminal, and an output voltage output from an output voltage terminal, and output the first control signal from the first output terminal and the second control signal from the second output terminal. When the input voltage is greater than or equal to the output voltage, the voltage of the first control signal is equal to the bias voltage. When the input voltage is less than the output voltage, the first control signal and the second control signal are used to alternately turn on the first power tube and the second power tube. The current detection circuit is configured to sample the first current flowing through the first power tube, generate a detection voltage signal based on the sampled current, and provide the detection voltage signal to the first input terminal of the first comparator. The first end of the output capacitor is coupled to the output voltage terminal. The second end of the output capacitor is coupled to the second voltage terminal. The feedback circuit is configured to generate a feedback voltage signal based on the output voltage signal output from the output voltage terminal, and provide the feedback voltage signal to the second input terminal of the error amplifier. The first input terminal of the error amplifier is coupled to the reference voltage terminal. The output terminal of the error amplifier is coupled to the second input terminal of the first comparator.

[0005] In some embodiments of the present disclosure, a switch control circuit includes: a logic control circuit, a voltage selection circuit, a second comparator, and a first inverter. The logic control circuit is configured to generate a first indication signal and a second indication signal based on a comparison signal and a clock signal, provide the first indication signal from a first output terminal of the logic control circuit to an input terminal of the first inverter, and provide the second indication signal from a second output terminal of the logic control circuit to a control terminal of a second power transistor. The first indication signal and the second indication signal are inverted signals of each other. The output terminal of the first inverter is coupled to a first candidate voltage terminal of the voltage selection circuit. The first input terminal of the second comparator is coupled to an output voltage terminal. The second input terminal of the second comparator is coupled to an input voltage terminal. The second comparator is configured to output a first level signal when the input voltage is less than the output voltage, and to output a second level signal when the input voltage is greater than or equal to the output voltage. The second candidate voltage terminal of the voltage selection circuit is coupled to a bias voltage terminal. The selection terminal of the voltage selection circuit is coupled to the output terminal of the second comparator. The output terminal of the voltage selection circuit is coupled to the control terminal of the first power transistor. The voltage selection circuit is configured to output a voltage from a first candidate voltage terminal as a first control signal when a first level signal is provided to the selection terminal, and to output a bias voltage as the first control signal when a second level signal is provided to the selection terminal.

[0006] In some embodiments of the present disclosure, a switch control circuit includes: a logic control circuit, a voltage selection circuit, a second comparator, a first inverter, a second inverter, and a third inverter. The logic control circuit is configured to generate a first indication signal and a second indication signal based on a comparison signal and a clock signal, and to provide the first indication signal from a first output terminal of the logic control circuit to an input terminal of the first inverter, and to provide the second indication signal from a second output terminal of the logic control circuit to an input terminal of the second inverter. The first indication signal and the second indication signal are inverted signals of each other. The output terminal of the first inverter is coupled to a first candidate voltage terminal of the voltage selection circuit. The first input terminal of the second comparator is coupled to an output voltage terminal. The second input terminal of the second comparator is coupled to an input voltage terminal. The second comparator is configured to output a first level signal when the input voltage is less than the output voltage, and to output a second level signal when the input voltage is greater than or equal to the output voltage. The second candidate voltage terminal of the voltage selection circuit is coupled to a bias voltage terminal. The selection terminal of the voltage selection circuit is coupled to the output terminal of the second comparator. The output terminal of the voltage selection circuit is coupled to the control electrode of the first power transistor. The voltage selection circuit is configured to output a voltage from a first candidate voltage terminal as a first control signal when a first level signal is provided to the selection terminal, and to output a bias voltage as the first control signal when a second level signal is provided to the selection terminal. The output of the second inverter is coupled to the input of the third inverter. The output of the third inverter is coupled to the control electrode of the second power transistor.

[0007] In some embodiments of the present disclosure, a logic control circuit includes: a first NOT gate, a second NOT gate, a third NOT gate, a first NAND gate, and a second NAND gate. The input of the first NOT gate is coupled to the output of the first comparator. The output of the first NOT gate is coupled to the first input of the first NAND gate. The input of the second NOT gate is coupled to the clock signal terminal. The output of the second NOT gate is coupled to the second input of the second NAND gate. The second input of the first NAND gate is coupled to the output of the second NAND gate. The output of the first NAND gate is coupled to the first input of the second NAND gate. The output of the second NAND gate is coupled to the first output of the logic control circuit. The input of the third NOT gate is coupled to the output of the second NAND gate. The output of the third NOT gate is coupled to the second output of the logic control circuit.

[0008] In some embodiments of the present disclosure, the current detection circuit includes: a third transistor, a fourth transistor, and a fifth transistor. The control electrode of the third transistor is coupled to the control electrode of the first power transistor. The first electrode of the third transistor is coupled to the first input terminal of the first comparator. The second electrode of the third transistor is coupled to the second electrode of the first power transistor. The control electrode of the fourth transistor is coupled to the second voltage terminal. The first electrode of the fourth transistor is coupled to the output voltage terminal. The second electrode of the fourth transistor is coupled to the first input terminal of the first comparator. The control electrode of the fifth transistor is coupled to the output terminal of the second comparator. The first electrode of the fifth transistor is coupled to the output voltage terminal. The second electrode of the fifth transistor is coupled to the second electrode of the fourth transistor.

[0009] In some embodiments of the present disclosure, a feedback circuit includes: a first resistor and a second resistor. A first end of the first resistor is coupled to an output voltage terminal. A second end of the first resistor is coupled to a second input terminal of an error amplifier. A first end of the second resistor is coupled to the second input terminal of the error amplifier. A second end of the second resistor is coupled to a second voltage terminal.

[0010] In some embodiments of the present disclosure, the DC-DC converter further includes a clock generation circuit configured to generate a clock signal and output the clock signal from a clock signal terminal.

[0011] In some embodiments of the present disclosure, the first power tube is a P-type transistor, and the second power tube is an N-type transistor.

[0012] In some embodiments of the present disclosure, the first input terminal of the error amplifier is a non-inverting input terminal, the second input terminal of the error amplifier is an inverting input terminal, the first input terminal of the first comparator is a non-inverting input terminal, and the second input terminal of the first comparator is an inverting input terminal.

[0013] According to a second aspect of the present disclosure, a DC-DC converter is provided. The DC-DC converter includes: an inductor, a first power transistor, a second power transistor, third to fifth transistors, first to third NOT gates, a first NAND gate, a second NAND gate, a voltage selection circuit, a second comparator, first to third inverters, an output capacitor, a first resistor, a second resistor, an error amplifier, and a first comparator. A first terminal of the inductor is coupled to an input voltage terminal. A second terminal of the inductor is coupled to the second electrode of the first power transistor and the second electrode of the second power transistor. A control electrode of the first power transistor is coupled to the output terminal of the voltage selection circuit. A first electrode of the first power transistor is coupled to the output voltage terminal. A control electrode of the second power transistor is coupled to the output terminal of the third inverter. A first electrode of the second power transistor is coupled to the second voltage terminal. An input terminal of the first NOT gate is coupled to the output terminal of the first comparator. An output terminal of the first NOT gate is coupled to the first input terminal of the first NAND gate. An input terminal of the second NOT gate is coupled to a clock signal terminal. An output terminal of the second NOT gate is coupled to the second input terminal of the second NAND gate. A second input terminal of the first NAND gate is coupled to the output terminal of the second NAND gate. The output of the first NAND gate is coupled to the first input of the second NAND gate. The output of the second NAND gate is coupled to the input of the first inverter. The input of the third NOT gate is coupled to the output of the second NAND gate. The output of the third NOT gate is coupled to the input of the second inverter. The output of the first inverter is coupled to the first candidate voltage terminal of the voltage selection circuit. The first input of the second comparator is coupled to the output voltage terminal. The second input of the second comparator is coupled to the input voltage terminal. The second input of the voltage selection circuit is coupled to the bias voltage terminal. The select terminal of the voltage selection circuit is coupled to the output of the second comparator. The output of the voltage selection circuit is coupled to the control electrode of the first power transistor. The voltage selection circuit is configured to output the voltage from the first candidate voltage terminal when a first level signal is provided to the select terminal, and to output the bias voltage when a second level signal is provided to the select terminal. The output of the second inverter is coupled to the input of the third inverter. The output of the third inverter is coupled to the control electrode of the second power transistor. The control electrode of the third transistor is coupled to the control electrode of the first power transistor. The first electrode of the third transistor is coupled to the first input of the first comparator. The second electrode of the third transistor is coupled to the second electrode of the first power transistor. The control electrode of the fourth transistor is coupled to the second voltage terminal. The first electrode of the fourth transistor is coupled to the output voltage terminal. The second electrode of the fourth transistor is coupled to the first input terminal of the first comparator. The control electrode of the fifth transistor is coupled to the output terminal of the second comparator. The first electrode of the fifth transistor is coupled to the output voltage terminal. The second electrode of the fifth transistor is coupled to the second electrode of the fourth transistor. The first end of the first resistor is coupled to the output voltage terminal. The second end of the first resistor is coupled to the second input terminal of the error amplifier. The first end of the second resistor is coupled to the second input terminal of the error amplifier. The second end of the second resistor is coupled to the second voltage terminal. The first end of the output capacitor is coupled to the output voltage terminal. The second end of the output capacitor is coupled to the second voltage terminal. The first input terminal of the error amplifier is coupled to the reference voltage terminal.The output terminal of the error amplifier is coupled to the second input terminal of the first comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0015] Figure 1 is an exemplary circuit diagram of a DC-DC converter;

[0016] Figure 2 is a schematic block diagram of a DC-DC converter according to an embodiment of the present disclosure;

[0017] Figure 3 is an exemplary circuit diagram of a DC-DC converter according to an embodiment of the present disclosure;

[0018] Figure 4 yes Figure 3 An exemplary circuit diagram of the logic control circuit in the illustrated embodiment;

[0019] Figure 5 is used for Figure 3 The timing diagram of some signals of the DC-DC converter; and

[0020] Figure 6 is another exemplary circuit diagram of a DC-DC converter according to an embodiment of the present disclosure.

[0021] In the drawings, reference numerals having the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0024] In all embodiments of the present disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the directions of the conduction current between the source and drain (emitter and collector) of the N-type transistor and the P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle end of the transistor is referred to as the control electrode, and the remaining two ends of the transistor are referred to as the first electrode and the second electrode, respectively. The transistors used in the embodiments of the present disclosure are mainly metal oxide semiconductor (MOS) transistors. In addition, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0025] Figure 1 FIG. 1 shows an exemplary circuit diagram of a DC-DC converter 100. Figure 1 As shown, the DC-DC converter 100 may include: an inductor L, a first power transistor Mp0, a second power transistor Mn0, a first transistor Mp1, a second transistor Mp2, a clock generation circuit 110, a logic control circuit 121, a first inverter O1, a second inverter O2, a third inverter O3, an output capacitor Cout, a first resistor R1, a second resistor R2, an error amplifier EA, and a first comparator COMP1. The first power transistor Mp0, the first transistor Mp1, and the second transistor Mp2 are PMOS transistors. The second power transistor Mn0 is an NMOS transistor.

[0026] The first power tube Mp0 and the second power tube Mn0 can be used as power tubes to control the external load (in Figure 1(shown in FIG. 1 ) as a power supply for a load current source Iload. In some examples, the DC-DC converter 100 can be coupled to a clock signal terminal of the clock generation circuit 110 to obtain a clock signal CLK. The logic control circuit 121 can generate a first indication signal and a second indication signal based on the comparison signal OUT1 output by the first comparator COMP1 and the clock signal CLK from the clock signal terminal, outputting the first indication signal from the first output terminal PON and the second indication signal from the second output terminal NON. The first indication signal is provided to the gate of the first power transistor Mp0 via the first inverter O1, and the second indication signal is provided to the gate of the second power transistor Mn0 via the second inverter O2 and the third inverter O3. The second inverter O2 and the third inverter O3 can be used to increase the driving capability of the second indication signal. The non-inverting input terminal of the first comparator COMP1 is coupled to the source of the first transistor Mp1 and the drain of the second transistor Mp2. The first power transistor Mp0 and the first transistor Mp1 can form a current mirror circuit. The first transistor Mp1 and the second transistor Mp2 can form a current detection circuit, which can sample the current flowing through the first power transistor Mp0 and generate a detection voltage signal VS1 based on the sampled current. The detection voltage signal VS1 is provided to the non-inverting input of the first comparator. The first resistor R1 and the second resistor R2 can form a feedback circuit, which can divide the output voltage signal output from the output voltage terminal Vout to generate a feedback voltage signal FB. The feedback voltage signal FB is provided to the inverting input of the error amplifier EA. The non-inverting input of the error amplifier EA can be coupled to the reference voltage terminal Vref. The output terminal ea of ​​the error amplifier EA can be coupled to the inverting input of the first comparator COMP1.

[0027] When the sampled voltage VS1 is greater than or equal to the voltage at the output terminal ea, the comparison signal OUT1 is at a high level, the second indication signal outputted by the second output terminal NON of the logic control circuit 121 is at a high level, the second power transistor Mn0 is turned on, the inductor L enters an energy storage state, and the inductor current IL begins to rise (this phase is referred to as the positive half-cycle of the inductor current IL). At this time, the slope of the inductor current IL is k1 = Vin / L. When the clock signal CLK is at a high level, the first indication signal outputted by the first output terminal PON of the logic control circuit 121 is at a high level, the first power transistor Mp0 is turned on, the second power transistor Mn0 is turned off, the inductor L enters a discharge state, and the inductor current IL begins to decrease (this phase is referred to as the negative half-cycle of the inductor current IL). At this time, the slope of the inductor current IL is k2 = (Vin - Vout) / L.

[0028] When Vin < Vout, that is, when the DC-DC converter operates in the boost mode, k2 < 0. Since k1 > 0 and k2 < 0, the inductor current IL can be balanced. When Vin > VoutT, that is, when the DC-DC converter operates in the buck mode, k2 > 0. Since k1 > 0 and k2 > 0, the inductor current IL rises in both the positive and negative half-cycles, and the inductor current IL cannot be balanced, and the DC-DC converter cannot regulate the voltage.

[0029] Embodiments of the present disclosure propose a DC-DC converter. Figure 2 A schematic block diagram of a DC-DC converter 200 according to an embodiment of the present disclosure is shown. As Figure 2 shown, the DC-DC converter 200 may include: an inductor L, a first power transistor M1, a second power transistor M2, a switch control circuit 220, a current detection circuit 230, an output capacitor Cout, a feedback circuit 240, an error amplifier EA, and a first comparator COMP1. Although in Figure 2 the example it is shown that the DC-DC converter 200 further includes a clock generation circuit 210, those skilled in the art should understand that the clock signal terminal of the DC-DC converter 200 may be coupled to an external clock generation circuit, and thus the DC-DC converter 200 itself may not include the clock generation circuit 210.

[0030] In Figure 2 the example, the first power transistor M1 is a PMOS transistor. The second power transistor M2 is an NMOS transistor.

[0031] In the DC-DC converter 200, the first end of the inductor L is coupled to the input voltage terminal Vin. The second end of the inductor L is coupled to the second pole of the first power transistor M1 and the second pole of the second power transistor M2. The control pole of the first power transistor M1 is coupled to the first output terminal PGATE of the switch control circuit 220. The first pole of the first power transistor M1 is coupled to the output voltage terminal Vout. The control pole of the second power transistor M2 is coupled to the second output terminal NGATE of the switch control circuit 220. The first pole of the second power transistor M2 is coupled to the second voltage terminal V2.

[0032] The switch control circuit 220 may be coupled to the output terminal of the first comparator COMP1, the clock signal terminal of the clock generation circuit 210, the first power transistor M1, the second power transistor M2, the bias voltage terminal Vb, the input voltage terminal Vin, and the output voltage terminal Vout. The switch control circuit 220 may be configured to generate a first control signal and a second control signal based on the comparison signal OUT1 output by the first comparator COMP1, the clock signal CLK from the clock signal terminal, the bias voltage from the bias voltage terminal Vb, the input voltage from the input voltage terminal Vin, and the output voltage from the output voltage terminal Vout, and to output the first control signal from the first output terminal PGATE and the second control signal from the second output terminal NGATE. When the input voltage Vin is greater than or equal to the output voltage Vout, the voltage of the first control signal is equal to the bias voltage Vb. When the input voltage Vin is less than the output voltage Vout, the first control signal and the second control signal are used to alternately turn on the first power transistor M1 and the second power transistor M2. For example, when the first control signal and the second control signal are at a low level, the first power transistor M1 is turned on and the second power transistor M2 is turned off. When the first control signal and the second control signal are at a high level, the first power tube M1 is turned off, and the second power tube M2 is turned on.

[0033] The current detection circuit 230 can be coupled to the non-inverting input terminal of the first comparator COMP1, the second electrode of the first power transistor M1, and the second electrode of the second power transistor M2. The current detection circuit 230 is configured to sample the first current flowing through the first power transistor M1, generate a detection voltage signal VS1 based on the sampled current, and provide the detection voltage signal VS1 to the non-inverting input terminal of the first comparator COMP1.

[0034] A first terminal of the output capacitor Cout is coupled to the output voltage terminal Vout. A second terminal of the output capacitor Cout is coupled to the second voltage terminal V2.

[0035] Feedback circuit 240 can be coupled to the output voltage terminal Vout, the second voltage terminal V2, and the inverting input terminal of the error amplifier EA. Feedback circuit 240 is configured to generate a feedback voltage signal FB based on the output voltage signal output from the output voltage terminal Vout, and provide the feedback voltage signal FB to the inverting input terminal of the error amplifier EA. The non-inverting input terminal of the error amplifier EA is coupled to the reference voltage terminal Vref. The output terminal ea of ​​the error amplifier EA is coupled to the inverting input terminal of the first comparator COMP1.

[0036] exist Figure 2In the example, the second voltage terminal V2 is grounded. When Vin < Vout, when the first control signal and the second control signal are at a high level, the first power transistor M1 is turned off and the second power transistor M2 is turned on. At this time, the inductor current IL is in the positive half cycle. The slope k1 of the inductor current IL > 0. When the first control signal and the second control signal are at a low level, the first power transistor M1 is turned on and the second power transistor M2 is turned off. At this time, the inductor current IL is in the negative half cycle. The slope k2 of the inductor current IL < 0. In this case, k1 > 0 and k2 < 0, so the inductor current IL can be balanced.

[0037] When Vin ≥ Vout, the voltage V of the first control signal ,

[0039] , Figure 3 = Vb. Vb represents the voltage output by the bias voltage terminal Vb. In some examples, Vb can be equal to Vin or slightly less than Vin. When the second control signal is at a high level, the second power transistor M2 is turned on. The voltage Vsw of the node sw is pulled to zero potential by the second power transistor M2, and the first power transistor M1 is turned off. At this time, the inductor current IL is in the positive half cycle. The slope k1 of the inductor current IL > 0. When the second control signal is at a low level, the second power transistor M2 is turned off, and the inductor current IL can only flow through the first power transistor M1 to the output voltage terminal Vout, so the voltage Vsw of the node sw will be raised to Vb + Vgs_M1 (Vgs_M1 represents the gate-source voltage of the first power transistor M1), making the first power transistor M1 in a high-impedance conduction state. At this time, the slope of the inductor current IL is k2 = (Vin - Vsw) / L = (Vin - Vin - Vgs_M1) / L = -Vgs_M1 / L < 0. In this case, k​​​​​​​​The logic control circuit 221 may be coupled to the first comparator COMP1, the clock generation circuit 210, the first inverter O1, and the second inverter O2. The logic control circuit 221 is configured to generate a first indication signal and a second indication signal based on the comparison signal OUT1 and the clock signal CLK. The first indication signal is provided from the first output terminal PON of the logic control circuit 221 to the input terminal of the first inverter O1, and the second indication signal is provided from the second output terminal NON of the logic control circuit 221 to the input terminal of the second inverter O2. The output terminal of the second inverter O2 is coupled to the input terminal of the third inverter O3, and the output terminal of the third inverter O3 is coupled to the gate electrode of the second power transistor M2. The first indication signal and the second indication signal are inverted signals of each other. The output terminal of the first inverter O1 is coupled to the first candidate voltage terminal PONB of the voltage selection circuit 222. The first input terminal (e.g., the non-inverting input terminal) of the second comparator COMP2 is coupled to the output voltage terminal Vout. The second input terminal (e.g., inverting input terminal) of the second comparator COMP2 is coupled to the input voltage terminal Vin. The second comparator COMP2 is configured to output a first level signal when the input voltage Vin is less than the output voltage Vout, and output a second level signal when the input voltage Vin is greater than or equal to the output voltage Vout. Figure 3 In the example, the first level signal is a high level signal, and the second level signal is a low level signal.

[0040] The second candidate voltage terminal Q1 of the voltage selection circuit 222 is coupled to the bias voltage terminal Vb. The selection terminal SL of the voltage selection circuit 222 is coupled to the output terminal of the second comparator COMP2. The output terminal PGATE of the voltage selection circuit 222 is coupled to the control electrode of the first power transistor M1. The voltage selection circuit 222 is configured to output the voltage from the first candidate voltage terminal PONB as the first control signal when the selection terminal SL is provided with a first level signal, and to output the bias voltage Vb as the first control signal when the selection terminal SL is provided with a second level signal.

[0041] exist Figure 3 In the example, the second inverter O2 and the third inverter O3 are used to increase the driving capability of the second indication signal. In some alternative embodiments of the present disclosure, the switch control circuit 220 may not include the second inverter O2 and the third inverter O3. The second output terminal NON of the logic control circuit 221 can be directly coupled to the gate electrode of the second power transistor M2.

[0042] Figure 4 Shown Figure 3 FIG. 2 is an exemplary circuit diagram of the logic control circuit 221 in the embodiment shown. Figure 4As shown, the logic control circuit 221 may include: a first NOT gate N1, a second NOT gate N2, a third NOT gate N3, a first NAND gate A1, and a second NAND gate A2. The input of the first NOT gate N1 is coupled to the output of the first comparator COMP1. The output of the first NOT gate N1 is coupled to the first input of the first NAND gate A1. The input of the second NOT gate N2 is coupled to the clock signal terminal CLK. The output of the second NOT gate N2 is coupled to the second input of the second NAND gate A2. The second input of the first NAND gate A1 is coupled to the output of the second NAND gate A2. The output of the first NAND gate A1 is coupled to the first input of the second NAND gate A2. The output of the second NAND gate A2 is coupled to the first output PON of the logic control circuit 221. The input of the third NOT gate N3 is coupled to the output of the second NAND gate A2. The output of the third NOT gate N3 is coupled to the second output NON of the logic control circuit 221.

[0043] Figure 5 Shown for Figure 3 The timing diagram of some signals of the DC-DC converter 300 is shown below. Figure 3 and Figure 4 Examples and Figure 5 The timing diagram is used to illustrate the working process of the DC-DC converter 300 according to the embodiment of the present disclosure.

[0044] like Figure 5 As shown in the figure, at time t1, the comparison signal OUT1 is at a high level and the clock signal CLK is at a low level. The first indication signal PON output by the first output terminal PON is at a low level, and the second indication signal NON output by the second output terminal NON is at a high level. As a result, the first power transistor M1 is turned off and the second power transistor M2 is turned on. The inductor L begins to store energy. The inductor current IL begins to enter the positive half-cycle. At time t2, the comparison signal OUT1 is at a low level and the clock signal CLK is at a high level. The first indication signal PON output by the first output terminal PON is at a high level, and the second indication signal NON output by the second output terminal NON is at a low level. This turns on the first power transistor M1 and turns off the second power transistor M2. The inductor L begins to discharge. The inductor current IL begins to enter the negative half-cycle.

[0045] Back to Figure 3 The current detection circuit 230 may include: a third transistor M3 and a fourth transistor M4. The control electrode of the third transistor M3 is coupled to the control electrode of the first power transistor M1. A first electrode of the third transistor M3 is coupled to the first input terminal of the first comparator. A second electrode of the third transistor M3 is coupled to the second electrode of the first power transistor M1. A control electrode of the fourth transistor M4 is coupled to the second voltage terminal V2. A first electrode of the fourth transistor M4 is coupled to the output voltage terminal Vout. A second electrode of the fourth transistor M4 is coupled to the first input terminal of the first comparator COMP1.

[0046] The feedback circuit 240 may include: a first resistor R1 and a second resistor R2. Among them, the first end of the first resistor R1 is coupled to the output voltage terminal Vout. The second end of the first resistor R1 is coupled to the second input terminal of the error amplifier EA. The first end of the second resistor R2 is coupled to the second input terminal of the error amplifier EA. The second end of the second resistor R2 is coupled to the second voltage terminal V2.

[0047] In Figure 3 the example of, the third transistor M3 and the fourth transistor M4 are PMOS transistors. The first input terminal of the error amplifier EA is the non-inverting input terminal. The second input terminal of the error amplifier EA is the inverting input terminal. The first input terminal of the first comparator COMP1 is the non-inverting input terminal. The second input terminal of the first comparator COMP1 is the inverting input terminal. Those skilled in the art should understand that modifications made to the Figure 3 circuit shown should also fall within the protection scope of the present disclosure. In this modification, the above-mentioned transistors and ports may also have settings different from those in the Figure 3 example shown.

[0048] In Figure 3 the example of, when Vout > Vin, the voltage signal OUT2 output by the second comparator COMP₂ is at a high level. The voltage signal OUT2 at a high level is provided to the selection terminal SL of the voltage selection circuit 222, and the voltage selection circuit 222 outputs the voltage from the first candidate voltage terminal PONB as the first control signal. At this time, V PGATE = V PONB , V PONB represents the voltage of the first candidate voltage terminal. When Vout < Vin, the voltage signal OUT2 output by the second comparator COMP₂ is at a low level. The voltage signal OUT2 at a low level is provided to the selection terminal SL of the voltage selection circuit 222, and the voltage selection circuit 222 outputs the bias voltage Vb as the first control signal. At this time, V PGATE = Vb.

[0049] In both cases of Vin > Vout and Vin < Vout, in the negative half cycle of the inductor current IL, the voltage at the control pole of the first power transistor M1 is different, so the current sampling ratio performed by the current sampling circuit 230 is different, resulting in inaccurate detection voltage signal VS1.

[0050] Regarding the problem of different current sampling ratios in the two cases of Vin > Vout and Vin < Vout, the embodiments of the present disclosure propose Figure 6 the DC-DC converter 600 shown in. As Figure 6As shown, the DC-DC converter 600 may include: an inductor L, a first power transistor M1, a second power transistor M2, a current detection circuit 630, an output capacitor Cout, a feedback circuit 240, an error amplifier EA, a first comparator COMP1, a logic control circuit 221, a voltage selection circuit 222, a second comparator COMP2, a first inverter O1, a second inverter O2, and a third inverter O3.

[0051] The current detection circuit 630 may include: a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The control electrode of the fifth transistor M5 is coupled to the output terminal of the second comparator COMP2. The first electrode of the fifth transistor M5 is coupled to the output voltage terminal Vout. The second electrode of the fifth transistor M5 is coupled to the second electrode of the fourth transistor M4. In Figure 6 the example, the fifth transistor M5 is a PMOS transistor.

[0052] When Vout>Vin, OUT2 is at a high level and the fifth transistor M5 is in an off state. At this time, the first power transistor M1, the third transistor M3, and the fourth transistor M4 all operate in the linear region. In this embodiment, the aspect ratio W / L_M1 of the first power transistor M1 = a, the aspect ratio W / L_M3 of the third transistor M3 = b, and the aspect ratio W / L_M4 of the fourth transistor M4 = c, where a is much larger than b and c. The third transistor M3 and the fourth transistor M4 are in a series relationship, and the equivalent aspect ratio W / L after series connection = b / / c = bc / (b + c). The inductor current is IL, and because a is much larger than b and c, the currents sampled by the third transistor M3 and the fourth transistor M4 can be considered Because the on-resistance ron_M4 of the fourth transistor M4 is inversely proportional to the aspect ratio W / L_M4, so ron_M4 = 1 / ck. k represents a coefficient for converting the on-resistance and the aspect ratio. Therefore, the voltage drop between the first and second electrodes of the fourth transistor M4 is That is

[0053] When Vout<Vin, OUT2 is at a low level and the fifth transistor M5 is in a conducting state. At this time, the first power transistor M1 and the third transistor M3 operate in the saturation region. The fourth transistor M4 operates in the linear region. Therefore, only the first power transistor M1 and the third transistor M3 have a current mirror image relationship. The currents sampled by the third transistor M3 and the fourth transistor M4 are approximately Select the aspect ratio W / L_M5 of the fifth transistor M5 to be equal to the aspect ratio W / L_M3 of the third transistor M3, i.e., W / L_M5 = W / L_M3 = b. The on-resistance ron_M5 of the fifth transistor M5 = 1 / bk. Also, since the on-resistance ron_M4 of the fourth transistor M4 = 1 / ck. Then the on-resistance ron after the fourth transistor M4 and the fifth transistor M5 are connected in parallel is 1 / (b + c)k. The voltage drop between the first and second poles of the fourth transistor M4 is

[0054] It can be seen that the voltage drop between the first and second poles of the fourth transistor M4 obtained from Equation (1) and Equation (2) is the same. Therefore, the DC-DC converter 600 of the embodiments of the present disclosure can make the current sampling ratios the same in both cases of Vin > Vout and Vin < Vout. In this way, the DC-DC converter 600 of the embodiments of the present disclosure can operate normally in both cases of Vin > Vout and Vin < Vout.

[0055] In summary, the DC-DC converter according to the embodiments of the present disclosure operates normally in both of these two modes by controlling the voltage of the control pole of the first power transistor and the current sampling ratio in the boost mode (input voltage is less than output voltage) and the buck mode (input voltage is greater than output voltage). Therefore, the DC-DC converter of the embodiments of the present disclosure can be applied to more actual application scenarios.

[0056] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of devices and methods according to multiple embodiments of the present disclosure.At this point, each block in the flowchart or block diagram may represent a module, a segment of a program, or a part of an instruction, and the module, the segment of a program, or the part of an instruction contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions marked in the block may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0057] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0058] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present application.

[0059] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A DC-DC converter, comprising: an inductor, a first power tube, a second power tube, a switch control circuit, a current detection circuit, an output capacitor, a feedback circuit, an error amplifier, and a first comparator, Wherein, the first end of the inductor is coupled to the input voltage end, and the second end of the inductor is coupled to the second electrode of the first power tube and the second electrode of the second power tube; The control electrode of the first power tube is coupled to the first output terminal of the switch control circuit, and the first electrode of the first power tube is coupled to the output voltage terminal; The control electrode of the second power tube is coupled to the second output terminal of the switch control circuit, and the first electrode of the second power tube is coupled to the second voltage terminal; The switch control circuit is configured to: generate a first control signal and a second control signal according to a comparison signal output by the first comparator, a clock signal from a clock signal terminal, a bias voltage from a bias voltage terminal, an input voltage from the input voltage terminal, and an output voltage output from the output voltage terminal, output the first control signal from the first output terminal, and output the second control signal from the second output terminal, wherein, when the input voltage is greater than or equal to the output voltage, the voltage of the first control signal is equal to the bias voltage, and when the input voltage is less than the output voltage, the first control signal and the second control signal are used to alternately turn on the first power transistor and the second power transistor; The current detection circuit is configured to sample a first current flowing through the first power transistor, generate a detection voltage signal based on the sampled current, and provide the detection voltage signal to the first input terminal of the first comparator; The first terminal of the output capacitor is coupled to the output voltage terminal, and the second terminal of the output capacitor is coupled to the second voltage terminal; The feedback circuit is configured to generate a feedback voltage signal according to the output voltage signal output from the output voltage terminal, and provide the feedback voltage signal to the second input terminal of the error amplifier; A first input terminal of the error amplifier is coupled to a reference voltage terminal, and an output terminal of the error amplifier is coupled to a second input terminal of the first comparator.

2. The DC-DC converter according to claim 1, wherein: The switch control circuit includes: a logic control circuit, a voltage selection circuit, a second comparator, and a first inverter. The logic control circuit is configured to: generate a first indication signal and a second indication signal according to the comparison signal and the clock signal, provide the first indication signal from a first output terminal of the logic control circuit to an input terminal of the first inverter, and provide the second indication signal from a second output terminal of the logic control circuit to the control terminal of the second power transistor, wherein the first indication signal and the second indication signal are inverted signals of each other; The output terminal of the first inverter is coupled to the first candidate voltage terminal of the voltage selection circuit; The first input terminal of the second comparator is coupled to the output voltage terminal, the second input terminal of the second comparator is coupled to the input voltage terminal, and the second comparator is configured to: output a first level signal when the input voltage is less than the output voltage, and output a second level signal when the input voltage is greater than or equal to the output voltage; The second candidate voltage terminal of the voltage selection circuit is coupled to the bias voltage terminal, the selection terminal of the voltage selection circuit is coupled to the output terminal of the second comparator, and the output terminal of the voltage selection circuit is coupled to the control terminal of the first power tube. The voltage selection circuit is configured to: when the first level signal is provided to the selection terminal, output the voltage from the first candidate voltage terminal as the first control signal; when the second level signal is provided to the selection terminal, output the bias voltage as the first control signal.

3. The DC-DC converter according to claim 1, wherein: The switch control circuit includes: a logic control circuit, a voltage selection circuit, a second comparator, a first inverter, a second inverter, and a third inverter. The logic control circuit is configured to: generate a first indication signal and a second indication signal according to the comparison signal and the clock signal, provide the first indication signal from a first output terminal of the logic control circuit to an input terminal of the first inverter, and provide the second indication signal from a second output terminal of the logic control circuit to an input terminal of the second inverter, wherein the first indication signal and the second indication signal are inverted signals of each other; The output terminal of the first inverter is coupled to the first candidate voltage terminal of the voltage selection circuit; The first input terminal of the second comparator is coupled to the output voltage terminal, the second input terminal of the second comparator is coupled to the input voltage terminal, and the second comparator is configured to: output a first level signal when the input voltage is less than the output voltage, and output a second level signal when the input voltage is greater than or equal to the output voltage; The second candidate voltage terminal of the voltage selection circuit is coupled to the bias voltage terminal, the selection terminal of the voltage selection circuit is coupled to the output terminal of the second comparator, and the output terminal of the voltage selection circuit is coupled to the control electrode of the first power transistor. The voltage selection circuit is configured to: when the first level signal is provided to the selection terminal, output the voltage from the first candidate voltage terminal as the first control signal; when the second level signal is provided to the selection terminal, output the bias voltage as the first control signal; The output terminal of the second inverter is coupled to the input terminal of the third inverter; An output terminal of the third inverter is coupled to the control electrode of the second power tube.

4. The DC-DC converter according to claim 2 or 3, wherein: The logic control circuit includes: a first NOT gate, a second NOT gate, a third NOT gate, a first NAND gate, and a second NAND gate. The input terminal of the first NOT gate is coupled to the output terminal of the first comparator, and the output terminal of the first NOT gate is coupled to the first input terminal of the first NAND gate; The input terminal of the second NOT gate is coupled to the clock signal terminal, and the output terminal of the second NOT gate is coupled to the second input terminal of the second NAND gate; The second input terminal of the first NAND gate is coupled to the output terminal of the second NAND gate, and the output terminal of the first NAND gate is coupled to the first input terminal of the second NAND gate; The output terminal of the second NAND gate is coupled to the first output terminal of the logic control circuit; An input terminal of the third NOT gate is coupled to the output terminal of the second NAND gate, and an output terminal of the third NOT gate is coupled to the second output terminal of the logic control circuit.

5. The DC-DC converter according to claim 2 or 3, wherein: The current detection circuit includes: a third transistor, a fourth transistor, and a fifth transistor, wherein the control electrode of the third transistor is coupled to the control electrode of the first power transistor, the first electrode of the third transistor is coupled to the first input terminal of the first comparator, and the second electrode of the third transistor is coupled to the second electrode of the first power transistor; A control electrode of the fourth transistor is coupled to the second voltage terminal, a first electrode of the fourth transistor is coupled to the output voltage terminal, and a second electrode of the fourth transistor is coupled to the first input terminal of the first comparator; A control electrode of the fifth transistor is coupled to the output terminal of the second comparator, a first electrode of the fifth transistor is coupled to the output voltage terminal, and a second electrode of the fifth transistor is coupled to the second electrode of the fourth transistor.

6. The DC-DC converter according to claim 1, wherein: The feedback circuit includes: a first resistor and a second resistor, Wherein, a first end of the first resistor is coupled to the output voltage terminal, and a second end of the first resistor is coupled to the second input terminal of the error amplifier; A first terminal of the second resistor is coupled to the second input terminal of the error amplifier, and a second terminal of the second resistor is coupled to the second voltage terminal.

7. The DC-DC converter according to claim 1, further comprising: Clock generation circuit, The clock generation circuit is configured to generate a clock signal and output the clock signal from the clock signal terminal.

8. The DC-DC converter according to claim 1, wherein: The first power tube is a P-type transistor, and the second power tube is an N-type transistor.

9. The DC-DC converter according to claim 1, wherein: The first input terminal of the error amplifier is a non-inverting input terminal, and the second input terminal of the error amplifier is an inverting input terminal; The first input terminal of the first comparator is a non-inverting input terminal, and the second input terminal of the first comparator is an inverting input terminal.

10. A DC-DC converter, comprising: an inductor, a first power tube, a second power tube, third to fifth transistors, first to third NOT gates, a first NAND gate, a second NAND gate, a voltage selection circuit, a second comparator, first to third inverters, an output capacitor, a first resistor, a second resistor, an error amplifier, and a first comparator. Wherein, the first end of the inductor is coupled to the input voltage end, and the second end of the inductor is coupled to the second electrode of the first power tube and the second electrode of the second power tube; The control electrode of the first power tube is coupled to the output terminal of the voltage selection circuit, and the first electrode of the first power tube is coupled to the output voltage terminal; The control electrode of the second power tube is coupled to the output terminal of the third inverter, and the first electrode of the second power tube is coupled to the second voltage terminal; The input terminal of the first NOT gate is coupled to the output terminal of the first comparator, and the output terminal of the first NOT gate is coupled to the first input terminal of the first NAND gate; An input terminal of the second NOT gate is coupled to the clock signal terminal, and an output terminal of the second NOT gate is coupled to the second input terminal of the second NAND gate; The second input terminal of the first NAND gate is coupled to the output terminal of the second NAND gate, and the output terminal of the first NAND gate is coupled to the first input terminal of the second NAND gate; The output terminal of the second NAND gate is coupled to the input terminal of the first inverter; An input terminal of the third NOT gate is coupled to the output terminal of the second NAND gate, and an output terminal of the third NOT gate is coupled to the input terminal of the second inverter; The output terminal of the first inverter is coupled to the first candidate voltage terminal of the voltage selection circuit; The first input terminal of the second comparator is coupled to the output voltage terminal, and the second input terminal of the second comparator is coupled to the input voltage terminal; The second input terminal of the voltage selection circuit is coupled to the bias voltage terminal, the selection terminal of the voltage selection circuit is coupled to the output terminal of the second comparator, and the output terminal of the voltage selection circuit is coupled to the control terminal of the first power transistor. The voltage selection circuit is configured to: output the voltage from the first candidate voltage terminal when the first level signal is provided to the selection terminal, and output the bias voltage when the second level signal is provided to the selection terminal; The output terminal of the second inverter is coupled to the input terminal of the third inverter; The output terminal of the third inverter is coupled to the control electrode of the second power tube; A control electrode of the third transistor is coupled to the control electrode of the first power transistor, a first electrode of the third transistor is coupled to the first input terminal of the first comparator, and a second electrode of the third transistor is coupled to the second electrode of the first power transistor; A control electrode of a fourth transistor is coupled to the second voltage terminal, a first electrode of the fourth transistor is coupled to the output voltage terminal, and a second electrode of the fourth transistor is coupled to the first input terminal of the first comparator; A control electrode of the fifth transistor is coupled to the output terminal of the second comparator, a first electrode of the fifth transistor is coupled to the output voltage terminal, and a second electrode of the fifth transistor is coupled to the second electrode of the fourth transistor; A first end of the first resistor is coupled to the output voltage terminal, and a second end of the first resistor is coupled to the second input terminal of the error amplifier; A first end of the second resistor is coupled to the second input terminal of the error amplifier, and a second end of the second resistor is coupled to the second voltage terminal; The first terminal of the output capacitor is coupled to the output voltage terminal, and the second terminal of the output capacitor is coupled to the second voltage terminal; A first input terminal of the error amplifier is coupled to a reference voltage terminal, and an output terminal of the error amplifier is coupled to a second input terminal of the first comparator.

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