Circuit board with embedded chip and manufacturing method thereof

Abstract

The present application provides a method for manufacturing a circuit board with an embedded chip, comprising the following steps: providing a chip, the chip comprising a first surface and a second surface arranged opposite to each other; forming a first lead frame and a second lead frame on the first surface and the second surface respectively; forming a package body on the side surface of the chip, part of the first surface and part of the second surface to obtain a chip packaging structure; providing a first dielectric layer, the first dielectric layer having a through hole; placing the chip packaging structure in the through hole; and forming a first circuit substrate and a second circuit substrate on the two opposite surfaces of the first dielectric layer and the chip packaging structure respectively, thereby obtaining the circuit board. The present application has a low production cost and high reliability. The present application also provides a circuit board with an embedded chip produced by the production method.

Description

Technical Field

[0001] The present application relates to the technical field of circuit boards, and in particular to a circuit board with an embedded chip and a manufacturing method thereof. Background Art

[0002] With the advancement of technology, electronic products such as mobile phones and laptops are developing in the direction of miniaturization, thinness and multi-function. For this reason, chip embedding technology is becoming more and more popular in the industry. The traditional chip embedding technology is to first embed the bare crystal and then use micropores to connect the chip to the circuit board. However, the use of this chip embedding technology usually has the following problems: it is necessary to add chip handling equipment and circuit board alignment equipment, and expensive materials such as silver sintering are needed to fix the chip on the circuit board. The surface treatment thickness and type of the chip must be able to meet the subsequent drilling and electroplating processes. The quality of the chip needs to be able to be detected during feeding. It is necessary to use more expensive low thermal expansion coefficient plates to avoid the difference in thermal expansion coefficient between the chip and the circuit board, which may cause the circuit board to bend and the chip to crack. Summary of the Invention

[0003] In view of this, the present application provides a method for manufacturing a circuit board with an embedded chip that can solve at least one of the above problems.

[0004] In addition, it is also necessary to provide a circuit board with an embedded chip manufactured by the above manufacturing method.

[0005] An embodiment of the present application provides a method for manufacturing a circuit board with an embedded chip, comprising the following steps:

[0006] Providing a chip, the chip comprising a first surface and a second surface disposed opposite to each other;

[0007] forming a first lead frame and a second lead frame on the first surface and the second surface respectively, and electrically connecting the first lead frame and the second lead frame to the chip, and making the first lead frame and the second lead frame parallel to the first surface and the second surface respectively;

[0008] forming a package body on the side surface, part of the first surface, and part of the second surface of the chip, and positioning the chip in a receiving space enclosed by the package body, the first lead frame, and the second lead frame to obtain a chip package structure;

[0009] Providing a first dielectric layer, wherein a through hole is formed in the first dielectric layer;

[0010] placing the chip package structure in the through hole; and

[0011] A first circuit substrate and a second circuit substrate are respectively formed on two opposing surfaces of the first dielectric layer and the chip packaging structure, thereby obtaining the circuit board, wherein the first circuit substrate includes a first insulating layer formed on one surface of the first dielectric layer and the chip packaging structure, and a first conductive circuit layer provided on the first insulating layer, and the first conductive circuit layer is electrically connected to the first lead frame; and the second circuit substrate includes a second insulating layer formed on the other surface of the first dielectric layer and the chip packaging structure, and a second conductive circuit layer provided on the second insulating layer, and the second conductive circuit layer is electrically connected to the second lead frame.

[0012] An embodiment of the present application further provides a circuit board with an embedded chip, comprising:

[0013] a first dielectric layer, wherein a through hole is formed in the first dielectric layer;

[0014] a chip package structure located in the through-hole, the chip package structure comprising a chip, a first lead frame, a second lead frame, and a package body, the chip comprising a first surface and a second surface oppositely disposed, the first lead frame and the second lead frame being located on the first surface and the second surface, respectively, the first lead frame and the second lead frame being electrically connected to the chip, and the first lead frame and the second lead frame being parallel to the first surface and the second surface, respectively, the package body being located on a side surface of the chip, a portion of the first surface, and a portion of the second surface, the package body, the first lead frame, and the second lead frame jointly enclosing a housing space, and the chip being located within the housing space;

[0015] a first circuit substrate, located on one surface of the first dielectric layer and the chip packaging structure, the first circuit substrate comprising a first insulating layer formed on one surface of the first dielectric layer and the chip packaging structure, and a first conductive circuit layer provided on the first insulating layer, the first conductive circuit layer being electrically connected to the first lead frame; and

[0016] a second circuit substrate, located on the other surface of the first dielectric layer and the chip packaging structure, comprising a second insulating layer formed on the first dielectric layer and the other surface of the chip packaging structure, and a second conductive circuit layer provided on the second insulating layer, wherein the second conductive circuit layer is electrically connected to the second lead frame.

[0017] The present application forms a package body on the side surface of the chip, a portion of the first surface, and a portion of the second surface to obtain a chip package structure. Furthermore, a first circuit substrate and a second circuit substrate are formed on the first dielectric layer and on opposing surfaces of the chip package structure to obtain the circuit board. This avoids the use of chip handling equipment and expensive materials such as silver sintering, thereby reducing production costs. Furthermore, the package body exhibits higher reliability than the plates used in conventional methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic structural diagram of the chip provided in the first embodiment of the present application.

[0019] Figure 2 is Figure 1 The diagram shows a structure in which a first lead frame and a second lead frame are formed on the first surface and the second surface respectively, and a package body is formed on the side surface of the chip, a portion of the first surface, and a portion of the second surface.

[0020] Figure 3 Schematic diagram of the structure of the first dielectric layer provided in the first embodiment of the present application.

[0021] Figure 4 Is to put multiple Figure 2 The chip package structure shown is placed in Figure 3 The schematic diagram of the structure after the through hole is shown.

[0022] Figure 5 is Figure 4 The schematic diagram shows the structure of the circuit board obtained by sequentially forming a first circuit substrate, a third circuit substrate and a fourth circuit substrate on one surface of the first dielectric layer and the chip packaging structure, and forming a second circuit substrate on the other surface of the first dielectric layer and the chip packaging structure.

[0023] Figure 6 It is a structural diagram of the chip packaging structure provided in the second embodiment of the present application.

[0024] Figure 7 Schematic diagram of the structure of the first dielectric layer provided in the second embodiment of the present application.

[0025] Figure 8 This is a schematic diagram of the structure of the circuit board provided in the second embodiment of the present application.

[0026] Description of main component symbols

[0027] Circuit board 100, 200

[0028] Chip 10

[0029] First surface 101

[0030] Second surface 102

[0031] First lead frame 20

[0032] First main body 201

[0033] First extension portion 202

[0034] Second lead frame 21

[0035] Second main body 211

[0036] Second extension portion 212

[0037] Packages 30 and 31

[0038] Chip packaging structures 40 and 41

[0039] First dielectric layers 50 and 51

[0040] Through hole 501

[0041] First groove 511

[0042] Second groove 512

[0043] First circuit substrate 60

[0044] First insulating layer 601

[0045] First conductive circuit layer 602

[0046] Second circuit substrate 70

[0047] Second insulating layer 701

[0048] Second conductive circuit layer 702

[0049] Third circuit substrate 80

[0050] The third insulating layer 801

[0051] The third conductive circuit layer 802

[0052] Fourth conductive circuit layer 803

[0053] Fourth circuit substrate 81

[0054] Fourth insulating layer 811

[0055] Fifth conductive circuit layer 812

[0056] Sixth conductive circuit layer 813

[0057] Second dielectric layer 90

[0058] The third dielectric layer 91

[0059] First conductive portion 92

[0060] Second conductive portion 93

[0061] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0064] In order to further illustrate the technical means and effects adopted by this application to achieve the intended purpose, the following detailed description of this application is made in conjunction with the accompanying drawings and preferred implementation methods.

[0065] A first embodiment of the present application provides a method for manufacturing a circuit board with an embedded chip, comprising the following steps:

[0066] Step S11, please refer to Figure 1 , providing a plurality of chips 10.

[0067] Each of the chips 10 includes a first surface 101 and a second surface 102 that are oppositely disposed.

[0068] Step S12, please refer to Figure 2 A first lead frame 20 and a second lead frame 21 are formed on the first surface 101 and the second surface 102 respectively.

[0069] The first lead frame 20 and the second lead frame 21 are both electrically connected to the chip 10 , and the first lead frame 20 and the second lead frame 21 are parallel to the first surface 101 and the second surface 102 , respectively.

[0070] In this embodiment, the first lead frame 20 includes a first main body 201 and a first extension 202 formed by extending from one end of the first main body 201. The first main body 201 is located on the first surface 101, and the first extension 202 protrudes from one side of the chip 10. The first extension 202 can be used for subsequent connection with the circuit substrate (see FIG. Figure 5 ) between them.

[0071] In this embodiment, the second lead frame 21 includes a second main body 211 and a second extension 212 formed by extending from one end of the second main body 211. The second main body 211 is located on the second surface 102, and the second extension 212 protrudes from the other side of the chip 10. The second extension 212 can be used for subsequent connection with the circuit substrate (see FIG. Figure 5 ) between them.

[0072] In step S13 , a package body 30 is formed on the side surface of the chip 10 , a portion of the first surface 101 , and a portion of the second surface 102 to obtain a chip package structure 40 .

[0073] The chip 10 is located in a receiving space (not shown) enclosed by the package body 30 , the first lead frame 20 , and the second lead frame 21 .

[0074] In one embodiment, the first lead frame 20 is embedded in the package body 30 . That is, the first main portion 201 and the first extension portion 202 are both embedded in the package body 30 , and the surface of the first lead frame 20 away from the chip 10 is substantially flush with one surface of the package body 30 .

[0075] In one embodiment, the second lead frame 21 is also embedded in the package body 30 . That is, the second main portion 211 and the second extension portion 212 are both embedded in the package body 30 , and the surface of the second lead frame 21 away from the chip 10 is substantially flush with another surface of the package body 30 .

[0076] In this embodiment, the package body 30 may be formed by an injection molding process.

[0077] Step S14, please refer to Figure 3 , providing a first dielectric layer 50.

[0078] The first dielectric layer 50 is provided with at least one through hole 501 , which passes through the first dielectric layer 50 .

[0079] The material of the first dielectric layer 50 can be selected from epoxy resin, polypropylene (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). In this embodiment, the material of the first dielectric layer 50 is polypropylene.

[0080] Step S15, please refer to Figure 4 , placing the chip packaging structure 40 in the through hole 501 .

[0081] The surface of the chip packaging structure 40 is substantially flush with the surface of the first dielectric layer 50 , that is, the height of the chip packaging structure 40 is substantially equal to the depth of the through hole 501 .

[0082] like Figure 4 As shown, the two chip packaging structures 40 are placed in the two through holes 501 respectively.

[0083] Step S16, see Figure 5 A first circuit substrate 60 and a second circuit substrate 70 are respectively formed on two opposite surfaces of the first dielectric layer 50 and the chip packaging structure 40 , thereby obtaining the circuit board 100 .

[0084] In one embodiment, the first circuit substrate 60 includes a first insulating layer 601 formed on one surface of the first dielectric layer 50 and the chip package structure 40, and a first conductive circuit layer 602 disposed on the first insulating layer 601. It should be noted that in this embodiment, the first circuit substrate 60 may be a single-sided circuit substrate; in other embodiments, the first circuit substrate 60 may also be a double-sided circuit substrate.

[0085] The material of the first insulating layer 601 can be selected from one of the resins such as epoxy resin, polypropylene (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). In this embodiment, the material of the first insulating layer 601 is polyimide.

[0086] In one embodiment, the second circuit substrate 70 includes a second insulating layer 701 formed on the other surface of the first dielectric layer 50 and the chip package structure 40, and a second conductive circuit layer 702 disposed on the second insulating layer 701. It should be noted that in this embodiment, the second circuit substrate 70 may be a single-sided circuit substrate; in other embodiments, the second circuit substrate 70 may also be a double-sided circuit substrate.

[0087] In this embodiment, the material of the second insulating layer 701 may be the same as that of the first insulating layer 601 . For details, please refer to the material of the first insulating layer 601 , which will not be described in detail here.

[0088] In this embodiment, a third circuit substrate 80 and a fourth circuit substrate 81 may be sequentially formed on the first circuit substrate 60 to obtain the circuit board 100. A second dielectric layer 90 is provided between the first circuit substrate 60 and the third circuit substrate 80, and a third dielectric layer 91 is provided between the third circuit substrate 80 and the fourth circuit substrate 81.

[0089] In one embodiment, the third circuit substrate 80 includes a third insulating layer 801 and a third conductive circuit layer 802 and a fourth conductive circuit layer 803 disposed on opposite surfaces of the third insulating layer 801. The third conductive circuit layer 802 is disposed on a surface of the second dielectric layer 90.

[0090] In one embodiment, the fourth circuit substrate 81 includes a fourth insulating layer 811 and a fifth conductive circuit layer 812 and a sixth conductive circuit layer 813 disposed on opposite surfaces of the fourth insulating layer 811. The fifth conductive circuit layer 812 is disposed on a surface of the third dielectric layer 91.

[0091] In this embodiment, the materials of the third insulating layer 801 and the fourth insulating layer 811 can be the same as the material of the first insulating layer 601 . For details, please refer to the material of the first insulating layer 601 , which will not be described in detail here.

[0092] In this embodiment, the materials of the second dielectric layer 90 and the third dielectric layer 91 can be the same as the material of the first dielectric layer 50 . For details, please refer to the material of the first dielectric layer 50 , which will not be described in detail here.

[0093] The circuit board 100 is provided with a first conductive portion 92 and a second conductive portion 93. The first conductive portion 92 sequentially penetrates the fourth circuit substrate 81, the third dielectric layer 91, the third circuit substrate 80, the second dielectric layer 90, the first circuit substrate 60, the first extension portion 202, the package body 30, and the second circuit substrate 70. The first conductive portion 92 is used to electrically connect the sixth conductive circuit layer 813, the fifth conductive circuit layer 812, the fourth conductive circuit layer 803, the third conductive circuit layer 802, the first conductive circuit layer 602, the first extension portion 202, and the second conductive circuit layer 702, so that the sixth conductive circuit layer 813, the fifth conductive circuit layer 812, the fourth conductive circuit layer 803, the third conductive circuit layer 802, the first conductive circuit layer 602, and the second conductive circuit layer 702 are all electrically connected to the chip 10.

[0094] The second conductive portion 93 sequentially passes through the fourth circuit substrate 81, the third dielectric layer 91, the third circuit substrate 80, the second dielectric layer 90, the first circuit substrate 60, the package body 30, the second extension portion 212, and the second circuit substrate 70. The second conductive portion 93 is used to electrically connect the sixth conductive circuit layer 813, the fifth conductive circuit layer 812, the fourth conductive circuit layer 803, the third conductive circuit layer 802, the first conductive circuit layer 602, the second extension portion 212, and the second conductive circuit layer 702, so that the sixth conductive circuit layer 813, the fifth conductive circuit layer 812, the fourth conductive circuit layer 803, the third conductive circuit layer 802, the first conductive circuit layer 602, and the second conductive circuit layer 702 are all electrically connected to the chip 10.

[0095] A second embodiment of the present application provides a method for manufacturing a circuit board with an embedded chip. The difference between the manufacturing method provided in the second embodiment and the manufacturing method provided in the first embodiment is that:

[0096] See also Figure 6In step S13, the first lead frame 20 is partially embedded in the package body 31. Specifically, the first main body 201 is embedded in the package body 31, and the first extension 202 is partially embedded in the package body 31. Specifically, the end of the first extension 202 away from the first main body 201 protrudes from one side surface of the package body 31. The second lead frame 21 is also partially embedded in the package body 31. Specifically, the second main body 211 is embedded in the package body 31, and the second extension 212 is partially embedded in the package body 31. Specifically, the end of the second extension 212 away from the second main body 211 protrudes from the other side surface of the package body 31.

[0097] See also Figure 7 In step S14 , a first groove 511 and a second groove 512 are further formed in the first dielectric layer 51 . The first groove 511 and the second groove 512 are located on different surfaces of the first dielectric layer 51 , and both the first groove 511 and the second groove 512 are connected to the through hole 501 .

[0098] See also Figure 8 In step S15 , the chip packaging structure 40 is placed in the through hole 501 , and the first extension portion 202 and the second extension portion 212 are located in the first groove 511 and the second groove 512 , respectively.

[0099] In step S16, Figure 8 As shown, neither the first conductive portion 92 nor the second conductive portion 93 penetrates the package body 31 , and both the first conductive portion 92 and the second conductive portion 93 penetrate the first dielectric layer 50 .

[0100] See also Figure 5 The first embodiment of the present application also provides a circuit board 100 with an embedded chip, wherein the circuit board 100 includes a first dielectric layer 50, multiple chip packaging structures 40, a first circuit substrate 60, a second circuit substrate 70, a second dielectric layer 90, a third circuit substrate 80, a third dielectric layer 91 and a fourth circuit substrate 81.

[0101] At least one through hole 501 is defined in the first dielectric layer 50 , wherein the through hole 501 passes through the first dielectric layer 50 .

[0102] The material of the first dielectric layer 50 can be selected from epoxy resin, polypropylene (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). In this embodiment, the material of the first dielectric layer 50 is polypropylene.

[0103] The chip packaging structure 40 is located in the through hole 501. The surface of the chip packaging structure 40 is substantially flush with the surface of the first dielectric layer 50. That is, the height of the chip packaging structure 40 is substantially equal to the depth of the through hole 501. Figure 5 As shown, the two chip package structures 40 are respectively located in the two through holes 501. The chip package structure 40 includes a chip 10, a first lead frame 20, a second lead frame 21 and a package body 30.

[0104] Each of the chips 10 includes a first surface 101 and a second surface 102 that are oppositely disposed.

[0105] The first lead frame 20 and the second lead frame 21 are located on the first surface 101 and the second surface 102 respectively.

[0106] The first lead frame 20 and the second lead frame 21 are both electrically connected to the chip 10 , and the first lead frame 20 and the second lead frame 21 are parallel to the first surface 101 and the second surface 102 , respectively.

[0107] In this embodiment, the first lead frame 20 includes a first main portion 201 and a first extension portion 202 extending from one end of the first main portion 201. The first main portion 201 is located on the first surface 101, and the first extension portion 202 protrudes from one side surface of the chip 10. The first extension portion 202 can be used for alignment with the first circuit substrate 60, the third circuit substrate 80, and the fourth circuit substrate 81.

[0108] In this embodiment, the second lead frame 21 includes a second main portion 211 and a second extension portion 212 extending from one end of the second main portion 211. The second main portion 211 is located on the second surface 102, and the second extension portion 212 protrudes from the other side of the chip 10. The second extension portion 212 can be used for alignment with the second circuit substrate 70.

[0109] The package body 30 is located on a side surface of the chip 10 , a portion of the first surface 101 , and a portion of the second surface 102 .

[0110] The package body 30 , the first lead frame 20 , and the second lead frame 21 are collectively arranged to form a receiving space (not shown), and the chip 10 is located in the receiving space.

[0111] In one embodiment, the first lead frame 20 is embedded in the package body 30 . That is, the first main portion 201 and the first extension portion 202 are both embedded in the package body 30 , and the surface of the first lead frame 20 away from the chip 10 is substantially flush with one surface of the package body 30 .

[0112] In one embodiment, the second lead frame 21 is also embedded in the package body 30 . That is, the second main portion 211 and the second extension portion 212 are both embedded in the package body 30 , and the surface of the second lead frame 21 away from the chip 10 is substantially flush with another surface of the package body 30 .

[0113] The first circuit substrate 60 is located on one surface of the first dielectric layer 50 and the chip packaging structure 40. In one embodiment, the first circuit substrate 60 includes a first insulating layer 601 formed on one surface of the first dielectric layer 50 and the chip packaging structure 40, and a first conductive circuit layer 602 disposed on the first insulating layer 601. It should be noted that in this embodiment, the first circuit substrate 60 may be a single-sided circuit substrate. In other embodiments, the first circuit substrate 60 may also be a double-sided circuit substrate.

[0114] The material of the first insulating layer 601 can be selected from one of epoxy resin, polypropylene (PP), BT resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). In this embodiment, the material of the first insulating layer 601 is polyimide.

[0115] The second circuit substrate 70 is located on the other surface of the first dielectric layer 50 and the chip packaging structure 40. In one embodiment, the second circuit substrate 70 includes a second insulating layer 701 formed on the other surface of the first dielectric layer 50 and the chip packaging structure 40, and a second conductive circuit layer 702 disposed on the second insulating layer 701. It should be noted that in this embodiment, the second circuit substrate 70 can be a single-sided circuit substrate. In other embodiments, the second circuit substrate 70 can also be a double-sided circuit substrate.

[0116] In this embodiment, the second insulating layer 701 may be made of the same material as the first insulating layer 601 . For details, please refer to the material of the first insulating layer 601 , which will not be described in detail here.

[0117] The second dielectric layer 90 is located on the surface of the first conductive circuit layer 602. In this embodiment, the material of the second dielectric layer 90 can be the same as that of the first dielectric layer 50. For details, please refer to the material of the first dielectric layer 50, which will not be described in detail here.

[0118] The third circuit substrate 80 is located on a surface of the second dielectric layer 90. In one embodiment, the third circuit substrate 80 includes a third insulating layer 801 and a third conductive circuit layer 802 and a fourth conductive circuit layer 803 disposed on opposite surfaces of the third insulating layer 801. The third conductive circuit layer 802 is disposed on a surface of the second dielectric layer 90.

[0119] In this embodiment, the material of the third insulating layer 801 may be the same as the material of the first insulating layer 601 . For details, please refer to the material of the first insulating layer 601 , which will not be described in detail here.

[0120] The third dielectric layer 91 is located on the surface of the fourth conductive circuit layer 803. In this embodiment, the material of the third dielectric layer 91 can be the same as that of the first dielectric layer 50. For details, please refer to the material of the first dielectric layer 50 and will not be described in detail here.

[0121] The fourth circuit substrate 81 is located on a surface of the third dielectric layer 91. In one embodiment, the fourth circuit substrate 81 includes a fourth insulating layer 811 and a fifth conductive circuit layer 812 and a sixth conductive circuit layer 813 disposed on opposite surfaces of the fourth insulating layer 811. The fifth conductive circuit layer 812 is disposed on a surface of the third dielectric layer 91.

[0122] In this embodiment, the material of the fourth insulating layer 811 may be the same as the material of the first insulating layer 601 . For details, please refer to the material of the first insulating layer 601 , which will not be described in detail here.

[0123] The circuit board 100 is provided with a first conductive portion 92 and a second conductive portion 93. The first conductive portion 92 sequentially penetrates the fourth circuit substrate 81, the third dielectric layer 91, the third circuit substrate 80, the second dielectric layer 90, the first circuit substrate 60, the first extension portion 202, the package body 30, and the second circuit substrate 70. The first conductive portion 92 is used to electrically connect the sixth conductive circuit layer 813, the fifth conductive circuit layer 812, the fourth conductive circuit layer 803, the third conductive circuit layer 802, the first conductive circuit layer 602, the first extension portion 202, and the second conductive circuit layer 702, so that the sixth conductive circuit layer 813, the fifth conductive circuit layer 812, the fourth conductive circuit layer 803, the third conductive circuit layer 802, the first conductive circuit layer 602, and the second conductive circuit layer 702 are all electrically connected to the chip 10.

[0124] The second conductive portion 93 sequentially passes through the fourth circuit substrate 81, the third dielectric layer 91, the third circuit substrate 80, the second dielectric layer 90, the first circuit substrate 60, the package body 30, the second extension portion 212, and the second circuit substrate 70. The second conductive portion 93 is used to electrically connect the sixth conductive circuit layer 813, the fifth conductive circuit layer 812, the fourth conductive circuit layer 803, the third conductive circuit layer 802, the first conductive circuit layer 602, the second extension portion 212, and the second conductive circuit layer 702, so that the sixth conductive circuit layer 813, the fifth conductive circuit layer 812, the fourth conductive circuit layer 803, the third conductive circuit layer 802, the first conductive circuit layer 602, and the second conductive circuit layer 702 are all electrically connected to the chip 10.

[0125] See also Figure 8The second embodiment of the present application further provides a circuit board 200 with an embedded chip. The circuit board 200 provided in the second embodiment differs from the circuit board 100 provided in the first embodiment in that:

[0126] The first lead frame 20 is partially embedded in the package body 31. Specifically, the first main portion 201 is embedded in the package body 31, and the first extension portion 202 is partially embedded in the package body 31. Specifically, the end of the first extension portion 202 away from the first main portion 201 protrudes from one side surface of the package body 31. The second lead frame 21 is also partially embedded in the package body 31. Specifically, the second main portion 211 is embedded in the package body 31, and the second extension portion 212 is partially embedded in the package body 31. Specifically, the end of the second extension portion 212 away from the second main portion 211 protrudes from the other side surface of the package body 31.

[0127] The first dielectric layer 51 further defines a first groove 511 and a second groove 512. The first groove 511 and the second groove 512 are located on different surfaces of the first dielectric layer 51 and are both connected to the through hole 501. The first extension 202 and the second extension 212 are located in the first groove 511 and the second groove 512, respectively.

[0128] The first conductive portion 92 and the second conductive portion 93 do not penetrate the package body 31 , and both the first conductive portion 92 and the second conductive portion 93 penetrate the first dielectric layer 50 .

[0129] In this application, a package body 30 is formed on the side surface of the chip 10, a portion of the first surface 101, and a portion of the second surface 102 to obtain a chip package structure 40. Furthermore, a first circuit substrate 60 and a second circuit substrate 70 are formed on the opposing surfaces of the first dielectric layer 50 and the chip package structure 40, respectively, to obtain the circuit board 100. This avoids the use of chip handling equipment and expensive materials such as silver sintering, thereby reducing production costs. Furthermore, the package body 30 has higher reliability than the plates used in traditional methods.

[0130] The present invention can also reduce the number of press-fits, thereby reducing the risk of cracking the chip 10. Instead of drilling and plating on the chip 10, the present invention mechanically drills and electroplates on the lead frame after embedding the chip 10, thereby reducing contact damage to the chip 10.

[0131] The above description is merely an optimized specific implementation of the present application, but in actual application, it cannot be limited to this implementation.

Claims

1. A method for manufacturing a circuit board with an embedded chip, characterized in that: The following steps are involved: Providing a chip, the chip comprising a first surface and a second surface disposed opposite to each other; forming a first lead frame and a second lead frame on the first surface and the second surface respectively, and electrically connecting the first lead frame and the second lead frame to the chip, and making the first lead frame and the second lead frame parallel to the first surface and the second surface respectively; The first lead frame includes a first main body and a first extension formed by extending from one end of the first main body, the first main body is located on the first surface, and the first extension protrudes from one side surface of the chip; the second lead frame includes a second main body and a second extension formed by extending from one end of the second main body, the second main body is located on the second surface, and the second extension protrudes from the other side surface of the chip; forming a package body on the side surface, part of the first surface, and part of the second surface of the chip, and positioning the chip in a receiving space enclosed by the package body, the first lead frame, and the second lead frame to obtain a chip package structure; Providing a first dielectric layer, wherein a through hole is formed in the first dielectric layer; placing the chip packaging structure in the through hole; as well as A first circuit substrate and a second circuit substrate are respectively formed on two opposing surfaces of the first dielectric layer and the chip packaging structure, thereby obtaining the circuit board, wherein the first circuit substrate includes a first insulating layer formed on one surface of the first dielectric layer and the chip packaging structure, and a first conductive circuit layer provided on the first insulating layer, and the first conductive circuit layer is electrically connected to the first lead frame; and the second circuit substrate includes a second insulating layer formed on the other surface of the first dielectric layer and the chip packaging structure, and a second conductive circuit layer provided on the second insulating layer, and the second conductive circuit layer is electrically connected to the second lead frame.

2. The method for manufacturing a circuit board according to claim 1, wherein: The circuit board is provided with a first conductive part and a second conductive part, the first conductive part is used to electrically connect the first conductive circuit layer, the first extension part and the second conductive circuit layer, and the second conductive part is used to electrically connect the first conductive circuit layer, the second extension part and the second conductive circuit layer.

3. The method for manufacturing a circuit board according to claim 2, wherein: Also includes: forming a second dielectric layer and a third circuit substrate in sequence on the surface of the first circuit substrate; The third circuit substrate includes a third insulating layer and a third conductive circuit layer and a fourth conductive circuit layer provided on two opposite surfaces of the third insulating layer. The third conductive circuit layer is provided on the surface of the second dielectric layer. The first conductive portion and the second conductive portion are provided in the third circuit substrate and the second dielectric layer. The third conductive circuit layer is electrically connected to the first extension portion via the first conductive portion, and the fourth conductive circuit layer is electrically connected to the second extension portion via the second conductive portion.

4. The method for manufacturing a circuit board according to claim 2, wherein: One end of the first extension portion away from the first main portion protrudes from one side surface of the package body, and one end of the second extension portion away from the second main portion protrudes from the other side surface of the package body. The first dielectric layer is further provided with a first groove and a second groove. The first groove and the second groove are located on different surfaces of the first dielectric layer, and both the first groove and the second groove are connected to the through hole. After the chip packaging structure is placed in the through hole, the first extension portion and the second extension portion are respectively located in the first groove and the second groove.

5. The method for manufacturing a circuit board according to claim 1, wherein: A surface of the first lead frame away from the chip is flush with one surface of the package body, and a surface of the second lead frame away from the chip is flush with the other surface of the package body.

6. A circuit board with an embedded chip, characterized in that: include: a first dielectric layer, wherein a through hole is formed in the first dielectric layer; a chip package structure located in the through hole, the chip package structure comprising a chip, a first lead frame, a second lead frame, and a package body, the chip comprising a first surface and a second surface opposite to each other, the first lead frame and the second lead frame being located on the first surface and the second surface, respectively, the first lead frame and the second lead frame being electrically connected to the chip, and the first lead frame and the second lead frame being parallel to the first surface and the second surface, respectively, the package body being located on a side surface of the chip, a portion of the first surface, and a portion of the second surface, the package body, the first lead frame, and the second lead frame jointly enclosing a housing space, and the chip being located in the housing space, the first lead frame comprising a first main portion and a first extension portion extending from one end of the first main portion, the first main portion being located on the first surface, the first extension portion protruding from one side surface of the chip, the second lead frame comprising a second main portion and a second extension portion extending from one end of the second main portion, the second main portion being located on the second surface, the second extension portion protruding from the other side surface of the chip; a first circuit substrate, located on one surface of the first dielectric layer and the chip packaging structure, the first circuit substrate comprising a first insulating layer formed on one surface of the first dielectric layer and the chip packaging structure, and a first conductive circuit layer provided on the first insulating layer, the first conductive circuit layer being electrically connected to the first lead frame; as well as a second circuit substrate, located on the other surface of the first dielectric layer and the chip packaging structure, comprising a second insulating layer formed on the first dielectric layer and the other surface of the chip packaging structure, and a second conductive circuit layer provided on the second insulating layer, wherein the second conductive circuit layer is electrically connected to the second lead frame.

7. The circuit board according to claim 6, wherein: The circuit board is provided with a first conductive part and a second conductive part, the first conductive part is used to electrically connect the first conductive circuit layer, the first extension part and the second conductive circuit layer, and the second conductive part is used to electrically connect the first conductive circuit layer, the second extension part and the second conductive circuit layer.

8. The circuit board according to claim 7, wherein: Also includes: a second dielectric layer, located on a surface of the first circuit substrate; a third circuit substrate, located on a surface of the second dielectric layer; The third circuit substrate includes a third insulating layer and a third conductive circuit layer and a fourth conductive circuit layer provided on two opposite surfaces of the third insulating layer. The third conductive circuit layer is provided on the surface of the second dielectric layer. The first conductive portion and the second conductive portion are provided in the third circuit substrate and the second dielectric layer. The third conductive circuit layer is electrically connected to the first extension portion via the first conductive portion, and the fourth conductive circuit layer is electrically connected to the second extension portion via the second conductive portion.

9. The circuit board according to claim 7, wherein: One end of the first extension portion away from the first main portion protrudes from one side surface of the package body, and one end of the second extension portion away from the second main portion protrudes from the other side surface of the package body. A first groove and a second groove are also provided in the first dielectric layer. The first groove and the second groove are located on different surfaces of the first dielectric layer, and both the first groove and the second groove are connected to the through hole. The first extension portion and the second extension portion are respectively located in the first groove and the second groove.

10. The circuit board according to claim 6, wherein: A surface of the first lead frame away from the chip is flush with one surface of the package body, and a surface of the second lead frame away from the chip is flush with the other surface of the package body.

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