BMC chip with DMA function virtual serial port and use method

Abstract

The application discloses a BMC chip with a virtual serial port with DMA function and a use method, and relates to the technical field of BMC chips, and comprises a Core module, a DDR module, a GMAC module and a virtual serial port, wherein the virtual serial port comprises a first UART controller, a second UART controller and a DMA controller; the first UART controller is connected with an external Host end; output pins of the first UART controller are connected with input pins of the second UART controller, and output pins of the second UART controller are connected with input pins of the first UART controller; the second UART controller is connected with the DMA controller, and the DMA controller is connected with the DDR module; the Core module is connected with the virtual serial port, the DDR module and the GMAC module respectively; and the GMAC module is connected with the DDR module and an external Client end respectively. Through the virtual serial port with the DMA function, the data interaction problem between the BMC chip and the Host end and the slow data interaction efficiency problem are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to a BMC chip with DMA function virtual serial port and a use method, and belongs to the chip front-end design technical field. BACKGROUND

[0002] UART (Universal Asynchronous Receiver / Transmitter) is a universal asynchronous receiver / transmitter device that receives parallel information in the chip, converts the information from the serial port, and outputs data from the serial port. At the same time, it can receive data from the serial port, convert it, and transmit data in the chip. As a device that has been developed for many years and has been updated for many generations, UART has high completeness in technology and function. According to the application scenario, the UART is changed into a "virtual serial port" by assembling and recombining. This "virtual serial port" can be applied to local debugging, remote monitoring and display, firmware loading and other scenarios of the server.

[0003] Currently, the transmission efficiency of the virtual serial port technology is not high. Each byte of data needs to read and write a register once. If there is a large amount of data to be transmitted and received, according to the current working mechanism, it will greatly affect the transmission efficiency and also occupy the core process of the chip.

[0004] The information disclosed in this BACKGROUND section is only intended to increase an understanding of the general context in which the present application can be practiced. It is not admitted that any of the information provided in this section constitutes prior art against the present application. SUMMARY

[0005] The purpose of the present application is to overcome the deficiencies in the prior art, provide a BMC chip with DMA function virtual serial port and a use method, by setting a virtual serial port with DMA function, the problem of data interaction between the BMC chip and the Host end and the problem of slow interaction data efficiency are solved.

[0006] To achieve the above purpose, the present application adopts the following technical scheme:

[0007] On the one hand, the present application discloses a BMC chip with DMA function virtual serial port, which comprises a Core module, a DDR module, a GMAC module and a virtual serial port, wherein the virtual serial port comprises a first UART controller, a second UART controller and a DMA controller.

[0008] The first UART controller is connected to an external Host end.

[0009] The output pin of the first UART controller is connected with the input pin of the second UART controller, and the output pin of the second UART controller is connected with the input pin of the first UART controller;

[0010] The second UART controller is connected with a DMA controller, and the DMA controller is connected with a DDR module.

[0011] The Core module is connected with a virtual serial port, a DDR module and a GMAC module respectively, and the GMAC module is connected with the DDR module and an external Client.

[0012] Further,

[0013] The first UART controller is connected with a Host through a first Bus module.

[0014] The Core module is connected with a virtual serial port and a GMAC module through a second Bus module respectively.

[0015] The DMA controller and the GMAC module are connected with a DDR module through a third Bus module respectively.

[0016] Further, the GMAC module is connected with a Client through a LAN network cable.

[0017] Further, the first UART controller is used for serving an external Host, and the second UART controller is used for serving the Core module.

[0018] In another aspect, the application discloses a use method of a BMC chip with a virtual serial port with DMA function, which is applied to the BMC chip with the virtual serial port with DMA function and comprises the following steps:

[0019] Initializing the virtual serial port and allocating a Host virtual serial port permission;

[0020] In a TX process, debugging data is acquired and written into a DDR module; a DMA controller is configured to read back the debugging data in the DDR module and write the debugging data into a second UART controller.

[0021] In an RX process, the DMA controller is configured to receive debugging data of the second UART controller and write the debugging data into the DDR module; and a Core module sends the debugging data in the DDR module.

[0022] Further, the initialization of the virtual serial port comprises setting of a baud rate clock, setting of a frame format, FIFO setting and setting of interrupt enable.

[0023] Further, in the TX process, debug data is acquired and written into the DDR module, including the following steps:

[0024] If it is local debugging, the Core module directly acquires the debug data and writes it into the DDR module.

[0025] If it is remote debugging, the Core module configures the GMAC module, so that the GMAC module acquires the debug data returned by the Client end and writes it into the DDR module.

[0026] Further, in the RX process, debug data in the DDR module is sent, including the following steps:

[0027] If it is local debugging, the Core module reads back the debug data in the DDR module and sends it.

[0028] If it is remote debugging, the Core module configures the GMAC module, so that the GMAC module reads back the debug data in the DDR module and packages and sends it to the external Client end.

[0029] Compared with the prior art, the present application has the following beneficial effects:

[0030] The BMC chip with the DMA function virtual serial port and the use method solve the problem of data interaction between the BMC chip and the Host end and the problem of slow interaction data efficiency.

[0031] The present application guarantees the data interaction mode of serial-to-parallel reception and parallel-to-serial transmission of the debug data on the virtual serial port, and guarantees that the virtual serial port is always working in the case of sufficient data, greatly improving the work efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 It is a structural schematic diagram of the BMC chip with the DMA function virtual serial port.

[0033] Figure 2 It is a work flow diagram of the BMC chip with the DMA function virtual serial port in the TX process.

[0034] Figure 3 It is a work flow diagram of the DMA controller in the TX process.

[0035] Figure 4 It is a work flow diagram of the BMC chip with the DMA function virtual serial port in the RX process.

[0036] Figure 5 It is a work flow diagram of the DMA controller in the RX process. Detailed Implementation

[0037] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention. Example

[0038] This embodiment discloses a BMC chip with a virtual serial port featuring DMA functionality, such as... Figure 1 As shown, it includes a Core module, a DDR module, a GMAC module, and a virtual serial port. The virtual serial port includes a first UART controller, a second UART controller, and a DMA controller.

[0039] The first UART controller is connected to an external host.

[0040] The output pins of the first UART controller are connected to the input pins of the second UART controller, and the output pins of the second UART controller are connected to the input pins of the first UART controller.

[0041] The second UART controller is connected to the DMA controller, and the DMA controller is connected to the DDR module.

[0042] The Core module connects to the virtual serial port, the DDR module, and the GMAC module, respectively; the GMAC module connects to the DDR module and the external client.

[0043] The technical concept of this invention is to establish a virtual serial port with DMA function to serve the server and meet the needs of local debugging, remote monitoring and display, and firmware loading of the server, while reducing the burden on the Core module and improving transmission efficiency.

[0044] It should be noted that the first UART controller is used to serve the host side, and the second UART controller is used to serve the core module of the BMC chip.

[0045] Furthermore, the first UART controller is connected to the host via the first Bus module;

[0046] The Core module is connected to the virtual serial port and the GMAC module via the second Bus module;

[0047] The DMA controller and GMAC module are connected to the DDR module via the third Bus module.

[0048] Furthermore, the GMAC module is connected to the client via a LAN cable.

[0049] The BMC chip with the DMA function virtual serial port relates to two work flows, respectively, a TX data sending work flow and a RX data receiving work flow.

[0050] The TX data sending work flow is as shown in the figure Figure 2 The DMA controller reads back the debugging data from the DDR module, writes the debugging data to the second UART controller, and the second UART controller sends out the debugging data from the output pin, the first UART controller receives the debugging data through the input pin, and the first UART controller sends the debugging data to the external Host. Specifically, the steps include the following steps:

[0051] (1) Initialize the virtual serial port:

[0052] The Core module sends an initialization configuration instruction to the second UART controller, so that the second UART controller sets the baud rate clock, sets the frame format, sets the FIFO, and sets the interrupt enable.

[0053] Specifically, the baud rate clock setting: the second UART controller needs an external clock as a reference clock for transmitting data when transmitting serial port data. Specifically, a baud rate reference clock needs to be selected for serial port data transmission. The external clock after frequency division is called the baud rate actual clock. And there is an error between the baud rate actual clock after frequency division and the baud rate reference clock. All bits in the character transmission occupy 16 baud rate clock periods. The receiver samples the central position of each bit time after detecting the start bit, and the sampling period is also 16 baud rate clock periods. Therefore, the above-mentioned frequency division number needs to be configured by the Core into the register of the second UART controller.

[0054] Frame format setting: in order to realize the synchronization consistency of serial port data transmission, the start bit and the stop bit are added to the data transmitted by the UART controller to indicate the start and end of data transmission. Overall, the bit string composed of the start bit, the data bit, the check bit and the stop bit is regarded as a "character" / frame. The start bit is 1 bit, the data bit is 5-8 bits, the check bit is 1 bit, and the stop bit is 1 / 1.5 / 2 bits. The above character format needs to be configured by the Core into the register of the second UART controller.

[0055] FIFO setting: there are two ways to store data written into the second UART controller, one is not to use FIFO, and only one byte of data (8-bit data) can be stored in the second UART controller. The other is to use FIFO, which can store 16 / 32 / … bytes of data. The depth of FIFO is determined according to the actual situation. The setting of FIFO refers to: taking the RX process FIFO mode as an example, the second UART controller receives debugging data from the serial port, and the DMA controller moves the debugging data to the DDR module. At this time, the debugging data received from the serial port is stored in the RXFIFO of the second UART controller. When the data in the RXFIFO reaches a threshold, the second UART controller will send an interrupt to the Core. The Core will check the specific interrupt type and check that it is a receive data available interrupt type to notify the Core to read the data in the RXFIFO. The threshold described above needs to be configured by the Core into the register of the second UART controller.

[0056] Interrupt enable setting: during data transmission, the Core module needs to process interrupts, so it must set the interrupt enable of the corresponding type. If an interrupt occurs, the corresponding interrupt identifier (no other higher priority interrupt) will be displayed in a register. For example, receive data available interrupt, character timeout interrupt, send buffer register empty interrupt, etc. The interrupt enable of each type described above needs to be configured by the Core to the register in the second UART controller.

[0057] (2) Assign virtual serial port permissions to the Host:

[0058] First, the Core module configures the virtual serial port enable, that is, configures the virtual serial port enable register in the second UART controller to enable the virtual serial port. At the same time, configure the virtual serial port Host address, that is, configure the virtual serial port Host address register in the second UART controller, so that the external Host obtains the address of the first UART controller.

[0059] Second, pull the virtual serial port enable information and virtual serial port Host address information to the external Host, so that the external Host obtains the virtual serial port enable information and virtual serial port Host address information, thereby recognizing the permission to obtain the virtual serial port.

[0060] (3) Preparation of virtual serial port pending data:

[0061] First, determine whether it is local debugging. If it is local debugging, the Core module directly obtains the debugging data and writes it into the DDR module. If it is remote debugging, the Core module configures the GMAC module to obtain the debugging data returned by the remote Client and writes it into the DDR module.

[0062] (4) Configure the DMA controller so that it reads back the debug data from the DDR module and writes it to the second UART controller:

[0063] like Figure 3 As shown, the DMA controller needs to be initialized first, including resetting the values ​​of some registers, such as the read / write pointer register for DMA operations in the data transmission process, disabling the DMA interrupt enable register and the DMA enable register, etc.

[0064] Configure the DMA base address, which is the first address of the debug data to be sent in the DDR module;

[0065] Configure the DMA data length, which is the end address of the debug data to be sent in the DDR module. The data size for DMA transfer needs to be calculated manually.

[0066] Enable the DMA interrupt enable register and the DMA enable register, which means starting the DMA controller and making it work;

[0067] After all debug data is sent out from the virtual serial port, the DMA controller sends a TX DMA completion interrupt command to the Core module to end the current DMA transfer.

[0068] It should be noted that the process of the DMA controller writing the debug data in the DDR module to the second UART controller is a whole process. It involves the DMA controller retrieving the debug data back to the DMA controller, then writing the debug data to the second UART controller, and finally sending the debug data out from the virtual serial port.

[0069] In the TX process, the second UART controller acts as an asynchronous data transmission device, converting parallel data into serial data and sending it out through the serial port pin. The clock frequency for the parallel data is faster than the serial clock frequency. The DMA controller helps the second UART controller retrieve the large amounts of data to be sent from the serial port. If there is space within the second UART controller, the DMA controller fills it with the data, ensuring the second UART controller remains in a continuous serial transmission state without interruption.

[0070] The workflow for RX receiving data is as follows: Figure 4 As shown, the external host sends debug data to the first UART controller. The first UART controller transmits the debug data serially via its output pin, and the second UART controller receives the debug data serially via its input pin. The DMA controller first reads the debug data from the second UART controller and then writes the debug data to the DDR module. Specifically, the steps are as follows:

[0071] Steps (1) and (2) are consistent with the workflow of sending data via TX as described above.

[0072] (3) Configure the DMA controller so that it reads back the debug data from the second UART controller and writes it to the DDR module:

[0073] like Figure 5 As shown, the DMA controller needs to be initialized first, including resetting the values ​​of some registers, such as the read / write pointer register for DMA operations in the data receiving process, disabling the DMA interrupt enable register and the DMA enable register, etc.

[0074] Configure the DMA base address, which is the first address of the debug data to be received in the DDR module;

[0075] Configure the DMA data length, which is the end address of the debug data to be received in the DDR module. The data size for DMA transfer needs to be calculated manually.

[0076] Enable the DMA interrupt enable register and the DMA enable register, which means starting the DMA controller and making it work;

[0077] After all debug data is sent out from the virtual serial port, the DMA controller sends an RX DMA completion interrupt command to the Core module to end the current DMA transfer.

[0078] In the RX process, the second UART controller acts as an asynchronous data receiving device, converting serial data on the serial port pins into parallel data and receiving it. The DMA controller helps the second UART controller promptly and quickly send data to the DDR module. When the second UART controller has data, the DMA controller retrieves it, keeping the second UART controller in a serial port receiveable state. If the serial port sender's data is continuous, the second UART controller will continuously receive data.

[0079] (4) Subsequent processing of data in the DDR module:

[0080] First, it determines whether it is local debugging. If it is local debugging, the Core module reads back the debugging data from the DDR module and sends it to other modules of the BMC chip.

[0081] For remote debugging, the Core module is configured with the GMAC module, which reads back the debugging data from the DDR module and packages it to send to the external client.

[0082] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0083] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0084] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0085] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0086] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A BMC chip with a virtual serial port featuring DMA functionality, characterized in that, It includes a Core module, a DDR module, a GMAC module, and a virtual serial port, wherein the virtual serial port includes a first UART controller, a second UART controller, and a DMA controller; The first UART controller is connected to an external host. The output pin of the first UART controller is connected to the input pin of the second UART controller, and the output pin of the second UART controller is connected to the input pin of the first UART controller. The second UART controller is connected to the DMA controller, and the DMA controller is connected to the DDR module; The Core module is connected to the virtual serial port, the DDR module, and the GMAC module, respectively; the GMAC module is connected to the DDR module and the external Client.

2. The BMC chip with DMA function virtual serial port according to claim 1, characterized in that, The first UART controller is connected to the host via the first Bus module; The Core module is connected to the virtual serial port and the GMAC module respectively through the second Bus module; The DMA controller and GMAC module are respectively connected to the DDR module through the third Bus module.

3. The BMC chip with DMA function virtual serial port according to claim 1, characterized in that, The GMAC module is connected to the client via a LAN cable.

4. The BMC chip with DMA function virtual serial port according to claim 1, characterized in that, The first UART controller is used to serve the external Host terminal, and the second UART controller is used to serve the Core module.

5. A method for using a BMC chip with a virtual serial port featuring DMA functionality, characterized in that, The BMC chip with DMA-enabled virtual serial port as described in any one of claims 1-4 includes the following steps: Initialize the virtual serial port and assign virtual serial port permissions to the host. In the TX process, debug data is acquired and written to the DDR module; the DMA controller is configured so that it reads back the debug data from the DDR module and writes it to the second UART controller. In the RX process, the DMA controller is configured to receive debug data from the second UART controller and write it into the DDR module; the Core module sends the debug data from the DDR module.

6. The method of using the BMC chip with DMA function virtual serial port according to claim 5, characterized in that, The initialization of the virtual serial port includes setting the baud rate clock, frame format, FIFO, and interrupt enable.

7. The method of using the BMC chip with DMA function virtual serial port according to claim 5, characterized in that, During the TX process, the debug data is acquired and written to the DDR module, including the following steps: For local debugging, the Core module directly obtains the debugging data and writes it to the DDR module; For remote debugging, the Core module is configured with the GMAC module, which enables the GMAC module to obtain the debugging data returned by the client and write it to the DDR module.

8. The method of using the BMC chip with DMA function virtual serial port according to claim 5, characterized in that, During the RX process, send debug data from the DDR module, including the following steps: If it is for local debugging, the Core module reads back the debugging data from the DDR module and sends it; For remote debugging, the Core module is configured with the GMAC module, which reads back the debugging data from the DDR module and packages it to send to the external client.

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