A CHI bus memory for rapid functional verification of chip prototypes

Abstract

The present invention discloses a CHI bus memory for rapid functional verification of chip prototypes, comprising a link management module, a credit control module, a transaction processing module, a message cache module, and an SRAM module. The message cache module is respectively connected to the link management module, the credit control module, and the transaction processing module, the transaction processing module is connected to the SRAM module, and the link management module, the credit control module, and the message cache module are respectively connected to a CHI bus interface. The CHI bus memory for rapid functional verification of chip prototypes of the present invention can be used to replace real storage controllers of complex protocols such as DDR and HBM in high-performance multi-core processors or SoC chips, quickly build a chip rapid prototyping system to meet the rapid verification requirements of chip prototypes, improve verification resources and verification efficiency, and facilitate deployment.

Description

Technical Field

[0001] The present invention belongs to the technical field of rapid functional verification of chip prototypes in the technical field of computer technology, and in particular relates to a CHI bus memory for rapid functional verification of chip prototypes. Background Art

[0002] High-performance multi-core processors or SoCs typically include a DDR (Double Data Rate) memory controller, which connects to the actual memory DIMMs (Dual Inline Memory Modules) through a physical interface. The DDR initialization process is time-consuming and complex, requiring power-up and initial configuration, ZQ calibration, DQ calibration, and PHY link training. Only after initialization is complete can read and write memory access be performed. This initialization configuration involves over 20 steps, primarily configuring the DDR controller's memory model, memory capacity, timing parameters, and mode registers. This configuration process consumes significant simulation verification time.

[0003] During full-chip system-level verification, if the memory controller's functionality is not verified, there's no need to focus on its details. Otherwise, significant verification resources will be consumed and verification efficiency will be affected. To address this issue, a chip prototype must be quickly built for functional verification. Design flaws can be quickly identified through test stimulus loosely coupled with the memory controller. This allows the chip's memory controller to be directly replaced with a memory model using the CHI bus. The CHI bus is a fifth-generation bus specification defined by ARM, providing a scalable on-chip interconnect. Memory is a slave node (SN) on the CHI bus, accepting read and write requests from the home node (HN). The CHI protocol is an evolution of the ACE (AXI Coherence Extension) protocol. The ACE protocol is compatible with the AXI protocol and uses a master / slave signal level communication scheme. The ACE protocol is commonly used in mobile and embedded chips, supporting smaller CC coherence protocol systems and the Snoop broadcast bus scheme. With the increasing integration of coherence clusters in SoCs, AMBA5 introduced the CHI protocol. The CHI protocol utilizes a layered, packet-based communication protocol, encompassing the protocol, network, and link layers. It supports QoS-based flow control, a retry mechanism, the directory implementation of the CC consistency protocol, and the Snoop broadcast bus method. The AXI / ACE bus storage functional model is relatively simple to implement, but requires the design of a CHI-to-AXI / ACE protocol bridge, which requires additional design circuitry and increases resource overhead. Summary of the Invention

[0004] The technical problem to be solved by the present invention is as follows: For designs such as high-performance multi-core processors or complex SoCs (System on Chips) integrated with standard CHI bus memories, the present invention provides a CHI bus memory for rapid functional verification of chip prototypes. The memory can be used to replace the real memory controllers of complex protocols such as DDR and HBM in high-performance multi-core processors or SoC chips, and efficiently build a chip rapid prototyping system to meet the rapid verification requirements of chip prototypes.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A CHI bus memory for rapid functional verification of chip prototypes, comprising:

[0007] Link management module, used to manage the link status of the CHI bus;

[0008] Credit control module, used to manage the credit of each channel of CHI bus memory;

[0009] The transaction processing module includes a read transaction state machine and a write transaction state machine. The read transaction state machine is used to process CHI bus request messages, and the write transaction state machine is used to process CHI bus write request messages.

[0010] Message cache module, used to cache CHI messages to provide data support for the transaction processing module;

[0011] and an SRAM module for storing CHI message data;

[0012] The message buffer module is connected to the link management module, the credit control module and the transaction processing module respectively. The transaction processing module is connected to the SRAM module. The link management module, the credit control module and the message buffer module are connected to the CHI bus interface respectively.

[0013] Optionally, the link management module manages the link status of the CHI bus, including: pulling up the link activation response signal after receiving the link activation request from the HN master node of the CHI bus, so that the link enters a normal working state; pulling down the link activation response signal after receiving the link low request signal from the HN master node, so that the link enters an idle state IDLE.

[0014] Optionally, the message buffer module includes four first-in-first-out buffers, namely, a receive request message buffer RX_ReqFlitFifo, a receive data message buffer RX_DatFlitFifo, a transmit data message buffer TX_DatFlitFifo, and a transmit response message buffer TX_RspFlitFifo. When the link is in working state and the credit is valid, the CHI bus memory receives the CHI request message and the CHI receive data message from the CHI bus, and inputs them into the receive request message buffer RX_ReqFlitFifo or the receive data message buffer RX_DatFlitFifo in the message buffer module respectively; the CHI response message and CHI data message generated by the transaction processing module are received by the CHI bus memory. The transmit data message buffer TX_DatFlitFifo or the transmit response message buffer TX_RspFlitFifo are respectively input into the message buffer module. When the transmit data message buffer TX_DatFlitFifo and the transmit response message buffer TX_RspFlitFifo are not empty, the CHI message buffer module determines that the link is in normal working condition. At this time, if the credit of the transmit response channel TX_RspLink and the transmit data channel TX_DatLink calculated by the credit control module is greater than 0, the CHI message buffer module sends the messages cached in the transmit data message buffer TX_DatFlitFifo and the transmit response message buffer TX_RspFlitFifo to the CHI bus.

[0015] Optionally, the channels of the CHI bus memory managed by the credit control module include four channels, namely, a request receiving channel RX_ReqLink, a data receiving channel RX_DatLink, a response sending channel TX_RspLink, and a data sending channel TX_DatLink. The credit control module also includes credit counters corresponding to the four channels to manage the credit of each channel; the initialization values of the credit counters of the response sending channel TX_RspLink and the data sending channel TX_DatLink are both 0. When the credit control signal TX_RspLink_Lcrd of the CHI bus is sampled, the credit counter of the response sending channel TX_RspLink is increased by 1. When the response sending message cache TX_RspFlitFifo of the CHI message cache module sends a message to the CHI bus, the credit counter of the response sending channel TX_RspLink is reduced by 1. When the credit control signal TX_DatLink_Lcrd of the CHI bus is sampled, the credit counter of the data sending channel TX_DatLink is increased by 1. When the transmit data message buffer TX_DatFlitFifo of the CHI message buffer module sends a message to the CHI bus, the credit counter of the transmit data channel TX_DatLink is reduced by 1; the initialization values of the credit counters of the receive request channel RX_ReqLink and the receive data channel RX_DatLink are both equal to the buffer depth of the receive request message buffer RX_ReqFlitFifo in the CHI message buffer module. When the link enters normal working state after the link activation response, the credit control module sends a credit control signal RX_ReqLink_Lcrd to the CHI bus, and the credit counter of the receive request channel RX_ReqLink is reduced by 1; after the link is working normally, when the credit control module receives the request message processing completion signal from the transaction processing module, the credit counter of the receive request channel RX_ReqLink is increased by 1, and the credit control module sends a credit control signal RX_ReqLink_Lcrd to the CHI bus; when the link enters normal working state after the link activation data is sent, the credit control module sends a credit control signal RX_ DatLink _Lcrd, the credit counter of the receiving data channel RX_DatLink is reduced by 1; when the link is working normally, when the credit control module receives the request message processing completion signal from the transaction processing module, the credit counter of the receiving data channel RX_DatLink is increased by 1, and the credit control module sends a credit control signal RX_DatLink _Lcrd to the CHI bus.

[0016] Optionally, the read transaction state machine of the transaction processing module has four states: RD_IDLE state, RD_SRAM state, CREATE_TXDATFLIT state and OUTPUT_TXDATFIFO state, where the RD_IDLE state is an idle state, the RD_SRAM state is an SRAM read state, the CREATE_TXDATFLIT state is a CHI send data message state, and the OUTPUT_TXDATFIFO state is a CHI send data message state input into the send data message cache TX_DatFlitFifo in the CHI message cache module.

[0017] Optionally, the state control process of the read transaction state machine includes: the read transaction state machine defaults to the RD_IDLE state; in the RD_IDLE state, if the transaction processing module detects that the receive request message cache RX_ReqFlitFifo in the CHI message cache module is not empty, the receive request message cache RX_ReqFlitFifo is read, the read message is decoded as a read operation, and the state is transferred to the RD_SRAM state; in the RD_SRAM state, the relevant fields of the read request message are parsed and recorded, the read counter is assigned to zero, the initial address of the read command and the read data byte length are recorded, the read command and read address are sent to the SRAM module, and the state is transferred to the CREATE_TXDATFLIT state; in the CREATE_TXDATFLIT state, a CHI send data message is generated, and then the state is transferred to the OUTPUT_TXDATFIFO state; in the OUTPUT_TXDATFIFO state, the CHI The transmit data message is input into the transmit data message buffer TX_DatFlitFifo in the CHI message buffer module; then the count value of the read counter is accumulated to the byte length of the read SRAM data. If the read counter is equal to the read data byte length recorded in the RD_SRAM status, the read transaction is determined to be complete and the state is transferred to the RD_IDLE state; otherwise, the state is transferred to the CREATE_TXDATFLIT state.

[0018] Optionally, the write transaction state machine of the transaction processing module has four states: WR_IDLE state, CREATE_TXRESPFLIT state, WAIT_RXDATA state, and WAIT_SRAM state, where the WR_IDLE state is an idle state, the CREATE_TXRESPFLIT state is to generate a send response message, the WAIT_RXDATA state is to wait for the receive data message cache RX_DatFlitFifo of the message cache module to be not empty, and the WAIT_SRAM state is the state of inputting SRAM write control signal, write address, and write data.

[0019] Optionally, the state control process of the write transaction state machine includes: the write transaction state machine is in the WR_IDLE state by default; in the WR_IDLE state, if the transaction processing module detects that the receive request message cache RX_ReqFlitFifo in the CHI message cache module is not empty, it reads the receive request message cache RX_ReqFlitFifo, decodes the message as a write operation, and enters the CREATE_TXRESPFLIT state; in the CREATE_TXRESPFLIT state, records the relevant fields of the write request message, fills in the fields of the send response message, generates a send response message, outputs it to the send response message cache TX_RspFlitFifo, records the address of the write request message and the byte length of the write data, initializes the count value of the write counter to 0, and enters the WAIT_RXDATA state; in the WAIT_RXDATA state, waits for the receive data message cache RX_ReqFlitFifo of the CHI message cache module to be received. _DatFlitFifo is not empty, read the receive data message cache RX_DatFlitFifo, parse the corresponding data according to the read receive data message, obtain the write SRAM data, and return a receive data transaction completion to the credit control module, and enter the WAIT_SRAM state; in the WAIT_SRAM state, output the write control signal, write address, and write data of the SRAM module. The write address is equal to the address of the write request message recorded in the CREATE_TXRESPFLIT state, and the write data is equal to the write SRAM data obtained in the WAIT_RXDATA state. The count value of the write counter is accumulated plus the byte length of the output data in the SRAM module. If the write counter is equal to the write data byte length recorded in the CREATE_TXRESPFLIT state, the write transaction is completed, and the request transaction completion signal is sent to the credit control module, and enter the WR_IDLE state. Otherwise, enter the WAIT_RXDATA state.

[0020] In addition, the present invention also provides a chip prototype rapid function verification system, including a verification device and a verified chip prototype with a storage module, wherein the storage module is the CHI bus memory for the chip prototype rapid function verification.

[0021] Optionally, the verified chip prototype with the storage module is written into the FPGA chip.

[0022] Compared with the prior art, the present invention mainly has the following advantages:

[0023] 1. The CHI bus memory for rapid functional verification of chip prototypes of the present invention includes a link management module, a credit control module, a transaction processing module, a message cache module and an SRAM module. The message cache module is respectively connected to the link management module, the credit control module and the transaction processing module, the transaction processing module is connected to the SRAM module, and the link management module, the credit control module and the message cache module are respectively connected to the CHI bus interface. The CHI bus memory for rapid functional verification of chip prototypes of the present invention can be used to replace the real storage controller of complex protocols such as DDR and HBM in high-performance multi-core processors or SoC chips, quickly build a chip rapid prototyping system to meet the rapid verification requirements of chip prototypes, improve verification resources and verification efficiency, and facilitate deployment.

[0024] 2. Compared to the memory function model based on the CHI-to-AXI / ACE protocol bridge, the CHI bus memory of this invention for rapid chip prototype functional verification optimizes circuit design resources, simplifies circuit structure, and improves verification resources and efficiency. Furthermore, in the full-chip verification process, excluding the testing of the DDR controller function, it facilitates verification of all chip functions, making it easier to deploy in simulators and FPGA prototype systems. It is also applicable to the design of SRAM memory using the CHI bus in SoC chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of the structure of the CHI bus memory in an embodiment of the present invention.

[0026] Figure 2 Schematic diagram of state switching of a read transaction state machine in an embodiment of the present invention.

[0027] Figure 3 Schematic diagram of state switching of a write transaction state machine in an embodiment of the present invention.

[0028] Legend: 1. Link management module; 2. Credit control module; 3. Transaction processing module; 4. Message cache module; 5. SRAM module. DETAILED DESCRIPTION

[0029] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, certain technical features well known in the art are not described to avoid confusion with the present invention.

[0030] like Figure 1 As shown, the CHI bus memory used for rapid functional verification of chip prototypes in this embodiment includes:

[0031] Link management module 1, used to manage the link status of the CHI bus;

[0032] Credit control module 2, used to manage the credit of each channel of the CHI bus memory;

[0033] Transaction processing module 3, including a read transaction state machine and a write transaction state machine, the read transaction state machine is used to process CHI bus request messages, and the write transaction state machine is used to process CHI bus write request messages;

[0034] Message cache module 4, used to cache CHI messages to provide data support for transaction processing module 3;

[0035] and an SRAM module 5 for storing CHI message data;

[0036] The message cache module 4 is connected to the link management module 1, the credit control module 2, and the transaction processing module 3 respectively. The transaction processing module 3 is connected to the SRAM module 5. The link management module 1, the credit control module 2, and the message cache module 4 are respectively connected to the CHI bus interface.

[0037] The link management module 1 is used to complete the link management of the CHI bus and ensure that the CHI bus is in a reasonable working state. In this embodiment, the link management module 1 manages the link state of the CHI bus by: pulling up the link activation response signal after receiving a link activation request from the HN master node of the CHI bus, so that the link enters a normal working state; pulling down the link activation response signal after receiving a link low request signal from the HN master node, so that the link enters an idle state IDLE.

[0038] In this embodiment, the message buffer module 4 includes four first-in-first-out buffers, namely, a receive request message buffer RX_ReqFlitFifo, a receive data message buffer RX_DatFlitFifo, a transmit data message buffer TX_DatFlitFifo, and a transmit response message buffer TX_RspFlitFifo. When the link is in working state and the credit is valid, the CHI bus memory receives the CHI request message and the CHI receive data message from the CHI bus and inputs them into the receive request message buffer RX_ReqFlitFifo or the receive data message buffer RX_DatFlitFifo in the message buffer module 4 respectively; the CHI response message and CHI data message generated by the transaction processing module 3 are received by the CHI bus memory. The send data message buffer TX_DatFlitFifo or the send response message buffer TX_RspFlitFifo are respectively input into the message buffer module 4. When the send data message buffer TX_DatFlitFifo and the send response message buffer TX_RspFlitFifo are not empty, the CHI message buffer module 4 determines that the link is in normal working state. At this time, if the credit of the send response channel TX_RspLink and the send data channel TX_DatLink calculated by the credit control module 2 is greater than 0, the CHI message buffer module 4 sends the messages cached in the send data message buffer TX_DatFlitFifo and the send response message buffer TX_RspFlitFifo to the CHI bus.

[0039] like Figure 1 As shown, the channels of the CHI bus memory managed by the credit control module 2 in this embodiment include four channels, namely, a request receiving channel RX_ReqLink, a data receiving channel RX_DatLink, a response sending channel TX_RspLink, and a data sending channel TX_DatLink. Each channel has an independent credit control signal Lcrd. The credit value is equal to the number of buffered messages that can be sent by the sending channel and is determined by the message cache depth of the receiving channel. The credit control of the receiving channel is implemented through the credit control signal Lcrd, and a pulse signal is used to send the other party. A CHI message consists of one or more micropackets (flits). For example, a request message and a response message are implemented by a micropacket, and a data message is implemented by one or two micropackets. The data message has a length field segment and can carry data ranging from 1 byte to 16 bytes. One micropacket carries a maximum of 256 bits of data, and two micropackets carry a maximum of 512 bits of data. The width of the message cache module 4 is the width of one micropacket. The credit representation value is the number of micropackets that can buffer the message, that is, when the number of micropackets in the message is 1 or 2, the credit control module 2 can send one or two credit control pulse signals Lcrd.

[0040] In this embodiment, the credit control module 2 further includes credit counters corresponding to four channels to manage the credit of each channel; the initialization values of the credit counters of the sending response channel TX_RspLink and the sending data channel TX_DatLink are both 0. When the credit control signal TX_RspLink_Lcrd of the CHI bus is sampled, the credit counter of the sending response channel TX_RspLink is increased by 1. When the sending response message buffer TX_RspFlitFifo of the CHI message buffer module 4 sends a message to the CHI bus, the credit counter of the sending response channel TX_RspLink is reduced by 1. When the credit control signal TX_DatLink_Lcrd of the CHI bus is sampled, the credit counter of the sending data channel TX_DatLink is increased by 1. When the sending data message buffer TX_DatFlitFifo of the CHI message buffer module 4 sends a message to the CHI bus, the sending data is decremented. The credit counter of the channel TX_DatLink is reduced by 1; the initialization values of the credit counters of the receive request channel RX_ReqLink and the receive data channel RX_DatLink are both equal to the buffer depth of the receive request message buffer RX_ReqFlitFifo in the CHI message buffer module 4. When the link enters the normal working state after the activation response, the credit control module 2 sends a credit control signal RX_ReqLink_Lcrd to the CHI bus, and the credit counter of the receive request channel RX_ReqLink is reduced by 1; after the link is working normally, when the credit control module 2 receives the request message processing completion signal sent by the transaction processing module 3, the credit counter of the receive request channel RX_ReqLink is increased by 1, and the credit control module 2 sends a credit control signal RX_ReqLink_Lcrd to the CHI bus; when the link enters the normal working state after the activation data is sent, the credit control module 2 sends a credit control signal RX_ DatLink_Lcrd, the credit counter of the receiving data channel RX_DatLink is reduced by 1; when the link is working normally, when the credit control module 2 receives the request message processing completion signal from the transaction processing module 3, the credit counter of the receiving data channel RX_DatLink is increased by 1, and the credit control module 2 sends a credit control signal RX_DatLink_Lcrd to the CHI bus.

[0041] The transaction processing module 3 includes a read transaction state machine and a write transaction state machine. When the receive request message buffer RX_ReqFlitFifo in the CHI message cache module 4 is not empty, the transaction processing module 3 reads RX_ReqFlitFifo and decodes the read request message to obtain a read or write operation command to start the read or write transaction state machine.

[0042] The read transaction state machine is used to process CHI bus request messages, parse and record read commands and addresses, send read signals and read address buses to SRAM, obtain read data from SRAM, generate CHI send data messages and output them to TX_DatFlitFifo in CHI message buffer module 4, request transaction completion, and send transaction completion signal to notify credit control module 2. Figure 2 In this embodiment, the read transaction state machine of the transaction processing module 3 has four states: RD_IDLE state, RD_SRAM state, CREATE_TXDATFLIT state, and OUTPUT_TXDATFIFO state. The RD_IDLE state is the idle state, the RD_SRAM state is the SRAM read state, the CREATE_TXDATFLIT state is the CHI transmit data message state, and the OUTPUT_TXDATFIFO state is the CHI transmit data message input into the transmit data message buffer TX_DatFlitFifo in the CHI message buffer module 4. Figure 2 As shown, the state control process of the read transaction state machine includes:

[0043] The read transaction state machine defaults to the RD_IDLE state;

[0044] In the RD_IDLE state, if the transaction processing module 3 detects that the receive request message buffer RX_ReqFlitFifo in the CHI message buffer module 4 is not empty, it reads the receive request message buffer RX_ReqFlitFifo, decodes the read message as a read operation, and enters the RD_SRAM state;

[0045] In the RD_SRAM state, the relevant fields of the read request message are parsed and recorded, the read counter is set to zero, the initial address of the read command and the length of the read data byte are recorded, the read command and read address are sent to SRAM module 5, and the state is transferred to CREATE_TXDATFLIT;

[0046] In the CREATE_TXDATFLIT state, generate CHI to send data message, and then enter the OUTPUT_TXDATFIFO state;

[0047] In the OUTPUT_TXDATFIFO state, the CHI transmit data message is input into the transmit data message buffer TX_DatFlitFifo in the CHI message buffer module 4; then the count value of the read counter is accumulated by the byte length of the read SRAM data. If the read counter is equal to the read data byte length recorded in the RD_SRAM state, the read transaction is determined to be completed and the state is transferred to the RD_IDLE state; otherwise, the state is transferred to the CREATE_TXDATFLIT state.

[0048] In this implementation, the CREATE_TXDATFLIT state generates the CHI transmit data message by filling the read data output by the SRAM into the data field of the CHI transmit data message, and filling the relevant field of the request message recorded in the RD_SRAM state into the corresponding field. The 8-bit data generates a 1-bit CRC check bit, which is filled into the data check field of the transmit data message. After filling, the CHI transmit data message is obtained and can be output to the transmit data message cache TX_DatFlitFifo in the CHI message cache module 4.

[0049] The write transaction state machine is used to process CHI bus write request messages, parse and record write commands and addresses, generate CHI response messages, and output them to the receive data message buffer RX_DatFlitFifo in the message buffer module 4; wait until the receive data message buffer RX_DatFlitFifo in the message buffer module 4 is not empty, read the receive data message in the receive data message buffer RX_DatFlitFifo, parse the write data, input the SRAM write signal, write address bus, and write data bus; after the write transaction is processed, send a transaction completion signal to the credit control module 2. Figure 3 The write transaction state machine of the transaction processing module 3 has four states: WR_IDLE state, CREATE_TXRESPFLIT state, WAIT_RXDATA state, and WAIT_SRAM state. The WR_IDLE state is the idle state, the CREATE_TXRESPFLIT state is to generate a send response message, the WAIT_RXDATA state is to wait for the receive data message cache RX_DatFlitFifo of the message cache module 4 to be not empty, and the WAIT_SRAM state is the state of inputting the SRAM write control signal, write address, and write data.

[0050] like Figure 2 As shown, the state control process of the write transaction state machine includes:

[0051] The write transaction state machine is in the WR_IDLE state by default;

[0052] In the WR_IDLE state, if the transaction processing module 3 detects that the receive request message buffer RX_ReqFlitFifo in the CHI message buffer module 4 is not empty, it reads the receive request message buffer RX_ReqFlitFifo, decodes the message as a write operation, and enters the CREATE_TXRESPFLIT state;

[0053] In the CREATE_TXRESPFLIT state, the relevant fields of the write request message are recorded, the fields of the send response message are filled, the send response message is generated, and the send response message is output to the send response message buffer TX_RspFlitFifo. The address of the write request message and the byte length of the write data are recorded, the count value of the write counter is initialized to 0, and the state is transferred to the WAIT_RXDATA state;

[0054] In the WAIT_RXDATA state, the module waits for the receive data message cache RX_DatFlitFifo of the CHI message cache module 4 to be not empty, reads the receive data message cache RX_DatFlitFifo, parses the corresponding data according to the read receive data message, obtains the write SRAM data, and returns a receive data transaction completion signal to the credit control module 2, and then enters the WAIT_SRAM state;

[0055] In the WAIT_SRAM state, the write control signal, write address, and write data of the SRAM module 5 are output. The write address is equal to the address of the write request message recorded in the CREATE_TXRESPFLIT state. The write data is equal to the write SRAM data obtained in the WAIT_RXDATA state. The count value of the write counter is added to the byte length of the output data in the SRAM module 5. If the write counter is equal to the write data byte length recorded in the CREATE_TXRESPFLIT state, the write transaction is completed, and a request transaction completion signal is returned to the credit control module 2, and the state is transferred to the WR_IDLE state. Otherwise, the state is transferred to the WAIT_RXDATA state.

[0056] In summary, the CHI bus memory for rapid functional verification of chip prototypes in this embodiment includes a link management module 1, a credit control module 2, a transaction processing module 3, a message cache module 4 and an SRAM module 5. The link management module 1 is used to process the CHI bus link status; the credit control module 2 maintains the credit of the four channels of the CHI bus, namely, the credit management of the request receiving channel RX_ReqLink, the data receiving channel RX_DatLink, the response sending channel TX_RspLink, and the data sending channel TX_DatLink; the transaction processing module 3 includes a read and write transaction state machine, which is used to process CHI bus read and write messages, parse commands, addresses, and data, exchange data with SRAM, generate data messages that comply with the CHI protocol, output them to the message cache module 4, and finally send them to the CHI bus; the message cache module 4 is used to cache CHI bus messages and provide data support for the transaction processing module 3. For designs such as high-performance multi-core processors or SoCs (System on Chips) that integrate standard CHI bus memory, the CHI bus memory for rapid functional verification of chip prototypes in this embodiment can implement standard CHI bus memory, be used to build chip rapid prototyping systems, meet rapid verification requirements, and replace real memory controllers of complex protocols such as DDR and HBM in high-performance multi-core processors or SoC chips. It can simulate and accelerate non-memory controller-related tests and is suitable for simulation acceleration platforms and FPGA platforms.

[0057] In addition, this embodiment also provides a chip prototype rapid functional verification system, including a verification device and a verified chip prototype with a storage module. The storage module is the CHI bus memory used for rapid chip prototype functional verification described above. As an optional implementation, the verified chip prototype with the storage module in this embodiment is written into an FPGA chip. Alternatively, it can be written into other types of programmable chips to achieve rapid functional verification of the chip prototype.

[0058] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A CHI bus memory for rapid functional verification of chip prototypes, characterized in that: include: A link management module (1) is used to manage the link status of the CHI bus; A credit control module (2) for managing the credit of each channel of the CHI bus memory; A transaction processing module (3) includes a read transaction state machine and a write transaction state machine, wherein the read transaction state machine is used to process CHI bus request messages, and the write transaction state machine is used to process CHI bus write request messages; A message buffer module (4) is used to buffer CHI messages to provide data support for the transaction processing module (3); and an SRAM module (5) for storing CHI message data; The message buffer module (4) is respectively connected to the link management module (1), the credit control module (2), and the transaction processing module (3); the transaction processing module (3) is connected to the SRAM module (5); the link management module (1), the credit control module (2), and the message buffer module (4) are respectively connected to the CHI bus interface; The message buffer module (4) includes a receive request message buffer RX_ReqFlitFifo, a receive data message buffer RX_DatFlitFifo, a transmit data message buffer TX_DatFlitFifo, and a transmit response message buffer TX_RspFlitFifo, a total of four first-in-first-out buffers. When the link is in a working state and the credit is valid, the CHI bus memory receives a CHI request message and a CHI receive data message from the CHI bus and inputs them into the receive request message buffer RX_ReqFlitFifo or the receive data message buffer RX_DatFlitFifo in the message buffer module (4) respectively; the CHI response message and the CHI data message generated by the transaction processing module (3) are respectively input into To the send data message buffer TX_DatFlitFifo or the send response message buffer TX_RspFlitFifo in the message buffer module (4), when the send data message buffer TX_DatFlitFifo and the send response message buffer TX_RspFlitFifo are not empty, the CHI message buffer module (4) determines that the link is in a normal working state. At this time, if the send response channel TX_RspLink and the send data channel TX_DatLink credit calculated by the credit control module (2) are greater than 0, the CHI message buffer module (4) sends the messages buffered in the send data message buffer TX_DatFlitFifo and the send response message buffer TX_RspFlitFifo to the CHI bus.

2. The CHI bus memory for rapid functional verification of chip prototypes according to claim 1, characterized in that: The link management module (1) manages the link state of the CHI bus by: pulling up the link activation response signal after receiving the link activation request from the HN master node of the CHI bus, so that the link enters a normal working state; and pulling down the link activation response signal after receiving the link pull-down request signal from the HN master node, so that the link enters an idle state IDLE.

3. The CHI bus memory for rapid functional verification of chip prototypes according to claim 2, characterized in that: The channels of the CHI bus memory managed by the credit control module (2) include a receiving request channel RX_ReqLink, a receiving data channel RX_DatLink, a sending response channel TX_RspLink and a sending data channel TX_DatLink, a total of four channels. The credit control module (2) also includes credit counters corresponding to the four channels to manage the credit of each channel; the initialization values of the credit counters of the sending response channel TX_RspLink and the sending data channel TX_DatLink are both 0, when the credit control signal TX_RspLink_Lcrd of the CHI bus is sampled, the credit counter of the sending response channel TX_RspLink is increased by 1, when the sending response message buffer TX_RspFlitFifo of the CHI message buffer module (4) sends a message to the CHI bus, the credit counter of the sending response channel TX_RspLink is reduced by 1; when the credit control signal TX_DatLink_Lcrd of the CHI bus is sampled, the credit counter of the sending data channel TX_DatLink is increased by 1, when the CHI message buffer module (4) sends a message to the CHI bus, the credit counter of the sending response channel TX_RspLink is reduced by 1; when the credit control signal TX_DatLink_Lcrd of the CHI bus is sampled, the credit counter of the sending data channel TX_DatLink is increased by 1, when the CHI message buffer module (4) sends a message to the CHI bus When the transmit data message buffer TX_DatFlitFifo of the storage module (4) sends a message to the CHI bus, the credit counter of the transmit data channel TX_DatLink is reduced by 1; the initialization values of the credit counters of the receive request channel RX_ReqLink and the receive data channel RX_DatLink are both equal to the buffer depth of the receive request message buffer RX_ReqFlitFifo in the CHI message buffer module (4); when the link enters the normal working state after the link activation response, the credit control module (2) sends a credit control signal RX_ReqLink_Lcrd to the CHI bus, and the credit counter of the receive request channel RX_ReqLink is reduced by 1; when the link is working normally, when the credit control module (2) receives the request message processing completion signal sent by the transaction processing module (3), the credit counter of the receive request channel RX_ReqLink is increased by 1, and the credit control module (2) sends a credit control signal RX_ReqLink_Lcrd to the CHI bus; when the link enters the normal working state after the link activation data is sent, the credit control module (2) sends a credit control signal RX_ DatLink_Lcrd, the credit counter of the receiving data channel RX_ DatLink is reduced by 1; when the link is working normally, when the credit control module (2) receives the request message processing completion signal sent by the transaction processing module (3), the credit counter of the receiving data channel RX_ DatLink is increased by 1, and the credit control module (2) sends a credit control signal RX_ DatLink_Lcrd to the CHI bus.

4. The CHI bus memory for rapid functional verification of chip prototypes according to claim 3, characterized in that: The read transaction state machine of the transaction processing module (3) has four states: RD_IDLE state, RD_SRAM state, CREATE_TXDATFLIT state and OUTPUT_TXDATFIFO state, wherein the RD_IDLE state is an idle state, the RD_SRAM state is an SRAM read state, the CREATE_TXDATFLIT state is a CHI transmit data message state, and the OUTPUT_TXDATFIFO state is a CHI transmit data message state input into the transmit data message cache TX_DatFlitFifo in the CHI message cache module (4).

5. The CHI bus memory for rapid functional verification of chip prototypes according to claim 4, characterized in that: The state control process of the read transaction state machine includes: the read transaction state machine defaults to the RD_IDLE state; in the RD_IDLE state, if the transaction processing module (3) detects that the receive request message cache RX_ReqFlitFifo in the CHI message cache module (4) is not empty, the receive request message cache RX_ReqFlitFifo is read, the read message is decoded as a read operation, and the state is transferred to the RD_SRAM state; in the RD_SRAM state, the relevant fields of the read request message are parsed and recorded, the read counter is assigned to zero, the initial address of the read command and the length of the read data byte are recorded, the read command and the read address are sent to the SRAM module (5), and the state is transferred to the CREATE_TXDATFLIT state; in the CREATE_TXDATFLIT state, a CHI send data message is generated, and then the state is transferred to the OUTPUT_TXDATFIFO state; in the OUTPUT_TXDATFIFO state, the CHI is sent The transmit data message is input into the transmit data message buffer TX_DatFlitFifo in the CHI message buffer module (4); then the count value of the read counter is added to the byte length of the read SRAM data. If the read counter is equal to the read data byte length recorded in the RD_SRAM state, the read transaction is determined to be completed and the state is transferred to the RD_IDLE state; otherwise, the state is transferred to the CREATE_TXDATFLIT state.

6. The CHI bus memory for rapid functional verification of chip prototypes according to claim 5, characterized in that: The write transaction state machine of the transaction processing module (3) has four states: WR_IDLE state, CREATE_TXRESPFLIT state, WAIT_RXDATA state, and WAIT_SRAM state, wherein the WR_IDLE state is an idle state, the CREATE_TXRESPFLIT state is to generate a send response message, the WAIT_RXDATA state is to wait for the receive data message cache RX_DatFlitFifo of the message cache module (4) to be not empty, and the WAIT_SRAM state is to input the SRAM write control signal, write address, and write data.

7. The CHI bus memory for rapid functional verification of chip prototypes according to claim 6, characterized in that: The state control process of the write transaction state machine includes: the write transaction state machine is in the WR_IDLE state by default; in the WR_IDLE state, if the transaction processing module (3) detects that the receive request message cache RX_ReqFlitFifo in the CHI message cache module (4) is not empty, the receive request message cache RX_ReqFlitFifo is read, and the message is decoded as a write operation, Enter the CREATE_TXRESPFLIT state; in the CREATE_TXRESPFLIT state, record the relevant fields of the write request message, fill in the fields of the send response message, generate a send response message, output it to the send response message buffer TX_RspFlitFifo, record the address of the write request message and the byte length of the write data, initialize the count value of the write counter to 0, and enter the WAIT_RXDATA state; in the WAIT_RXDATA state, wait for the receive data message buffer RX_DatFlitFifo of the CHI message buffer module (4) to be not empty, read the receive data message buffer RX_DatFlitFifo, parse the corresponding data according to the read receive data message, obtain the write SRAM data, and return to the credit control module (2) at the same time. A receive data transaction is completed and enter the WAIT_SRAM state; In the WAIT_SRAM state, the write control signal, write address, and write data of the SRAM module (5) are output. The write address is equal to the address of the write request message recorded in the CREATE_TXRESPFLIT state. The write data is equal to the write SRAM data obtained in the WAIT_RXDATA state. The count value of the write counter is added to the byte length of the output data in the SRAM module (5). If the write counter is equal to the byte length of the write data recorded in the CREATE_TXRESPFLIT state, the write transaction is completed, and the request transaction completion signal is sent to the credit control module (2). The state is transferred to the WR_IDLE state. Otherwise, the state is transferred to the WAIT_RXDATA state.

8. A chip prototype rapid functional verification system, comprising a verification device and a verified chip prototype with a storage module, characterized in that: The storage module is a CHI bus memory for rapid functional verification of chip prototypes as described in any one of claims 1 to 7.

9. The chip prototype rapid function verification system according to claim 8, characterized in that: The verified chip prototype with the storage module is written into the FPGA chip.

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