Multi-FPGA Global Synchronization Trigger Method and System for FPGA Simulation and Verification Platform

Abstract

The present invention discloses a multi-FPGA global synchronization triggering method and system for an FPGA simulation and verification platform. The present invention includes that in each clock cycle, if any FPGA meets the triggering condition, the master node directly or indirectly obtains the timestamp of the triggering moment and the sampling address at the triggering moment, and calculates the depth of continuous sampling after the master FPGA node is triggered and the timestamp of sampling stop; sets the trigger status register to "1", and saves the trigger status register, the timestamp of the triggering moment and the sampling address at the triggering moment to the register module for the host computer software to read. At the same time, the master node encapsulates the timestamp of sampling stop into a message and broadcasts it to all slave nodes to control the slave nodes to stop sampling. The present invention can realize the synchronous triggering of multiple conditions of distributed FPGAs, and provide efficient error location and diagnosis capabilities for global debugging and diagnosis in the parallel simulation process of multiple FPGA chips.

Description

Technical Field

[0001] The present invention relates to the debugging and diagnosis technology of an FPGA simulation verification platform, and particularly relates to a multi-FPGA global synchronization triggering method and system for an FPGA simulation verification platform. Background Art

[0002] During the process of using an FPGA to debug and diagnose a chip in an FPGA simulation verification platform, it is generally necessary to set trigger conditions for the signals in the chip to observe the states of each signal under this condition after triggering, so as to achieve the purpose of debugging. For example, Vivado Chipscope of Xilinx Company uses the above method for debugging, but it can only perform trigger debugging on the design in a single FPGA. It is difficult for a single FPGA to meet the debugging and diagnosis requirements of current high-end chips such as processor chips and accelerator chips, etc., which are ultra-large-scale chips. Therefore, it is necessary to divide the design onto multiple FPGAs for joint simulation. However, the trigger synchronization during the global debugging of multiple FPGAs has become an urgent problem to be solved. Summary of the Invention

[0003] The technical problem to be solved by the present invention: Aiming at the above problems of the prior art, a multi-FPGA global synchronization triggering method and system for an FPGA simulation verification platform are provided. The present invention can realize the synchronous triggering of multiple conditions of distributed FPGAs, and provide efficient error location and diagnosis capabilities for global debugging and diagnosis during the parallel simulation of chips with multiple FPGAs.

[0004] To solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0005] A multi-FPGA global synchronization triggering method for an FPGA simulation verification platform, comprising:

[0006] S1. In each clock cycle, each FPGA including the master node and slave nodes compares the inserted trigger probe signal value with the preset trigger condition in real time to determine whether the trigger condition is satisfied. If the master node satisfies the trigger condition, jump to step S3; if the slave node satisfies the trigger condition, jump to step S2;

[0007] S2. The triggered slave node obtains the trigger time timestamp trig_time_stamp and the trigger-time sampling address trig_addr at the trigger moment, encapsulates them into a message and sends it to the master node. The master node parses the trigger time timestamp rmt_trig_time_stamp and the trigger-time sampling address rmt_trig_addr in the message. The master node calculates the depth Tcnt of continuous sampling after triggering by the master FPGA node according to the local current time timestamp, the received remote trigger time timestamp rmt_trig_time_stamp, and the preset waveform ratio before and after triggering. m And the sampling stop timestamp stop_time_stamp, sets the trigger status register to "1", and saves the trigger status register, the remote trigger time timestamp rmt_trig_time_stamp, and the trigger-time sampling address rmt_trig_addr to the register module for the host computer software to read. At the same time, the master node encapsulates the sampling stop timestamp stop_time_stamp into a message and broadcasts it to all slave nodes; Jump to step S3;

[0008] S3. The master node obtains the trigger time timestamp trig_time_stamp and the trigger-time sampling address trig_addr. The master node calculates the depth Tcnt of continuous sampling after triggering according to the local timestamp and the preset waveform ratio before and after triggering. m And the sampling stop timestamp stop_time_stamp, sets the trigger status register to "1", and saves the trigger status register, the trigger time timestamp trig_time_stamp, and the trigger-time sampling address trig_addr to the register module for the host computer software to read. At the same time, the master node encapsulates the sampling stop timestamp stop_time_stamp into a message and broadcasts it to all slave nodes; Jump to step S4;

[0009] S4. The slave node parses the sampling stop timestamp stop_time_stamp in the received message and stops sampling when the local timestamp is equal to the sampling stop timestamp stop_time_stamp.

[0010] Optionally, when each FPGA in step S1 performs real-time comparison between the inserted trigger probe signal value and the preset trigger condition to determine whether the trigger condition is met, the trigger counter trig_cnt of each FPGA is driven by the global synchronous clock signal gclk to ensure that the count values of the trigger counters trig_cnt of each FPGA are completely synchronized.

[0011] Optionally, the obtained trigger moment timestamp trig_time_stamp and the trigger moment sampling address trig_addr refer to using the current moment timestamp recorded according to the trigger moment of the trigger counter trig_cnt as the trigger moment timestamp trig_time_stamp, and using the address where the sampling data corresponding to the trigger moment is stored in the memory as the trigger moment sampling address trig_addr.

[0012] Optionally, in step S3, the master node calculates the depth Tcnt of continued sampling after triggering based on the local timestamp and the preset waveform ratio before and after triggering. m And the calculation function expression of the sampling stop timestamp stop_time_stamp is:

[0013] Tcnt m = Scnt * (1 - k)

[0014] Ts s = Ts m + Tcnt m = Ts m + Scnt * (1 - k)

[0015] In the above formula, Scnt is the preset sampling depth, k is the preset waveform ratio coefficient before and after triggering, Ts m is the current timestamp of the master node, and Ts s is the sampling stop timestamp stop_time_stamp.

[0016] Optionally, in step S2, the master node calculates the depth Tcnt of continued sampling after triggering of the master FPGA node based on the local current moment timestamp, the received remote trigger moment timestamp rmt_trig_time_stamp, and the preset waveform ratio before and after triggering. m And the function expression of the sampling stop timestamp stop_time_stamp is:

[0017] Tcnt m = Scnt * (1 - k) - (Ts m - Ts r )

[0018] Ts s = Ts m + Tcnt m = Ts m +(Scnt * (1 - k) - (Ts m - Ts r )) = Scnt * (1 - k) + Ts r

[0019] In the above formula, Tcntm It is the depth of continuous sampling after the main FPGA node is triggered, Ts s It is the sampling stop timestamp stop_time_stamp, Ts m The current timestamp of the main node, Tcnt m It is the depth of continuous sampling after the main FPGA node is triggered, Scnt is the preset sampling depth, k is the preset waveform ratio coefficient before and after triggering, Ts r It is the timestamp rmt_trig_time_stamp at the triggering moment of the remote slave node.

[0020] Optionally, before step S1, it further includes selecting an FPGA as the main node, writing the node number of the main node into the main node number register of the remaining FPGAs serving as slave nodes, and writing the node numbers of all slave nodes into the FPGA node list register of the main node.

[0021] Optionally, before step S1, it further includes configuring sampling parameters for the main node, connecting the probe signals participating in the triggering to the interface of the trigger detection module according to the triggering conditions set by the user, and configuring the register to define the signal format and triggering conditions of the triggering probe.

[0022] In addition, the present invention also provides a multi-FPGA global synchronous triggering system for an FPGA simulation verification platform, including a high-speed interconnection network and multiple FPGAs respectively connected to the high-speed interconnection network, and the FPGAs are programmed or configured to execute the multi-FPGA global synchronous triggering method of the FPGA simulation verification platform.

[0023] Optionally, the host computer is connected to multiple FPGAs through the high-speed interconnection network. The host computer reads the trigger status register of the main node in each FPGA through software to obtain the system trigger status. If the value of the trigger status register is "1", it reads the register module of the main node to obtain the trigger moment timestamp rmt_trig_time_stamp and the trigger moment sampling address rmt_trig_addr, and then restores and reconstructs the waveforms of the sampling results of all FPGA nodes according to the values of the trigger moment timestamp rmt_trig_time_stamp and the trigger moment sampling address rmt_trig_addr.

[0024] In addition, the present invention also provides a computer-readable storage medium, in which a computer program is stored, and the computer program is used to be programmed or configured by a microprocessor to execute the multi-FPGA global synchronous triggering method of the FPGA simulation verification platform.

[0025] Compared with the prior art, the present invention mainly has the following advantages: The present invention proposes an FPGA array global synchronization triggering technology, which can achieve distributed FPGA multi-condition synchronization triggering for global debugging and diagnosis during the parallel simulation process of multiple FPGA chips. The present invention supports real-time monitoring of trigger signals distributed in multiple FPGAs and complex condition triggering, synchronizes the first triggered signal to all FPGAs in the network, and enables all FPGAs to trigger at the same moment to provide efficient error location and diagnosis capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the basic process of the method according to the embodiment of the present invention.

[0027] Figure 2 It is a schematic diagram of the structure of the multi-FPGA global synchronization triggering network in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] As Figure 1 and Figure 2 shown, the multi-FPGA global synchronization triggering method of the FPGA simulation verification platform in this embodiment includes:

[0029] S1. In each clock cycle, each FPGA including the master node and the slave nodes compares the inserted trigger probe signal value with the preset trigger condition in real time to determine whether the trigger condition is met. If the master node meets the trigger condition, jump to step S3; if the slave node meets the trigger condition, jump to step S2;

[0030] S2. The triggered slave node obtains the trigger time timestamp trig_time_stamp and the trigger time sampling address trig_addr at the trigger moment and encapsulates them into a message and sends it to the master node. The master node parses the trigger time timestamp rmt_trig_time_stamp and the trigger time sampling address rmt_trig_addr in the message; the master node calculates the depth Tcnt of continuous sampling after the master FPGA node is triggered according to the local current time timestamp, the received remote trigger time timestamp rmt_trig_time_stamp and the preset waveform ratio before and after the trigger m and the sampling stop timestamp stop_time_stamp, sets the trigger status register to "1", and saves the trigger status register, the received remote trigger time timestamp rmt_trig_time_stamp and the trigger time sampling address rmt_trig_addr to the register module for the upper computer software to read. At the same time, the master node encapsulates the sampling stop timestamp stop_time_stamp into a message and broadcasts it to all slave nodes; jump to step S3;

[0031] S3. The master node obtains the trigger moment timestamp trig_time_stamp and the trigger moment sampling address trig_addr. The master node calculates the depth Tcnt of continued sampling after triggering according to the local timestamp and the preset waveform ratio before and after triggering. m And the sampling stop timestamp stop_time_stamp, sets the trigger status register to "1", and saves the trigger status register, the trigger moment timestamp trig_time_stamp and the trigger moment sampling address trig_addr to the register module for the host computer software to read. At the same time, the master node encapsulates the sampling stop timestamp stop_time_stamp into a message and broadcasts it to all slave nodes; jump to step S4.

[0032] S4. The slave node parses the sampling stop timestamp stop_time_stamp in the received message and stops sampling when the local timestamp is equal to the sampling stop timestamp stop_time_stamp.

[0033] See Figure 2 . In this embodiment, each FPGA (FPGA 1 to FPGA N) is connected to the high-speed interconnection network through the gth serial port to realize communication with other FPGA nodes. The high-speed interconnection network is composed of a network interface chip (NIO) and a switching chip (NRSwitch). In this embodiment, when each FPGA in step S1 performs real-time comparison between the inserted trigger probe signal value and the preset trigger condition to determine whether the trigger condition is met, the trigger counter trig_cnt of each FPGA is driven by the global synchronous clock signal gclk to ensure that the count values of the trigger counters trig_cnt of each FPGA are completely synchronized.

[0034] In this embodiment, obtaining the trigger moment timestamp trig_time_stamp and the trigger moment sampling address trig_addr means using the current moment timestamp recorded at the trigger moment of the trigger counter trig_cnt as the trigger moment timestamp trig_time_stamp, and using the address where the sampling data corresponding to the trigger moment is stored in the memory as the trigger moment sampling address trig_addr.

[0035] In this embodiment, in step S3, the master node calculates the depth Tcnt of continued sampling after triggering according to the local timestamp and the preset waveform ratio before and after triggering. m And the calculation function expression of the sampling stop timestamp stop_time_stamp is: <>

[0036] Tcnt m = Scnt * (1 - k)

[0037] Ts s =Ts m +Tcnt m =Ts m +Scnt*(1-k)

[0038] In the above formula, Scnt is the preset sampling depth, k is the preset waveform ratio coefficient before and after triggering, Ts m The current timestamp of the master node, Ts s The sampling stop timestamp is stop_time_stamp.

[0039] In this embodiment, in step S2, the master node calculates the depth Tcnt of the master FPGA node after the trigger according to the local current time stamp, the received remote trigger time stamp rmt_trig_time_stamp and the preset waveform ratio before and after the trigger. m And the function expression of the sampling stop timestamp stop_time_stamp is:

[0040] Tcnt m =Scnt*(1-k)-(Ts m -Ts r )

[0041] Ts s =Ts m +Tcnt m =Ts m +(Scnt*(1-k)-(Ts m -Ts r ))=Scnt*(1-k)+Ts r

[0042] In the above formula, Tcnt m The depth of continued sampling after the master FPGA node is triggered, Ts s The sampling stop timestamp stop_time_stamp, Ts m The current timestamp of the master node, Tcnt m The sampling depth after the main FPGA node is triggered, Scnt is the preset sampling depth, k is the preset waveform ratio coefficient before and after the trigger, Ts r The trigger time timestamp of the remote slave node is rmt_trig_time_stamp.

[0043] In this embodiment, before step S1, it also includes selecting an FPGA to be configured as a master node, writing the node number of the master node into the master node number registers of the remaining FPGAs serving as slave nodes, and writing the node numbers of all slave nodes into the FPGA node list register of the master node.

[0044] In this embodiment, before step S1, it also includes configuring sampling parameters for the master node, connecting the probe signals participating in the trigger to the interface of the trigger detection module according to the trigger conditions set by the user, and configuring registers to define the signal format and trigger conditions of the trigger probe.

[0045] In this embodiment, it is also necessary to set a trigger counter trig_cnt in the trigger module to provide a unified reference timestamp for the whole system to achieve synchronous triggering of all FPGA breakpoints. This counter is driven by the global synchronous clock signal gclk of the whole system to ensure that the count values of the trigger counters trig_cnt of all FPGAs are completely synchronized. The trigger counter trig_cnt and the sampling timestamp counter sampts_cnt required for sampling (used to timestamp the sampling signal) maintain exactly the same counting frequency. After the debugging system starts, in each clock cycle, the trigger detection modules of each FPGA in the system will compare the trigger signal value with the trigger condition in real time. If a certain FPGA meets the trigger condition at a certain moment, record the trigger moment timestamp trig_time_stamp and the sampling data corresponding to the trigger moment into the address trig_addr in the memory according to the count value of the trigger moment trig_cnt, and calculate the depth Tcnt (in clock cycles) of continuous sampling after the trigger according to the sampling and trigger parameter information set by the user. The specific parameters include the sampling depth Scnt (in clock cycles) and the waveform ratio coefficient k before and after the trigger (defining the proportion of the waveform length before the trigger moment in the finally exported waveform). The calculation function expression is:

[0046] Tcnt = Scnt * (1 - k).

[0047] If the triggered FPGA node is not the master node (slave node), the trigger module encapsulates the trigger moment timestamp trig_time_stamp and the trigger moment sampling address trig_addr into a gth message and sends it to the master node in the network through the gth serial port. If the triggered FPGA node is the master node, the trigger module only encapsulates the sampling stop timestamp stop_time_stamp into a gth message and queries the FPGA node list register to broadcast this message to all slave nodes of the system through the high-speed interconnection network. The master node calculates the depth Tcnt of continuous sampling after the trigger of the main FPGA node according to the trigger moment timestamp rmt_trig_time_stamp mand a sampling stop timestamp stop_time_stamp; set the trigger status register to "1", and save the trigger status register, the trigger moment timestamp rmt_trig_time_stamp, and the trigger moment sampling address rmt_trig_addr to the register module for the host computer software to read. At the same time, the master node encapsulates the sampling stop timestamp stop_time_stamp into a gth message and broadcasts it to all slave nodes, and stops sampling when the local timestamp is equal to the sampling stop timestamp stop_time_stamp; finally, after other FPGA slave nodes receive the gth message from the master FPGA node, the trigger module first parses the system sampling stop timestamp system_stop_time_stamp in the message, and when the local timestamp of the FPGA slave node is equal to the system sampling stop timestamp, it stops sampling. Therefore, the FPGA array global synchronization trigger method proposed in this embodiment can achieve distributed FPGA multi-condition synchronous triggering for global debugging and diagnosis during the parallel simulation process of multiple FPGA chips. The present invention supports real-time monitoring of trigger signals distributed in multiple FPGAs and complex condition triggering, synchronizes the first triggered signal to all FPGAs in the network, and enables all FPGAs to be triggered at the same moment to provide efficient error location and diagnosis capabilities.

[0048] In addition, this embodiment also provides a multi-FPGA global synchronization trigger system for an FPGA simulation verification platform, including a high-speed interconnect network and multiple FPGAs respectively connected to the high-speed interconnect network. The foregoing FPGAs are programmed or configured to execute the multi-FPGA global synchronization trigger method of the foregoing FPGA simulation verification platform.

[0049] In this embodiment, the host computer is connected to multiple FPGAs through a high-speed interconnect network. The foregoing host computer reads the trigger status register of the master node in each FPGA through software to obtain the system trigger status. If the value of the trigger status register is "1", it reads the register module of the master node to obtain the trigger moment timestamp rmt_trig_time_stamp and the trigger moment sampling address rmt_trig_addr, and then restores and reconstructs the waveforms of the sampling results of all FPGA nodes according to the values of the trigger moment timestamp rmt_trig_time_stamp and the trigger moment sampling address rmt_trig_addr.

[0050] In addition, this embodiment also provides a computer-readable storage medium. The foregoing computer-readable storage medium stores a computer program, and the foregoing computer program is used to be programmed or configured by a microprocessor to execute the multi-FPGA global synchronization trigger method of the foregoing FPGA simulation verification platform.

[0051] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) that contain computer-usable program code. The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a system for realizing the functions specified in the Figure 1 single flow or multiple flows and / or blocks Figure 1 single block or multiple blocks. These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing devices to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including an instruction system that realizes the functions specified in the Figure 1 single flow or multiple flows and / or blocks Figure 1 single block or multiple blocks. These computer program instructions can also be loaded onto a computer or other programmable data processing devices, so that a series of operation steps are executed on the computer or other programmable devices to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable devices provide steps for realizing the functions specified in the Figure 1 single flow or multiple flows and / or blocks Figure 1 single block or multiple blocks.

[0052] The above is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, several improvements and refinements made without departing from the principle of the present invention should also be regarded as within the protection scope of the present invention.

Claims

1. A multi-FPGA global synchronization triggering method for an FPGA simulation and verification platform, characterized in that, Including: S1. In each clock cycle, each FPGA including the master node and slave nodes compares the inserted trigger probe signal value with a preset trigger condition in real time to determine whether the trigger condition is met. If the master node meets the trigger condition, jump to step S3; If a slave node meets the trigger condition, jump to step S2; S2. The triggered slave node obtains the trigger moment timestamp trig_time_stamp and the trigger moment sampling address trig_addr, encapsulates them into a message and sends it to the master node. The master node parses the trigger moment timestamp rmt_trig_time_stamp and the trigger moment sampling address rmt_trig_addr in the message. The master node calculates the depth Tcnt of continuous sampling after the trigger of the main FPGA node according to the local current moment timestamp, the received remote trigger moment timestamp rmt_trig_time_stamp and the preset waveform ratio before and after the trigger. m And the sampling stop timestamp stop_time_stamp, sets the trigger status register to "1", and saves the trigger status register, the remote trigger moment timestamp rmt_trig_time_stamp and the trigger moment sampling address rmt_trig_addr to the register module for the host computer software to read. At the same time, the master node encapsulates the sampling stop timestamp stop_time_stamp into a message and broadcasts it to all slave nodes; Jump to step S3; S3. The master node obtains the trigger time timestamp trig_time_stamp and the trigger-time sampling address trig_addr. The master node calculates the depth Tcnt for continued sampling after the trigger based on the local timestamp and the preset waveform ratio before and after the trigger. m And the sampling stop timestamp stop_time_stamp. Set the trigger status register to "1", and save the trigger status register, the trigger time timestamp trig_time_stamp, and the trigger-time sampling address trig_addr to the register module for the host computer software to read. At the same time, the master node encapsulates the sampling stop timestamp stop_time_stamp into a message and broadcasts it to all slave nodes. Jump to step S4; S4. The slave node parses the sampling stop timestamp stop_time_stamp in the received message, and stops sampling when the local timestamp is equal to the sampling stop timestamp stop_time_stamp.

2. The multi-FPGA global synchronization triggering method of the FPGA simulation and verification platform according to claim 1, wherein When each FPGA in step S1 compares the inserted trigger probe signal value with the preset trigger condition in real time to determine whether the trigger condition is met, the trigger counter trig_cnt of each FPGA is driven by the global synchronous clock signal gclk to ensure that the count values of the trigger counters trig_cnt of all FPGAs are completely synchronized.

3. The multi-FPGA global synchronization triggering method of the FPGA simulation and verification platform according to claim 1, wherein The obtaining of the trigger moment timestamp trig_time_stamp and the trigger moment sampling address trig_addr means taking the current moment timestamp recorded according to the trigger moment of the trigger counter trig_cnt as the trigger moment timestamp trig_time_stamp, and taking the address where the sampling data corresponding to the trigger moment is stored in the memory as the trigger moment sampling address trig_addr.

4. The multi-FPGA global synchronization triggering method of the FPGA simulation and verification platform according to claim 1, characterized in that In step S3, the master node calculates the depth Tcnt for continuous sampling after triggering based on the local timestamp and the preset waveform ratio before and after triggering. m The calculation function expression for the sampling stop timestamp stop_time_stamp is as follows: Tcnt m =Scnt*(1-k) Ts s = Ts m + Tcnt m = Ts m + Scnt*(1 - k) In the above formula, Scnt is the preset sampling depth, k is the preset waveform ratio coefficient before and after triggering, Ts m is the current timestamp of the master node, Ts s is the sampling stop timestamp stop_time_stamp.

5. The multi-FPGA global synchronization triggering method of the FPGA simulation and verification platform according to claim 1, characterized in that, In step S2, the master node calculates the depth Tcnt for continuous sampling after triggering of the master FPGA node based on the local current time stamp, the received remote trigger time stamp rmt_trig_time_stamp, and the preset waveform ratio before and after triggering m and the function expressions for the sampling stop time stamp stop_time_stamp are as follows: Tcnt m =Scnt*(1-k)- (Ts m - Ts r ) Ts s = Ts m + Tcnt m = Ts m + (Scnt*(1-k) - (Ts m - Ts r )) = Scnt*(1-k) + Ts r In the above formula, Tcnt m is the depth of continuous sampling after the main FPGA node is triggered, Ts s is the sampling stop timestamp stop_time_stamp, Ts m is the current timestamp of the main node, Scnt is the preset sampling depth, k is the preset waveform ratio coefficient before and after triggering, Ts r is the remote slave node trigger time timestamp rmt_trig_time_stamp.

6. The multi-FPGA global synchronization triggering method of the FPGA simulation and verification platform according to claim 1, characterized in that Before step S1, it also includes selecting one FPGA to be configured as the master node, writing the node number of the master node into the master node number register of the remaining FPGAs serving as slave nodes, and writing the node numbers of all slave nodes into the FPGA node list register of the master node.

7. The multi-FPGA global synchronization triggering method of the FPGA simulation and verification platform according to claim 1, characterized in that Before step S1, it also includes configuring sampling parameters for the master node, connecting the probe signals participating in the trigger to the interface of the trigger detection module according to the trigger condition set by the user, and configuring the register to define the signal format and trigger condition of the trigger probe.

8. A multi-FPGA global synchronization triggering system for an FPGA simulation and verification platform, comprising a high-speed interconnection network and a plurality of FPGAs respectively connected to the high-speed interconnection network, characterized in that, The FPGA is programmed or configured to execute the multi-FPGA global synchronous trigger method of the FPGA simulation verification platform according to any one of claims 1 to 7.

9. The multi-FPGA global synchronization trigger system of the FPGA simulation and verification platform according to claim 8 further includes a host computer, characterized in that, The host computer is connected to multiple FPGAs through a high-speed interconnection network. The host computer reads the trigger status register of the master node in each FPGA through software to obtain the system trigger status. If the value of the trigger status register is "1", it reads the register module of the master node to obtain the trigger moment timestamp rmt_trig_time_stamp and the trigger moment sampling address rmt_trig_addr, and then restores and reconstructs the waveforms of the sampling results of all FPGA nodes according to the values of the trigger moment timestamp rmt_trig_time_stamp and the trigger moment sampling address rmt_trig_addr.

10. A computer-readable storage medium storing a computer program therein, characterized in that, The computer program is used to be programmed or configured by a microprocessor to execute the multi-FPGA global synchronous trigger method of the FPGA simulation verification platform according to any one of claims 1 to 7.

Images