A method and system for legalizing chip standard cells considering adjacent diffusion effects
By constructing auxiliary graphs and Hamiltonian paths using the Hamiltonian completion algorithm, the performance degradation problem caused by adjacency diffusion effect in the legalization of standard chip cells is solved. The optimization of adjacency diffusion effect and minimization of cell movement are achieved, thereby improving chip performance and operating efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- QILU UNIVERSITY OF TECHNOLOGY (SHANDONG ACADEMY OF SCIENCES)
- Filing Date
- 2022-11-28
- Publication Date
- 2026-05-05
AI Technical Summary
Traditional methods for legalizing standard chip cells cannot effectively address the performance degradation caused by adjacency diffusion effects. Especially with the ever-increasing performance requirements of chip devices, it has become a challenge to reduce adjacency diffusion violations and minimize cell movement without increasing area overhead.
An algorithm based on Hamiltonian completion is adopted. By constructing an auxiliary graph, a minimum spanning tree, and a Hamiltonian path, the cells are reordered to achieve consistent diffusion height between adjacent cells. The station position of the cell on the layout row is calculated by combining minimum spanning tree decomposition and Hamiltonian path reconnection.
Without increasing area overhead, it effectively reduces adjacent diffusion violations, achieves better chip performance and minimizes cell movement, thereby improving actual runtime.
Smart Images
Figure CN115796109B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic design automation, and particularly relates to a method and system for legalizing chip standard cells considering the adjacent diffusion effect. Background Technology
[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.
[0003] With the advancements in photolithography and the expansion of devices in advanced technologies, device performance depends not only on geometry-independent parameters but also on layout-dependent effects (LDEs). Performance degradation using LDEs can be as high as 10% or more. Neighbor diffusion effect (NDE) is an important type of LDE, caused by different diffusion heights (fin counts) between two adjacent cells. Notably, each cell has two diffusion heights on the left and right sides, and these heights are not necessarily identical. This mismatch in diffusion heights between adjacent transistors degrades transistor performance; this effect has become critical and requires addressing with advanced technologies.
[0004] In the traditional standard cell legalization of chips, only the case where the diffusion height on both sides of the cell is equal is often considered. However, with the continuous development of chip devices and photolithography technology, standard cells with the same diffusion height on both sides can no longer meet the performance requirements of chip devices. The adjacent diffusion effect (NDE) will have a more serious impact on chip performance, and the traditional standard cell layout method can no longer meet the growing demand.
[0005] In addition to reducing NDE violations and minimizing maximum cell movement, cells must also satisfy the following hard constraints:
[0006] (1) Standard cells must be placed within the chip area;
[0007] (2) Standard units must not overlap;
[0008] (3) Standard cells must be placed on the site of the layout row;
[0009] Therefore, under the premise of satisfying the above hard constraints, how to accurately control the different diffusion heights on the left and right sides of the control unit to achieve the optimal legalization of the chip standard cell is a topic worthy of research. Summary of the Invention
[0010] To overcome the shortcomings of the prior art, this invention provides a chip standard cell legalization method and system that considers the adjacency diffusion effect. It designs an algorithm based on Hamiltonian completion to calculate the new position of the cell. By moving the cell on a single layout row to make adjacent cells have the same diffusion height, it reduces NDE violations to near-optimal minimum and minimizes the maximum cell movement without any area overhead, while achieving better actual runtime.
[0011] To achieve the above objectives, one or more embodiments of the present invention provide the following technical solutions:
[0012] The first aspect of this invention provides a method for legalizing chip standard cells considering adjacent diffusion effects;
[0013] A method for legalizing chip standard cells considering adjacent diffusion effects includes:
[0014] An auxiliary diagram is constructed based on the unit layout and the left and right expansion height;
[0015] By using the minimum spanning tree and Hamiltonian path, the cells of the auxiliary graph are reordered to obtain the cell arrangement order;
[0016] Calculate the station position of the unit on the layout row based on the unit arrangement order and unit width.
[0017] Furthermore, the construction of the auxiliary graph specifically involves:
[0018] For each cell, construct three vertices: cell vertex, left diffusion height vertex, and right diffusion height vertex;
[0019] Each cell vertex has an edge between it and the left diffusion height vertex, and an edge between it and the right diffusion height vertex;
[0020] There is an edge between the vertices of different units with the same diffusion height.
[0021] Furthermore, the reordering of the units in the auxiliary diagram specifically involves:
[0022] Find the minimum spanning tree of the auxiliary graph;
[0023] Decompose the minimum spanning tree into multiple non-intersecting paths;
[0024] Reconnect multiple non-intersecting paths to form a Hamiltonian path;
[0025] The order of the cells is determined by the order of the vertices in the Hamiltonian path.
[0026] Furthermore, the process of finding the minimum spanning tree of the auxiliary graph specifically involves:
[0027] (1) Set the weight of the edge between two vertices in the auxiliary graph to the sum of the degrees of the two vertices;
[0028] (2) Remove the edge with the largest weight that will not result in an isolated vertex in the auxiliary graph after removal. If there are two edges with the largest weight and the same weight, remove either one.
[0029] Repeat steps (1) and (2) until the auxiliary graph becomes a tree.
[0030] Furthermore, the process of decomposing the minimum spanning tree into multiple non-intersecting paths is based on the idea of Hamiltonian completion, which decomposes and reconnects the minimum spanning tree to form multiple non-intersecting paths.
[0031] Furthermore, the reconnection of multiple non-intersecting vertex paths into Hamiltonian paths specifically involves:
[0032] (1) Let n be the number of non-intersecting paths at vertices, a and b be the range of the maximum element displacement, and disp be the current maximum displacement value; set the maximum number of NDE violations allowed η and the maximum number of elements allowed to exceed the maximum displacement δ;
[0033] (2) Let
[0034] (3) Add n-η edges with weights as small as possible less than disp, so that the paths with non-intersecting vertices are connected end to end, and the standard cells corresponding to the vertices connected by the edges have the same diffusion height.
[0035] (4) Add η edges with weights as small as possible less than disp to connect the remaining end points;
[0036] (5) After adding n edges, disconnect one edge in the Hamiltonian circuit formed so that c1 is the starting point of the Hamiltonian path, and calculate the number of edges with a weight greater than disp in the formed Hamiltonian path, maxedge.
[0037] (6) If maxedge > δ, then
[0038] If maxedge < δ, then
[0039] If maxedge = δ, proceed to step (8).
[0040] (7) Repeat steps (2)-(6);
[0041] (8) Output the Hamiltonian path from step (5).
[0042] Furthermore, the station position of the computing unit on the layout row is specifically as follows:
[0043] The number of stations occupied is calculated based on the width of the unit;
[0044] Place the units sequentially in the next station position after the station occupied by the previous unit.
[0045] A second aspect of the present invention provides a chip standard cell legalization system that takes into account the adjacent diffusion effect.
[0046] A chip standard cell legalization system considering adjacency diffusion effect includes an auxiliary graph construction module, a cell sorting module, and a position calculation module.
[0047] The auxiliary graph construction module is configured to construct auxiliary graphs based on cell layout and left and right diffusion height.
[0048] The cell sorting module is configured to: reorder the cells of the auxiliary graph using the minimum spanning tree and Hamiltonian path to obtain the cell arrangement order;
[0049] The location calculation module is configured to calculate the station position of a cell on a layout row based on the cell arrangement order and cell width.
[0050] A third aspect of the present invention provides a computer-readable storage medium having a program stored thereon that, when executed by a processor, implements the steps of a chip standard cell legalization method considering adjacent diffusion effects as described in the first aspect of the present invention.
[0051] A fourth aspect of the present invention provides an electronic device including a memory, a processor, and a program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the steps of a chip standard cell legalization method considering adjacent diffusion effects as described in the first aspect of the present invention.
[0052] The above one or more technical solutions have the following beneficial effects:
[0053] This invention designs an algorithm based on Hamiltonian completion to calculate the new position of a cell. By moving the cell on a single layout row, it makes adjacent cells have the same diffusion height. In particular, it accurately calculates the different diffusion heights of the left and right sides of the cell. Without any area overhead, it reduces NDE violations to a near-optimal minimum and minimizes the maximum cell movement, while achieving better actual runtime.
[0054] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0055] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.
[0056] Figure 1 This is a flowchart of the method in the first embodiment.
[0057] Figure 2 is an example diagram of standard cell diffusion height and NDE violation in the first embodiment.
[0058] Figure 3 is an example diagram of the auxiliary diagram in the first embodiment.
[0059] Figure 4 This is an example diagram of the minimum spanning tree in the first embodiment.
[0060] Figure 5 This is an example diagram of multiple non-intersecting paths at the vertices in the first embodiment.
[0061] Figure 6 This is an example diagram of the Hamiltonian path in the first embodiment.
[0062] Figure 7 This is a system structure diagram of the second embodiment. Detailed Implementation
[0063] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0064] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of the invention; unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.
[0065] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments of the present invention; as used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise; furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.
[0066] This implementation involves a large number of parameters, which are explained as follows:
[0067] c i1 c i and c i2 In the auxiliary graph, each standard unit corresponds to three vertices, where c i c represents the standard unit vertex. i1 and c i2This represents the left and right diffusion height vertices on either side of the standard cell;
[0068] T: Minimum spanning tree of the auxiliary graph generated using Prim's algorithm
[0069] H: A temporary variable used to store a copy of T;
[0070] N: The number of non-intersecting paths between vertices;
[0071] a, b: Empirical parameters, representing the range of maximum element displacement;
[0072] disp: Represents the current maximum cell displacement in the loop;
[0073] η: The maximum number of NDE violations allowed;
[0074] δ: The maximum number of elements allowed to exceed the maximum displacement;
[0075] maxedge: The number of edges with a weight greater than disp in the formed Hamiltonian path.
[0076] NDE (Neighbor-to-Diffusion) is caused by the difference in diffusion height (fin number) between two adjacent cells. With the continuous development of the chip manufacturing industry, the impact of NDE on chip performance is becoming increasingly significant. Figure 2(a) shows the layout of four standard cells with NDE violations. Each standard cell has different diffusion heights on both sides, such as c2 and c3, c3 and c4. The difference in diffusion height between two adjacent cells will result in NDE violations. The solution to NDE violations is to make the cells symmetrically flipped or moved to make adjacent cells have the same diffusion height. Figure 2(b) shows the layout of standard cells after all NDE violations have been resolved. To better describe the method of this invention, it is assumed that all standard cells are single-row high cells.
[0077] Example 1
[0078] This embodiment discloses a method for legalizing standard chip cells that takes into account the adjacent diffusion effect;
[0079] like Figure 1 As shown, a method for legalizing chip standard cells considering adjacent diffusion effects includes:
[0080] S1: Construct an auxiliary diagram based on the cell layout and the left and right diffusion height.
[0081] To transform the standard unit legalization problem into a Hamiltonian path problem, this embodiment proposes the concept of an auxiliary graph; the construction rules for the auxiliary graph are as follows:
[0082] (1) Vertex construction: Based on the cells in the row, construct three vertices for each cell in the auxiliary graph: cell vertex c i Left diffusion height vertex c i1 And the right spread height vertex c i2 .
[0083] (2) Edge construction: Each cell vertex has one edge between itself and the left diffusion height vertex, and one edge between itself and the right diffusion height vertex, that is, each cell has two edges (c i c i1 ) and (c i c i2 ).
[0084] There is an edge between the vertices of different units with the same diffusion height, i.e., if c in =c jm (where i ≠ j in n = {1, 2} and m = {1, 2}), then there is an edge (c) in the auxiliary graph. in c jm ).
[0085] After connecting the edges between the vertices in the auxiliary graph according to this rule, the auxiliary graph is completed.
[0086] Figure 3 illustrates an example of constructing an auxiliary graph. Figure 3(a) shows the positions of four standard cells {c1, c2, c3, c4} on the layout row, and Figure 3(b) shows the completed auxiliary graph. Each cell corresponds to three vertices on the auxiliary graph, and there are two edges between the three vertices of each cell. As shown in Figure 3(a), the left diffusion height of c1 is equal to the left diffusion height of c2, and the left and right diffusion heights of c4. Therefore, the auxiliary graph in Figure 3(b) has three edges (c1, c2, c3, c4). 11 c 21 ), (c 11 c 41 ), (c 11 c 42 ). And so on, connecting other edges.
[0087] S2: Using the minimum spanning tree and Hamiltonian path, the cells of the auxiliary graph are reordered to obtain the cell arrangement order, specifically:
[0088] S201: Find the minimum spanning tree of the auxiliary graph;
[0089] Based on the auxiliary graph constructed in step S1, the weights of the edges are marked as the distance between corresponding units of two vertices. Then, Prim's algorithm is used to obtain the minimum spanning tree of the auxiliary graph. The minimum spanning tree of the auxiliary graph shown in Figure 3(b) is as follows: Figure 4 As shown.
[0090] S202: Decompose the minimum spanning tree into multiple non-intersecting paths;
[0091] This embodiment employs the idea of Hamiltonian completion, decomposing and reconnecting the auxiliary graph into multiple non-intersecting paths, and finally obtaining a Hamiltonian path for the auxiliary graph by connecting these non-intersecting paths. Therefore, based on the minimum spanning tree T obtained in step S201, the minimum spanning tree T is first decomposed into multiple non-intersecting paths. Firstly, this embodiment proposes three operations:
[0092] Operation 1: Remove any terminal point u adjacent to any vertex w of degree 2 from the minimum spanning tree T.
[0093] Operation 2: If c i It is an endpoint, and c i With c i1 (c i2 Adjacent and c i1 (c i2 If the degree of vertex c is 3 or higher, then delete vertex c. i c i1 (c i2 ) and another with c i1 (c i2 Adjacent endpoints. If c i It is not an endpoint, and c i With c i1 and c i2 If points are adjacent and have a degree greater than or equal to 3, then delete point c. i c i1 c i2 、and c i1 Adjacent endpoints and c i2 Adjacent endpoints.
[0094] Operation 3: Delete an isolated point or an isolated edge from T.
[0095] Through the above three operations, this embodiment proposes a method for decomposing auxiliary diagrams, the steps of which are as follows:
[0096] (1) Let H = T, and delete all edges in H;
[0097] (2) If operation 1 can be applied to the minimum spanning tree T, then perform operation 1 and add the edges of the vertices deleted in operation 1 to H, and go to step (2); if operation 1 cannot be applied to the minimum spanning tree T and the minimum spanning tree T contains at least one isolated vertex or edge, then go to step (4); otherwise go to step (3).
[0098] (3) If operation 2 cannot be applied to the minimum spanning tree T, the decomposition ends; otherwise, apply operation 2 to the minimum spanning tree T, add the edges between the multiple vertices deleted in operation 2 to H, and go to step (4).
[0099] (4) If operation 3 cannot be applied to the minimum spanning tree T, then go to step (2); otherwise, apply operation 3 to the minimum spanning tree T, add the edges of the vertices deleted in operation 3 to H, and go to step (4).
[0100] The minimum spanning tree is decomposed into multiple non-intersecting paths using the method described above. Figure 3 shows the auxiliary graph with multiple non-intersecting paths, such as... Figure 5 As shown.
[0101] S203: Reconnect multiple non-intersecting vertex paths into a Hamiltonian path;
[0102] In this embodiment, it is necessary not only to reduce NDE violations but also to minimize the maximum element displacement. By pre-setting the maximum number of NDE violations η and the maximum number of elements exceeding the maximum displacement δ, multiple non-intersecting vertex paths are connected end-to-end based on these conditions. Through this method, a result that minimizes twice the maximum displacement is obtained without exceeding the maximum number of NDE violations η. Specifically:
[0103] (1) Let n be the number of non-intersecting paths at vertices, a and b be the range of the maximum element displacement, and disp be the current maximum displacement value; set the maximum number of NDE violations allowed η and the maximum number of elements allowed to exceed the maximum displacement δ;
[0104] (2) Let
[0105] (3) Add n-η edges with weights as small as possible less than disp, so that the paths with non-intersecting vertices are connected end to end, and the standard cells corresponding to the vertices connected by the edges have the same diffusion height.
[0106] (4) Add η edges with weights as small as possible less than disp to connect the remaining end points;
[0107] (5) After adding n edges, break one edge in the Hamiltonian circuit so that c1 is the starting point of the Hamiltonian path, and calculate the number of edges with a weight greater than disp in the formed Hamiltonian path, maxedge:
[0108] (6) If maxedge > δ, then
[0109] If maxedge < δ, then
[0110] If maxedge = δ, proceed to step (8).
[0111] (7) Repeat steps (2)-(6);
[0112] (8) Output the Hamiltonian path from step (5).
[0113] The Hamiltonian path in the auxiliary graph shown in Figure 3(b) is as follows: Figure 6 As shown.
[0114] S204: Determine the order of the cells based on the vertex order in the Hamiltonian path.
[0115] The Hamiltonian path of the auxiliary graph obtained in step S203 can correspond to an arrangement order of standard chip units. In step S1, each standard unit is assigned to three vertices in the auxiliary graph. The three vertices of each standard unit are adjacent to each other. After the unit sorting in step 2, the three vertices of each unit are still adjacent to each other in the final Hamiltonian path. Therefore, an arrangement order of standard units can be obtained based on the vertex order in the Hamiltonian path.
[0116] S3: Calculate the station position of the unit on the layout row based on the unit arrangement order and unit width.
[0117] After obtaining the standard cell arrangement order, since the standard cell layout of the chip requires that cells cannot overlap and that cells must be placed on the stations of the layout row, the cells need to be placed sequentially according to the cell arrangement order. First, calculate the number of stations occupied based on the width of the cell; then place the cells in the order of the next station position after the station occupied by the previous cell.
[0118] Example 2
[0119] This embodiment discloses a chip standard cell legalization system that considers the adjacent diffusion effect;
[0120] like Figure 7 As shown, a chip standard cell legalization system considering adjacency diffusion effect includes an auxiliary graph construction module, a cell sorting module, and a position calculation module:
[0121] The auxiliary graph construction module is configured to construct auxiliary graphs based on cell layout and left and right diffusion height.
[0122] The cell sorting module is configured to: reorder the cells of the auxiliary graph using the minimum spanning tree and Hamiltonian path to obtain the cell arrangement order;
[0123] The location calculation module is configured to calculate the station position of a cell on a layout row based on the cell arrangement order and cell width.
[0124] Example 3
[0125] The purpose of this embodiment is to provide a computer-readable storage medium.
[0126] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in a chip standard cell legalization method considering adjacent diffusion effects as described in Embodiment 1 of this disclosure.
[0127] Example 4
[0128] The purpose of this embodiment is to provide an electronic device.
[0129] An electronic device includes a memory, a processor, and a program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps in a chip standard cell legalization method considering adjacent diffusion effects as described in Embodiment 1 of this disclosure.
[0130] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for legalizing chip standard cells considering adjacent diffusion effects, characterized in that, include: An auxiliary diagram is constructed based on the unit layout and the left and right expansion height; By using the minimum spanning tree and Hamiltonian path, the cells of the auxiliary graph are reordered to obtain the cell arrangement order; Calculate the station position of the unit on the layout row based on the unit arrangement order and unit width; Specifically, the construction of the auxiliary graph includes: For each cell, construct three vertices: cell vertex, left diffusion height vertex, and right diffusion height vertex; Each cell vertex has an edge between it and the left diffusion height vertex, and an edge between it and the right diffusion height vertex; There is an edge between the vertices of different units with the same diffusion height; The reordering of the units in the auxiliary diagram specifically involves: Find the minimum spanning tree of the auxiliary graph; Decompose the minimum spanning tree into multiple non-intersecting paths; Reconnect multiple non-intersecting paths to form a Hamiltonian path; The order of the cells is determined by the order of the vertices in the Hamiltonian path; The process of finding the minimum spanning tree of the auxiliary graph is as follows: (1) Set the weight of the edge between two vertices in the auxiliary graph to the sum of the degrees of the two vertices; (2) Remove the edge with the largest weight that will not result in an isolated vertex in the auxiliary graph after removal. If there are two edges with the largest weight and the same weight, remove either one. Repeat steps (1) and (2) until the auxiliary graph becomes a tree; The method of decomposing the minimum spanning tree into multiple non-intersecting paths is based on the idea of Hamiltonian completion, which decomposes and reconnects the minimum spanning tree to form multiple non-intersecting paths. The reconnection of multiple non-intersecting paths into Hamiltonian paths specifically involves: (1) Let Let be the number of non-intersecting paths between vertices. and The range of the maximum element displacement. Sets the current maximum displacement value; sets the maximum number of NDE violations allowed. and the maximum number of elements allowed to exceed the maximum displacement. ; (2) Let ; (3) Add The weight of each item should be as small as possible. The edges are such that the vertices do not intersect, the paths are connected end to end, and the standard cells corresponding to the vertices connected by the edges have the same diffusion height; (4) Add arbitrarily The weight of each item should be as small as possible. The edges connect the remaining end points; (5) After adding Disconnect one edge in the Hamiltonian cycle formed after the edge is removed. As the starting point of the Hamiltonian path, and the weights in the calculated Hamiltonian path are greater than... Number of edges ; (6) If ,So ; if ,So ; if Execute step (8). (7) Repeat steps (2)-(6); (8) Output the Hamiltonian path from step (5); The specific location of the computing unit on the layout row is as follows: The number of stations occupied is calculated based on the width of the unit; Place the units sequentially in the next station position after the station occupied by the previous unit.
2. A chip standard cell legitimization system considering adjacent diffusion effects, characterized in that, The chip standard cell legalization method considering adjacency diffusion effect as described in claim 1 includes an auxiliary graph construction module, a cell sorting module, and a position calculation module: The auxiliary graph construction module is configured to construct auxiliary graphs based on cell layout and left and right diffusion height. The cell sorting module is configured to: reorder the cells of the auxiliary graph using the minimum spanning tree and Hamiltonian path to obtain the cell arrangement order; The location calculation module is configured to calculate the station position of a cell on a layout row based on the cell arrangement order and cell width.
3. A computer-readable storage medium having a program stored thereon, characterized in that, When executed by the processor, the program implements the steps in the chip standard cell legalization method considering the adjacency diffusion effect as described in claim 1.
4. An electronic device, comprising a memory, a processor, and a program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps in the chip standard cell legalization method considering the adjacency diffusion effect as described in claim 1.