Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for preparing the same, the method comprising: forming an etch stop layer, a first dielectric layer, an auxiliary dielectric layer, and a second dielectric layer stacked in sequence from bottom to top; using a photoresist layer as an etch barrier layer, patterning the second dielectric layer to obtain a first opening pattern, the bottom of the first opening pattern having a second opening pattern that partially exposes the auxiliary dielectric layer; forming a first trench that penetrates the second dielectric layer and the auxiliary dielectric layer and extends to the first dielectric layer based on the first opening pattern, forming a second trench that penetrates the first dielectric layer from the bottom of the first trench and extends to the etch stop layer based on the second opening pattern; and forming a conductive layer in the first and second trenches. The present invention can achieve the preparation of a damascene-like inlay structure through only one coating and development, thereby simplifying the process flow, reducing production costs, and not requiring expensive photolithography equipment support, resulting in lower equipment costs. Furthermore, the present invention has wide applicability and is compatible with a variety of semiconductor processes.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor device manufacturing and relates to a semiconductor device and a preparation method thereof. Background Art

[0002] The IC manufacturing industry is experiencing a dramatic shift in metal interconnect strategies. After many years of development, copper is now the primary inter-chip conductor used in many IC interconnects. Due to the difficulty of etching copper, early copper etching researchers were forced to consider alternative methods for creating metal lines. Dual Damascene has become the consensus method for copper metallization.

[0003] The dual damascene process is currently divided into two main types from a process perspective: one is via first (ViaFirst), trench last (Trench Last), and the other is trench first (Trench First), via last (Via Last). Both of these processes require two or more processes such as coating, exposure, and dry etching to achieve. The difference in the critical dimensions (CD) between the two times forms the pattern of the trench or via. Since multiple coating and exposure processes are required, the process cost is relatively high. In addition, multiple exposures are required on the same film layer, and the requirements for layer alignment (OVL) are high. Advanced equipment support is required, which means that the performance requirements of the lithography machine are high, and thus the cost of the photoresist is also high. In addition, the second coating currently has a certain step, so there are often defects caused by unclean development. Sufficient windows are required during exposure and development to solve the problem of defects. Problems such as small process windows are also prominent.

[0004] Therefore, how to provide a new method for preparing semiconductor devices to simplify the process and reduce production costs has become an important technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a semiconductor device and a method for preparing the same, which is used to solve the problem in the prior art that forming two connected conductive layers with different critical dimensions requires multiple photomasks, multiple coatings, exposures and developments, resulting in high costs and a small process window.

[0006] To achieve the above-mentioned and other related objects, the present invention provides a method for preparing a semiconductor device, comprising the following steps:

[0007] Providing a substrate, and forming an etch stop layer, a first dielectric layer, an auxiliary dielectric layer, and a second dielectric layer stacked sequentially from bottom to top on the substrate;

[0008] Using the photoresist layer as an etching barrier, patterning the second dielectric layer to form a first opening pattern extending downward from the upper surface of the second dielectric layer, wherein the bottom of the first opening pattern has a second opening pattern exposing a portion of the auxiliary dielectric layer;

[0009] Using the photoresist layer and the second dielectric layer remaining at the bottom of the first opening pattern as an etching stop layer, removing the auxiliary dielectric layer based on the second opening pattern to expose the first dielectric layer at the bottom of the second opening pattern;

[0010] Continuing to use the photoresist layer as an etching barrier layer, based on the first opening pattern and the second opening pattern, to remove the first dielectric layer and the second dielectric layer until the bottom of the first opening pattern exposes the auxiliary dielectric layer;

[0011] removing the auxiliary dielectric layer at the bottom of the first opening pattern;

[0012] Continuing to use the photoresist layer as an etch stop layer, removing the first dielectric layer, forming a first trench based on the first opening pattern that penetrates the second dielectric layer and the auxiliary dielectric layer and extends to the first dielectric layer, and forming a second trench based on the second opening pattern that penetrates the first dielectric layer from the bottom of the first trench and extends to the etch stop layer;

[0013] The photoresist layer and the etch stop layer at the bottom of the second trench are removed, and a conductive layer is formed in the first trench and the second trench.

[0014] Optionally, the method uses the photoresist layer as an etching stop layer to pattern the second dielectric layer to form a first opening pattern extending downward from the upper surface of the second dielectric layer, wherein the bottom of the first opening pattern has a second opening pattern that exposes a portion of the auxiliary dielectric layer. The method further includes: the photoresist layer has a photoresist opening pattern, and by controlling the inclination of the sidewalls of the photoresist opening pattern, the second opening pattern having the exposed portion of the auxiliary dielectric layer is formed at the bottom of the first opening pattern.

[0015] Optionally, the method uses the photoresist layer as an etching stop layer to pattern the second dielectric layer to form a first opening pattern extending downward from the upper surface of the second dielectric layer, wherein the bottom of the first opening pattern has a second opening pattern that exposes a portion of the auxiliary dielectric layer. The method also includes: utilizing the phase difference inherent in the photolithography machine to prepare a photoresist opening pattern in the photoresist layer, wherein the photoresist opening pattern has a first side wall and a second side wall that is asymmetric to the first side wall, and the angle between the first side wall and the bottom surface of the photoresist opening is different from the angle between the second side wall and the bottom surface of the photoresist opening.

[0016] Optionally, the first dielectric layer includes one or more of a borophosphosilicate glass layer, a phosphosilicate glass layer, a fluorosilicone glass layer, an undoped silica glass layer, an ethyl orthosilicate layer, a thermally oxidized silicon dioxide layer, and a wet oxidized silicon dioxide layer; the material of the auxiliary dielectric layer includes silicon carbide; the second dielectric layer includes one or more of a borophosphosilicate glass layer, a phosphosilicate glass layer, a fluorosilicone glass layer, an undoped silica glass layer, an ethyl orthosilicate layer, a thermally oxidized silicon dioxide layer, and a wet oxidized silicon dioxide layer; the material of the etch stop layer includes one of silicon nitride and silicon oxynitride.

[0017] Optionally, the method uses the photoresist layer and the second dielectric layer remaining at the bottom of the first opening pattern as an etching barrier layer, removes the auxiliary dielectric layer based on the second opening pattern to expose the first dielectric layer at the bottom of the second opening pattern, and further includes: removing the auxiliary dielectric layer by dry etching, wherein the etching rate of the dry etching gas used for the auxiliary dielectric layer is greater than the etching rate of the second dielectric layer, and when the auxiliary dielectric layer exposed by the second opening pattern is completely dry-etched, there is still a remaining second dielectric layer at the bottom of the first opening pattern.

[0018] Optionally, the dry etching gas contains at least SF6 and O2.

[0019] Optionally, the step of continuing to use the photoresist layer as an etching barrier layer, removing the first dielectric layer and the second dielectric layer based on the first opening pattern and the second opening pattern, and stopping when the auxiliary dielectric layer is exposed at the bottom of the first opening pattern, further includes: removing the first dielectric layer and the second dielectric layer by dry etching, the etching rate of the dry etching gas used for the first dielectric layer and the second dielectric layer being greater than the etching rate for the auxiliary dielectric layer, and the thickness of the first dielectric layer removed based on the second opening pattern being less than the thickness of the first dielectric layer.

[0020] Optionally, the dry etching gas includes one or more of CF4 / CHF3 / Ar, CF4 / CHF3 / Ar / O2, C4F8 / O2 / Ar, C4F8 / O2 / CO / Ar, C4F6 / O2 / Ar, C4F6 / O2 / CO / Ar, C5F8 / O2 / Ar and C5F8 / O2 / CO / Ar gas combinations.

[0021] The present invention also provides a semiconductor device, wherein: the semiconductor device is manufactured using the method for preparing a conductor device as described in any one of the above items, and includes a dielectric layer and a first trench and a second trench located in the dielectric layer, the first trench extending downward from the upper surface of the dielectric layer, and the trench depth of the first trench is less than the thickness of the dielectric layer, the second trench extending downward from the bottom surface of the first trench and penetrating the dielectric layer, and a conductive layer is provided in the first trench and the second trench.

[0022] Optionally, the second groove is located at an edge of the bottom of the first groove.

[0023] Optionally, the material of the conductive layer includes at least one of Cu, W, Al, Ag and Au, and the conductive layer serves as a conductive interconnection layer.

[0024] Optionally, the groove depth of the first groove is greater than the groove depth of the second groove.

[0025] As described above, the semiconductor device and preparation method of the present invention utilize the inherent phase difference of the photoresist machine to form an asymmetric photoresist opening morphology, and then use a subsequent preset etching menu to etch a stepped opening with asymmetric left and right depths in the dielectric layer. Based on the left and right depth differences and through a reasonable combination of dielectric film layers, the present invention can achieve the preparation of a damascene-like structure by only one coating and development, which not only simplifies the process flow, but also reduces production costs, does not require expensive photolithography equipment support, and has lower equipment costs. The present invention has a wide range of applicability and is compatible with current CMOS / DMOS / BCD processes, and has a wider application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a process flow chart of a method for manufacturing a semiconductor device according to the present invention.

[0027] Figure 2 It is a schematic diagram showing the device structure obtained after the steps of forming an etch stop layer, a first dielectric layer, an auxiliary dielectric layer and a second dielectric layer stacked sequentially from bottom to top on a substrate according to the method for preparing a semiconductor device of the present invention.

[0028] Figure 3 The device structure diagram is shown after the steps of forming a photoresist layer on the second dielectric layer and forming a photoresist opening pattern in the photoresist layer based on a photomask having an opening pattern according to the method for preparing the semiconductor device of the present invention.

[0029] Figure 4 It is a schematic diagram showing the structure of the device obtained after the steps of patterning the second dielectric layer using the photoresist layer as the etching barrier layer in the method for preparing the semiconductor device of the present invention.

[0030] Figure 5 The device structure diagram is shown as follows: the method for preparing the semiconductor device of the present invention uses the photoresist layer and the second dielectric layer remaining at the bottom of the first opening pattern as etching stop layers, and removes the auxiliary dielectric layer based on the second opening pattern.

[0031] Figure 6 Shown is a schematic diagram of the device structure obtained after the method for preparing the semiconductor device of the present invention continues to use the photoresist layer as the etching barrier layer, removes the first dielectric layer and the second dielectric layer based on the first opening pattern and the second opening pattern, and stops when the bottom of the first opening pattern reveals the auxiliary dielectric layer.

[0032] Figure 7 It is a schematic diagram showing the device structure obtained after the step of removing the auxiliary dielectric layer at the bottom of the first opening pattern in the method for preparing the semiconductor device of the present invention.

[0033] Figure 8 The schematic diagram of the device structure shown is a method for preparing a semiconductor device of the present invention, wherein the method continues to use the photoresist layer as an etching barrier layer, removes the first dielectric layer, forms a first trench based on the first opening pattern that penetrates the second dielectric layer and the auxiliary dielectric layer and extends to the first dielectric layer, and forms a second trench based on the second opening pattern that penetrates the first dielectric layer from the bottom of the first trench and extends to the etching stop layer.

[0034] Figure 9 It is a schematic diagram showing the device structure obtained after the step of removing the etching stop layer at the bottom of the second trench in the method for preparing the semiconductor device of the present invention.

[0035] Figure 10 It is a schematic diagram of the device structure obtained after the step of removing the photoresist layer in the method for preparing the semiconductor device of the present invention.

[0036] Figure 11 It is a schematic diagram of the device structure obtained after the step of forming a conductive layer in the first trench and the second trench in the method for preparing a semiconductor device of the present invention.

[0037] Component number description

[0038] Steps S1 to S4

[0039] 1 base

[0040] 2 Etch stop layer

[0041] 3. First dielectric layer

[0042] 4 Auxiliary dielectric layer

[0043] 5 Second dielectric layer

[0044] 6, 6', 6", 6"' photoresist layer

[0045] 7 Photoresist opening pattern

[0046] 701 First Side Wall

[0047] 702 Second side wall

[0048] 801 First Opening Graphic

[0049] 802 Second opening pattern

[0050] 901 First Groove

[0051] 902 Second Groove

[0052] 10 Conductive layer DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] See also Figures 1 to 11 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0055] Example 1

[0056] This embodiment provides a method for preparing a semiconductor device. Figure 1 , shown as a process flow diagram of the method, comprising the following steps:

[0057] S1: providing a substrate, and forming an etch stop layer, a first dielectric layer, an auxiliary dielectric layer, and a second dielectric layer stacked sequentially from bottom to top on the substrate;

[0058] S2: Using the photoresist layer as an etching stopper, patterning the second dielectric layer to form a first opening pattern extending downward from the upper surface of the second dielectric layer, wherein the bottom of the first opening pattern has a second opening pattern that exposes a portion of the auxiliary dielectric layer;

[0059] S3: using the photoresist layer and the second dielectric layer remaining at the bottom of the first opening pattern as an etching stop layer, removing the auxiliary dielectric layer based on the second opening pattern to expose the first dielectric layer at the bottom of the second opening pattern;

[0060] S4: continuing to use the photoresist layer as an etching barrier layer, based on the first opening pattern and the second opening pattern, removing the first dielectric layer and the second dielectric layer until the auxiliary dielectric layer is exposed at the bottom of the first opening pattern;

[0061] S5: removing the auxiliary dielectric layer at the bottom of the first opening pattern;

[0062] S6: continuing to use the photoresist layer as an etching stop layer to remove the first dielectric layer, forming a first trench based on the first opening pattern that penetrates the second dielectric layer and the auxiliary dielectric layer and extends to the first dielectric layer, and forming a second trench based on the second opening pattern that penetrates the first dielectric layer from the bottom of the first trench and extends to the etch stop layer;

[0063] S7: removing the photoresist layer and the etching stop layer at the bottom of the second trench, and forming a conductive layer in the first trench and the second trench.

[0064] First see Figure 2 , performing the step S1: providing a substrate 1, and forming an etch stop layer 2, a first dielectric layer 3, an auxiliary dielectric layer 4 and a second dielectric layer 5 stacked in sequence from bottom to top on the substrate 1.

[0065] As an example, the base layer 1 includes but is not limited to one of a silicon substrate, a germanium substrate, a germanium silicon substrate, a silicon carbide substrate, and a III-V compound substrate, and the base layer 1 may be provided with a front layer structure, such as a shallow trench isolation structure, a polysilicon layer, a conductive metal layer, an interlayer dielectric layer, etc. The material of the auxiliary dielectric layer 4 is different from that of the first dielectric layer 3 and the second dielectric layer 5.

[0066] As an example, the material of the etch stop layer 2 includes one of silicon nitride and silicon oxynitride, the first dielectric layer 3 includes one or more of a borophosphosilicate glass layer, a phosphosilicate glass layer, a fluorosilicone glass layer, an undoped silica glass layer, an ethyl orthosilicate layer, a thermally oxidized silicon dioxide layer and a wet oxidized silicon dioxide layer, the material of the auxiliary dielectric layer 4 includes silicon carbide, and the second dielectric layer 5 includes one or more of a borophosphosilicate glass layer, a phosphosilicate glass layer, a fluorosilicone glass layer, an undoped silica glass layer, an ethyl orthosilicate layer, a thermally oxidized silicon dioxide layer and a wet oxidized silicon dioxide layer.

[0067] It should be pointed out that the etch stop layer 2, the first dielectric layer 3, the auxiliary dielectric layer 4 and the second dielectric layer 5 can also be made of other suitable materials, as long as the etch stop layer 2 and the first dielectric layer 3 have a large etching selectivity ratio under specific etching conditions, the first dielectric layer 3 and the auxiliary dielectric layer 4 have a large etching selectivity ratio under specific etching conditions, and the auxiliary dielectric layer 4 and the second dielectric layer 5 have a large etching selectivity ratio under specific etching conditions. The scope of protection of the present invention should not be excessively limited here.

[0068] See also Figure 3 and Figure 4 , perform step S2: use the photoresist layer 6 as an etching stop layer to pattern the second dielectric layer 5 to form a first opening pattern 801 extending downward from the upper surface of the second dielectric layer 5, and the bottom of the first opening pattern 801 has a second opening pattern 802 that exposes a portion of the auxiliary dielectric layer 4.

[0069] Specifically, in this embodiment, the second opening pattern with a portion of the auxiliary dielectric layer exposed is formed at the bottom of the first opening pattern by controlling the inclination of the sidewall of the photoresist opening pattern 7 .

[0070] Specifically, such as Figure 3 As shown, a photoresist layer 6 is formed on the second dielectric layer 5 by spin coating or other suitable methods, and the photoresist layer 6 is exposed based on a photoresist having an opening pattern, and then developed to obtain a photoresist opening pattern 7 in the photoresist layer 6. The photoresist opening pattern 7 has a first side wall 701 and a second side wall 702 that is asymmetric to the first side wall. The angle α between the first side wall 701 and the bottom surface of the photoresist opening is different from the angle β between the second side wall 702 and the bottom surface of the photoresist opening.

[0071] Specifically, the asymmetric photoresist opening pattern 7 is obtained by utilizing the inherent phase difference of the photoresist machine, such that the angle α between the first sidewall 701 and the bottom surface of the photoresist opening is not equal to the angle β between the second sidewall 702 and the bottom surface of the photoresist opening. For example, when the angle α between the first sidewall 701 and the bottom surface of the photoresist opening is 90°, the angle β between the second sidewall 702 and the bottom surface of the photoresist opening is greater than 90°. Of course, both α and β can also be obtuse angles.

[0072] Specifically, such as Figure 4As shown, the second dielectric layer 5 is patterned using anisotropic dry etching to form a first opening pattern 801 extending downward from the upper surface of the second dielectric layer 5. The bottom of the first opening pattern 801 has a second opening pattern 802 that exposes a portion of the auxiliary dielectric layer 4. The second opening pattern 802 is formed at the edge of the bottom of the first opening pattern 801, that is, one sidewall of the second opening pattern 802 is connected to the sidewall of the first opening pattern 801, and the other sidewall is spaced apart from the sidewall of the first opening pattern 801.

[0073] In this embodiment, the angle α between the first side wall 701 and the bottom surface of the photoresist opening is small, and the etching rate of the material close to the first side wall 701 is slow, while the angle β between the second side wall 702 and the bottom surface of the photoresist opening is large, and the etching rate of the material close to the second side wall 702 is fast, thereby obtaining a stepped opening pattern consisting of the first opening pattern 801 and the second opening pattern 802.

[0074] In this embodiment, dry etching is used to pattern the second dielectric layer 5, which is made of silicon oxide. The etching gas used includes a CF4 / C4F8 / Ar / O2 gas combination. The CF4 flow rate is adjustable within a range of 10-30 sccm, the O2 flow rate is adjustable within a range of 10-20 sccm, the C4F8 flow rate is adjustable within a range of 10-30 sccm, the Ar flow rate is adjustable within a range of 100-200 sccm, the process pressure is adjustable within a range of 50-70 mT, and the lower RF source power is adjustable within a range of 700-900 W. The CF4 / C4F8 / Ar / O2 gas combination has a much higher etching rate for the second dielectric layer 5 than for the auxiliary dielectric layer 4, resulting in little or no loss to the auxiliary dielectric layer 4.

[0075] See also Figure 5 , perform step S3: use the photoresist layer 6 and the second dielectric layer 5 remaining at the bottom of the first opening pattern 801 as etching stop layers, remove the auxiliary dielectric layer 4 based on the second opening pattern 802, so as to expose the first dielectric layer 3 at the bottom of the second opening pattern 802.

[0076] In this embodiment, the auxiliary dielectric layer 4 made of silicon carbide is dry-etched in this step, and the etching gas used includes an SF6 / O2 gas combination. This gas combination has a much higher etching rate for the auxiliary dielectric layer 4 than for the second dielectric layer 5 and the first dielectric layer 3, resulting in little or no loss to the second dielectric layer 5 and the first dielectric layer 3. As a result, when the auxiliary dielectric layer 4 exposed by the second opening pattern 802 is dry-etched, the second dielectric layer 5 remains at the bottom of the first opening pattern 801. In this step, a portion of the thickness of the photoresist layer 6 is also removed to obtain a photoresist layer 6'.

[0077] See also Figure 6 , execute the step S4: continue to use the photoresist layer 6' as the etching stop layer, based on the first opening pattern 801 and the second opening pattern 802, remove the first dielectric layer 3 and the second dielectric layer 5 until the bottom of the first opening pattern 801 exposes the auxiliary dielectric layer 4 and stops.

[0078] In this embodiment, for the second dielectric layer 5 and the first dielectric layer 3 made of silicon oxide material, dry etching is adopted in this step, and the etching gas adopted includes CF4 / CHF3 / Ar, CF4 / CHF3 / Ar / O2, C4F8 / O2 / Ar, C4F8 / O2 / CO / Ar, C4F6 / O2 / Ar, C4F6 / O2 / CO / Ar, C5F8 / O2 / Ar, C5F8 / O2 / CO / Ar or other suitable gas combinations. The etching rate of this gas combination on the first dielectric layer 3 and the second dielectric layer 5 is much higher than the etching rate on the auxiliary dielectric layer 4, so that there is almost no loss or little loss on the auxiliary dielectric layer 4.

[0079] See also Figure 7 , executing step S5: removing the auxiliary dielectric layer 4 at the bottom of the first opening pattern 801 until the first dielectric layer 3 is exposed.

[0080] In this embodiment, the auxiliary dielectric layer 4 made of silicon carbide is dry-etched in this step, and the etching gas used includes an SF6 / O2 gas combination. This gas combination has a much higher etching rate for the auxiliary dielectric layer 4 than for the first dielectric layer 3, resulting in little or no loss to the first dielectric layer 3. In this step, a portion of the thickness of the photoresist layer 6' is also removed to obtain a photoresist layer 6".

[0081] See also Figure 8, executing step S6: continuing to use the photoresist layer 6″ as an etching stop layer, removing the first dielectric layer 3, forming a first trench 901 based on the first opening pattern 801, penetrating the second dielectric layer 5 and the auxiliary dielectric layer 4 and extending to the first dielectric layer 3, and forming a second trench 902 based on the second opening pattern 802, penetrating the first dielectric layer 3 from the bottom of the first trench 901 and extending to the etch stop layer 2.

[0082] In this embodiment, for the first dielectric layer 3 of silicon oxide material, dry etching is adopted in this step, and the etching gas adopted includes CF4 / CHF3 / Ar, CF4 / CHF3 / Ar / O2, C4F8 / O2 / Ar, C4F8 / O2 / CO / Ar, C4F6 / O2 / Ar, C4F6 / O2 / CO / Ar, C5F8 / O2 / Ar, C5F8 / O2 / CO / Ar or other suitable gas combinations. The etching rate of the first dielectric layer 3 by this gas combination is much higher than the etching rate of the etch stop layer 2, so that there is almost no loss or little loss to the etch stop layer 2.

[0083] See also Figures 9 to 11 , executing S7: removing the photoresist layer 6 ″ and the etching stop layer 2 at the bottom of the second trench 902 , and forming a conductive layer 10 in the first trench 901 and the second trench 902 .

[0084] Specifically, such as Figure 9 As shown, the etching stop layer 2 at the bottom of the second trench 902 is first removed. At the same time, a portion of the thickness of the photoresist layer 6 ″ is also removed to obtain a photoresist layer 6 ′″.

[0085] In this embodiment, the etch stop layer 2 made of silicon nitride is dry-etched, and the etching gas used includes CHF3 / AR / O2, CH2F2 / AR / O2, CH3F / AR / O2 or other suitable gas combinations. The etching rate of the etch stop layer 2 by this gas combination is much higher than the etching rate of the first dielectric layer 3. Therefore, when the etch stop layer 2 at the bottom of the second groove 902 is completely removed, the bottom surface of the first groove 901 still remains in the first dielectric layer 3. At the same time, part of the thickness of the photoresist layer 6" will also be removed to obtain a photoresist layer 6'".

[0086] Specifically, the etching stop layer 2 at the bottom of the second trench 902 is removed, and then the photoresist layer 6'' is removed to obtain the following: Figure 10 The structure shown.

[0087] Specifically, such as Figure 11As shown, a conductive layer 10 is deposited in the first trench 901, in the second trench 902, and on the second dielectric layer 5, and is planarized using chemical mechanical polishing or other suitable methods until the top surface of the conductive layer 10 is flush with the top surface of the second dielectric layer 5. The material of the conductive layer includes at least one of Cu, W, Al, Ag, and Au, or other suitable conductive materials.

[0088] At this point, a semiconductor device is prepared. The method for preparing the semiconductor device of this embodiment utilizes the inherent phase difference of the photoresist machine to form an asymmetric photoresist opening morphology, and then combines it with a subsequent preset etching step to etch a stepped opening with asymmetric left and right depths in the dielectric layer, and form a conductive layer in the stepped opening to obtain a Damascus-like mosaic structure. The method for preparing the semiconductor device of this embodiment can achieve the preparation of a Damascus-like mosaic structure through only one coating and development, which not only simplifies the process flow, but also reduces production costs. It does not require expensive photolithography equipment support, and the equipment cost is lower. In addition, the method for preparing the semiconductor device of this embodiment is also widely applicable and is compatible with current CMOS / DMOS / BCD and other processes, and has a broader application prospect.

[0089] Example 2

[0090] This embodiment provides a semiconductor device. Figure 11 , which is a schematic structural diagram of the semiconductor device, includes a dielectric layer and a first trench 901 and a second trench 902 located in the dielectric layer, wherein the first trench 901 extends downward from the upper surface of the dielectric layer, and the trench depth of the first trench 901 is less than the thickness of the dielectric layer, and the second trench 902 extends downward from the bottom surface of the first trench and penetrates the dielectric layer, and a conductive layer 10 is provided in the first trench 901 and the second trench 902, wherein the semiconductor device is manufactured using the method for preparing a conductor device described in Example 1, and the dielectric layer includes an etch stop layer 2, a first dielectric layer 3, an auxiliary dielectric layer 4, and a second dielectric layer 5, the bottom of the first trench 901 may be located in the first dielectric layer 3, and the second trench 902 penetrates the first dielectric layer 3 and the etch stop layer 2.

[0091] Specifically, the second groove 902 is located at the edge of the first groove 901 , that is, one side wall of the second groove 90 is connected to the side wall of the first groove 901 , and the other side wall is spaced apart from the side wall of the first groove 901 .

[0092] As an example, the groove depth of the first groove 901 is greater than the groove depth of the second groove 902. The groove depth of the first groove 901 is the distance from the groove opening of the first groove 901 to the groove bottom of the first groove 901, and the groove depth of the second groove 902 is the distance from the groove bottom of the first groove 901 to the groove bottom of the second groove 902.

[0093] As an example, the conductive layer 10 can be used as a conductive interconnection layer of a semiconductor device, wherein the material of the conductive layer includes at least one of Cu, W, Al, Ag and Au, the critical dimension of the portion of the conductive layer 10 located in the first groove 901 is larger than the critical dimension of the portion located in the second groove 902, and the bottom of the second groove 902 exposes the substrate. The portion of the conductive layer 10 located in the first groove 901 can be used as a wire layer of the conductive interconnection layer, and the portion of the conductive layer 10 located in the second groove 902 can be used as a through-hole layer of the conductive interconnection layer.

[0094] In summary, the semiconductor device and preparation method thereof of the present invention utilize the inherent phase difference of the photoresist machine to form an asymmetric photoresist opening morphology, and then match it with a subsequent preset etching menu to etch a stepped opening with asymmetric left and right depths in the dielectric layer. Based on the left and right depth differences and through a reasonable combination of dielectric film layers, the present invention can realize the preparation of a damask-like mosaic structure by only one coating and development, which not only simplifies the process flow, but also reduces production costs, does not require expensive photolithography equipment support, and has lower equipment costs. The present invention has a wide range of applicability, is compatible with current CMOS / DMOS / BCD and other processes, and has a wider application prospect. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, and forming an etch stop layer, a first dielectric layer, an auxiliary dielectric layer, and a second dielectric layer stacked sequentially from bottom to top on the substrate; The second dielectric layer is patterned using the photoresist layer as an etching stop layer to form a first opening pattern extending downward from the upper surface of the second dielectric layer, wherein the bottom of the first opening pattern has a second opening pattern that exposes a portion of the auxiliary dielectric layer, wherein the photoresist layer has a photoresist opening pattern, and the second opening pattern that exposes a portion of the auxiliary dielectric layer is formed at the bottom of the first opening pattern by controlling the inclination of the sidewalls of the photoresist opening pattern; Using the photoresist layer and the second dielectric layer remaining at the bottom of the first opening pattern as an etching stop layer, removing the auxiliary dielectric layer based on the second opening pattern to expose the first dielectric layer at the bottom of the second opening pattern; Continuing to use the photoresist layer as an etching barrier layer, based on the first opening pattern and the second opening pattern, to remove the first dielectric layer and the second dielectric layer until the bottom of the first opening pattern exposes the auxiliary dielectric layer; removing the auxiliary dielectric layer at the bottom of the first opening pattern; Continuing to use the photoresist layer as an etch stop layer, removing the first dielectric layer, forming a first trench based on the first opening pattern that penetrates the second dielectric layer and the auxiliary dielectric layer and extends to the first dielectric layer, and forming a second trench based on the second opening pattern that penetrates the first dielectric layer from the bottom of the first trench and extends to the etch stop layer; The photoresist layer and the etch stop layer at the bottom of the second trench are removed, and a conductive layer is formed in the first trench and the second trench.

2. The method for preparing a semiconductor device according to claim 1, wherein: The second dielectric layer is patterned using the photoresist layer as an etching stop layer to form a first opening pattern extending downward from the upper surface of the second dielectric layer, wherein the bottom of the first opening pattern has a second opening pattern that exposes a portion of the auxiliary dielectric layer, and further comprises: A photoresist opening pattern is prepared in the photoresist layer by utilizing the inherent phase difference of the photolithography machine. The photoresist opening pattern has a first side wall and a second side wall that is asymmetric to the first side wall. The angle between the first side wall and the bottom surface of the photoresist opening is different from the angle between the second side wall and the bottom surface of the photoresist opening.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The first dielectric layer includes one or more of a borophosphosilicate glass layer, a phosphosilicate glass layer, a fluorosilicone glass layer, an undoped silica glass layer, an ethyl orthosilicate layer, a thermally oxidized silicon dioxide layer, and a wet oxidized silicon dioxide layer; the material of the auxiliary dielectric layer includes silicon carbide; the second dielectric layer includes one or more of a borophosphosilicate glass layer, a phosphosilicate glass layer, a fluorosilicone glass layer, an undoped silica glass layer, an ethyl orthosilicate layer, a thermally oxidized silicon dioxide layer, and a wet oxidized silicon dioxide layer; the material of the etch stop layer includes one of silicon nitride and silicon oxynitride.

4. The method for preparing a semiconductor device according to claim 1 or 3, wherein: The method further comprises removing the auxiliary dielectric layer based on the second opening pattern using the photoresist layer and the second dielectric layer remaining at the bottom of the first opening pattern as an etching stop layer to expose the first dielectric layer at the bottom of the second opening pattern, and removing the auxiliary dielectric layer by dry etching, wherein the dry etching gas used has a higher etching rate for the auxiliary dielectric layer than for the second dielectric layer, and when the auxiliary dielectric layer exposed by the second opening pattern is completely dry-etched, the second dielectric layer still remains at the bottom of the first opening pattern.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The dry etching gas at least contains SF6 and O2.

6. The method for manufacturing a semiconductor device according to claim 1 or 3, wherein: The method further comprises: removing the first dielectric layer and the second dielectric layer by dry etching, wherein the etching rate of the dry etching gas used for the first dielectric layer and the second dielectric layer is greater than the etching rate of the auxiliary dielectric layer, and the thickness of the first dielectric layer removed based on the second opening pattern is less than the thickness of the first dielectric layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The dry etching gas includes one or more of CF4 / CHF3 / Ar, CF4 / CHF3 / Ar / O2, C4F8 / O2 / Ar, C4F8 / O2 / CO / Ar, C4F6 / O2 / Ar, C4F6 / O2 / CO / Ar, C5F8 / O2 / Ar and C5F8 / O2 / CO / Ar gas combinations.

8. A semiconductor device, characterized in that: The semiconductor device is manufactured using the method for preparing a conductor device according to any one of claims 1 to 7, and includes a dielectric layer and a first trench and a second trench located in the dielectric layer. The dielectric layer includes the etch stop layer, the first dielectric layer, the auxiliary dielectric layer, and the second dielectric layer. The first trench extends downward from the upper surface of the dielectric layer, and the trench depth of the first trench is less than the thickness of the dielectric layer. The second trench extends downward from the bottom surface of the first trench and penetrates the dielectric layer. A conductive layer is provided in the first trench and the second trench.

9. The semiconductor device according to claim 8, wherein: The second groove is located at an edge of a bottom of the first groove.

10. The semiconductor device according to claim 8, wherein: The material of the conductive layer includes at least one of Cu, W, Al, Ag and Au, and the conductive layer serves as a conductive interconnection layer.

11. The semiconductor device according to claim 8, wherein: The groove depth of the first groove is greater than the groove depth of the second groove.

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