A method for manufacturing a GaN CMOS inverter using a selective epitaxial process

Abstract

The present invention belongs to the field of power semiconductor technology, and specifically relates to a method for manufacturing a GaN CMOS inverter using a selective epitaxial process. In this manufacturing method, a dielectric is first grown on a GaN cap layer and a dielectric hard mask is formed by combining photolithography and etching processes. On this structure, a p-GaN layer and a SiN layer are selectively grown epitaxially. x The passivation layer is then removed, and the dielectric hard mask is finally removed. After the ohmic source-drain contacts between the P-FET and N-FET are established, dielectric material is deposited to form the recessed MIS gate of the enhancement-mode P-FET. Simultaneously, the selectively epitaxially grown p-GaN layer also serves as the p-GaN gate of the N-FET, achieving enhancement mode. Finally, metal interconnects are established between the N-FET and P-FET electrodes to form a GaN CMOS inverter. Compared to achieving enhancement-mode technology by partially or fully etching the p-GaN layer, this method reduces lattice damage introduced by etching the p-GaN layer, improves interface quality, and minimizes the reduction in channel electron and hole mobility, without requiring precise etching control.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and in particular relates to a method for manufacturing a GaN CMOS inverter using a selective epitaxial process. Background Art

[0002] CMOS digital circuits, due to their advantages such as low power consumption, high input impedance, and simple structure, hold significant application value in very large-scale integrated circuits (VLSI). Furthermore, their increasing application in high-frequency applications is driving higher demands on the high-frequency, miniaturization, and integration of CMOS digital circuits and modules. GaN, as a third-generation semiconductor, offers excellent high-frequency performance. Currently, companies like Navitas are integrating GaN power devices with Si-based logic control components and pre-drivers, a strategy that somewhat limits GaN's high-frequency performance. All-GaN CMOS digital circuits can meet these high-frequency and low-power requirements while avoiding the parasitic effects of the integration process. However, due to surface damage caused by etching during GaN-based device fabrication, the drift mobility of holes in p-GaN is very low, limiting the high-frequency and low-power advantages. Therefore, research on all-GaN CMOS not only provides theoretical guidance for improving P / N channel performance but also leverages the excellent properties of GaN to provide technical support for the multifunctionality, miniaturization, and efficiency of information systems. Summary of the Invention

[0003] Based on the requirements of high-frequency and miniaturized GaN-based digital devices, this paper proposes a method for manufacturing a GaN CMOS inverter using a selective epitaxial process. First, a dielectric is grown on the GaN cap layer and a dielectric hard mask is formed by combining photolithography and etching processes. Then, a p-GaN layer and an in-situ SiN layer are grown in sequence by metal organic chemical vapor deposition (MOCVD). x After removing the passivation layer and removing the dielectric hard mask, two discrete devices, GaN N-FET and GaN P-FET, are defined through mesa isolation. Then, dielectric is deposited to form the groove-type MIS gate of the enhancement-mode P-FET. At the same time, the p-GaN layer grown by selective epitaxy also serves as the p-GaN gate of the N-FET to achieve enhancement mode. The source, drain and gate electrodes of the two devices are gradually defined, and finally the gate and drain electrodes of the two devices are interconnected to form a GaN CMOS inverter. At the same time, the present invention uses a selective epitaxial method to grow the p-GaN layer and the in-situ SiN x The passivation layer reduces the lattice damage introduced by etching, so that the mobility of 2DEG and 2DHG is not affected, and the interface state density is reduced.

[0004] In order to achieve the above-mentioned object of the invention, the technical solution of the present invention is as follows:

[0005] A method for manufacturing a GaN CMOS inverter using a selective epitaxial process, characterized by comprising the following steps:

[0006] Step 1: preparing a substrate, which includes a substrate 1, a GaN buffer layer 2, a GaN channel layer 3, an AlGaN barrier layer 4, and a GaN cap layer 5 stacked from bottom to top;

[0007] Step 2: Using a chemical vapor deposition (CVD) process, a dielectric layer is deposited on the GaN cap layer 5. Combining photolithography and etching techniques, the resulting dielectric hard mask 6 is continuously distributed along the lateral direction of the device, and each section of the dielectric hard mask 6 has a different length.

[0008] Step 3: Using the metal organic chemical vapor deposition (MOCVD) process, a p-GaN layer 7 and a SiN layer are formed on the upper surface of the GaN cap layer 5 between the dielectric hard mask 6. x Passivation layer 8, SiN x The height of the passivation layer 8 is lower than the dielectric hard mask 6;

[0009] Step 4: Etch and remove the dielectric hard mask 6 to obtain the first p-GaN layer 71, the second p-GaN layer 72, the third p-GaN layer 73 and the first SiN layer 74 formed by selective epitaxy. x Passivation layer 81, second SiN x Passivation layer 82, third SiN x Passivation layer 83; wherein the first SiN x The passivation layer 81 is located on the upper surface of the first p-GaN layer 71, and the second SiN x The passivation layer 82 is located on the upper surface of the second p-GaN layer 72, and the third SiN x The passivation layer 83 is located on the upper surface of the third p-GaN layer 73 , and the second p-GaN layer 72 is located between the first p-GaN layer 71 and the third p-GaN layer 73 ;

[0010] Step 5: Etching a GaN cap layer 5, an AlGaN barrier layer 4, and a portion of the GaN channel layer 3 on a side of the second p-GaN layer 72 away from the first p-GaN layer 71 and at both ends of the GaN CMOS inverter, dividing the GaN cap layer 5 and the AlGaN barrier layer 4 into a first GaN cap layer 51, a second GaN cap layer 52, a first AlGaN barrier layer 41, and a second AlGaN barrier layer 42; wherein the first GaN cap layer 51 is located on the upper surface of the first AlGaN barrier layer 41 to form a first heterojunction, and the first p-GaN layer 71 and the second p-GaN layer 72 are located at both ends of the upper surface of the first GaN cap layer 51; the second GaN cap layer 52 is located on the upper surface of the second AlGaN barrier layer 42 to form a second heterojunction, and the third p-GaN layer 73 is located in the middle of the upper surface of the second GaN cap layer 52;

[0011] Step 6: Depositing a material for forming ohmic contacts of the N-FET source 11 and the N-FET drain 12 at both ends of the upper surface of the second heterojunction, using a lift-off process and performing annealing to form the N-FET source 11 and the N-FET drain 12, wherein the N-FET source 11 is located at one end close to the first heterojunction;

[0012] Step 7: Etch the first SiN x The side of the passivation layer 81 away from the second p-GaN layer 72 is adjacent to the second SiN layer. x The side of the passivation layer 82 away from the first p-GaN layer 71 reveals holes required for the P-FET source 9 and the P-FET drain 10 on the surfaces of the first p-GaN layer 71 and the second p-GaN layer 72 ;

[0013] Step 8: Deposit materials for forming ohmic contacts of the P-FET source 9 and the P-FET drain 10, and use a lift-off process and annealing to form the P-FET source 9 and the P-FET drain 10 at the openings on the surfaces of the first p-GaN layer 71 and the second p-GaN layer 72, respectively.

[0014] Step 9: Using low temperature dielectric deposition technology to deposit the first SiN between the P-FET source 9 and the P-FET drain 10 x The upper surface of the passivation layer 81 and the second SiN x The gate dielectric 13 is deposited on the upper surface of the passivation layer 82 and the upper surface of the first GaN cap layer 51, and the third SiN x passivation layer 83;

[0015] Step 10: Depositing a Schottky metal required to form the P-FET gate 14 on the gate dielectric 13, and depositing a Schottky metal required to form the N-FET gate 15 on the third p-GaN layer 73, and forming the P-FET gate 14 and the N-FET gate 15 by a lift-off process;

[0016] Step 11: depositing a passivation layer 16 in the groove between the first heterojunction and the second heterojunction, and depositing a first metal 17 on the passivation layer 16, with both ends of the first metal 17 extending to a portion of the upper surface of the P-FET drain 10 and the upper surface of the N-FET drain 12 respectively;

[0017] Step 12: Deposit a passivation layer 18 to cover the entire device surface, and deposit a second metal 19 on the passivation layer 18. The two ends of the second metal 19 are respectively connected to a portion of the upper surface of the P-FET gate 14 and the upper surface between the N-FET gates 15.

[0018] As a preferred method, the process used for the gate dielectric 13 includes but is not limited to atomic layer deposition (ALD) and pulsed laser deposition (PLD), and the materials used include but are not limited to SiN x , Al2O3, HfO2 and their combinations.

[0019] The beneficial effect of the present invention is that a dielectric is first grown on the GaN cap layer and a dielectric hard mask is formed by combining photolithography and etching processes, and then a p-GaN layer and a SiN layer are selectively grown on this structure. x The passivation layer is then removed, and finally the dielectric hard mask is removed to form the recessed MIS gate of the P-FET. Simultaneously, the selectively epitaxially grown p-GaN layer also serves as the p-GaN gate of the N-FET, achieving enhancement mode. Compared to methods that achieve enhancement mode by partially or fully etching the p-GaN layer, this invention reduces the lattice damage introduced by etching the p-GaN layer, improves the quality of the gate interface, and prevents a decrease in channel electron and hole mobility. There is no need to control etching precision, and the selectively epitaxially grown p-GaN layer simultaneously serves as the drift region of the enhancement-mode P-FET and the p-GaN gate of the N-FET, achieving enhancement mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic diagram of the two-dimensional structure of Example 1;

[0021] Figure 2 It is a process flow chart of Example 1;

[0022] Figure 3 The specific process steps of Example 1 are as follows:

[0023] (a) is a schematic diagram of the device structure after material preparation in step 1 of the process flow of Example 1;

[0024] (b) is a schematic diagram of the device structure after depositing and etching to form a dielectric hard mask in step 2 of the process flow of Example 1;

[0025] (c) is a schematic diagram of the device structure after the p-GaN layer and the passivation layer are regrown in step 3 of the process flow of Example 1;

[0026] (d) is a schematic diagram of the device structure after the dielectric hard mask is removed in step 4 of the process flow of Example 1;

[0027] (e) is a schematic diagram of the device structure after etching to form mesa isolation in step 5 of the process flow of Example 1 to isolate the N-FET from the P-FET and the adjacent devices;

[0028] (f) is a schematic diagram of the device structure after forming the source and drain electrodes of the N-FET in step 6 of the process flow of Example 1;

[0029] (g) is a schematic diagram of the device structure after etching the passivation layer to form the P-FET source and drain holes in step 7 of the process flow of Example 1;

[0030] (h) is a schematic diagram of the device structure after forming the source and drain electrodes of the P-FET in step 8 of the process flow of Example 1;

[0031] (i) is a schematic diagram of the device structure after depositing the P-FET gate dielectric and etching the passivation layer on the N-FET gate in step 9 of the process flow of Example 1;

[0032] (j) is a schematic diagram of the device structure after forming the P-FET and N-FET gates in step 10 of the process flow of Example 1;

[0033] (k) is a schematic diagram of the device structure after the drain electrodes of the P-FET and the N-FET are interconnected in step 11 of the process flow of Example 1;

[0034] (l) is a schematic diagram of the device structure after the gates of the P-FET and the N-FET are interconnected in step 11 of the process flow of Example 1. DETAILED DESCRIPTION

[0035] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments:

[0036] Example 1:

[0037] Step 1: preparing a substrate, which includes a substrate 1, a GaN buffer layer 2, a GaN channel layer 3, an AlGaN barrier layer 4, and a GaN cap layer 5 stacked from bottom to top;

[0038] Step 2: Using a chemical vapor deposition (CVD) process, a dielectric layer is deposited on the GaN cap layer 5. Combining photolithography and etching techniques, the resulting dielectric hard mask 6 is continuously distributed along the lateral direction of the device, and each section of the dielectric hard mask 6 has a different length.

[0039] Step 3: Using the metal organic chemical vapor deposition (MOCVD) process, a p-GaN layer 7 and a SiN layer are formed on the upper surface of the GaN cap layer 5 between the dielectric hard mask 6. x Passivation layer 8, SiN x The height of the passivation layer 8 is lower than the dielectric hard mask 6;

[0040] Step 4: Etch and remove the dielectric hard mask 6 to obtain the first p-GaN layer 71, the second p-GaN layer 72, the third p-GaN layer 73 and the first SiN layer 74 formed by selective epitaxy. x Passivation layer 81, second SiN x Passivation layer 82, third SiN x Passivation layer 83; wherein the first SiN x The passivation layer 81 is located on the upper surface of the first p-GaN layer 71, and the second SiN x The passivation layer 82 is located on the upper surface of the second p-GaN layer 72, and the third SiN x The passivation layer 83 is located on the upper surface of the third p-GaN layer 73 , and the second p-GaN layer 72 is located between the first p-GaN layer 71 and the third p-GaN layer 73 ;

[0041] Step 5: Etching a GaN cap layer 5, an AlGaN barrier layer 4, and a portion of the GaN channel layer 3 on a side of the second p-GaN layer 72 away from the first p-GaN layer 71 and at both ends of the GaN CMOS inverter, dividing the GaN cap layer 5 and the AlGaN barrier layer 4 into a first GaN cap layer 51, a second GaN cap layer 52, a first AlGaN barrier layer 41, and a second AlGaN barrier layer 42; wherein the first GaN cap layer 51 is located on the upper surface of the first AlGaN barrier layer 41 to form a first heterojunction, and the first p-GaN layer 71 and the second p-GaN layer 72 are located at both ends of the upper surface of the first GaN cap layer 51; the second GaN cap layer 52 is located on the upper surface of the second AlGaN barrier layer 42 to form a second heterojunction, and the third p-GaN layer 73 is located in the middle of the upper surface of the second GaN cap layer 52;

[0042] Step 6: Depositing a material for forming ohmic contacts of the N-FET source 11 and the N-FET drain 12 at both ends of the upper surface of the second heterojunction, using a lift-off process and performing annealing to form the N-FET source 11 and the N-FET drain 12, wherein the N-FET source 11 is located at one end close to the first heterojunction;

[0043] Step 7: Etch the first SiN x The side of the passivation layer 81 away from the second p-GaN layer 72 is adjacent to the second SiN layer. xThe side of the passivation layer 82 away from the first p-GaN layer 71 reveals holes required for the P-FET source 9 and the P-FET drain 10 on the surfaces of the first p-GaN layer 71 and the second p-GaN layer 72 ;

[0044] Step 8: Deposit materials for forming ohmic contacts of the P-FET source 9 and the P-FET drain 10, and use a lift-off process and annealing to form the P-FET source 9 and the P-FET drain 10 at the openings on the surfaces of the first p-GaN layer 71 and the second p-GaN layer 72, respectively.

[0045] Step 9: Using low temperature dielectric deposition technology to deposit the first SiN between the P-FET source 9 and the P-FET drain 10 x The upper surface of the passivation layer 81 and the second SiN x The gate dielectric 13 is deposited on the upper surface of the passivation layer 82 and the upper surface of the first GaN cap layer 51, and the third SiN x passivation layer 83;

[0046] Step 10: Depositing a Schottky metal required to form the P-FET gate 14 on the gate dielectric 13, and depositing a Schottky metal required to form the N-FET gate 15 on the third p-GaN layer 73, and forming the P-FET gate 14 and the N-FET gate 15 by a lift-off process;

[0047] Step 11: depositing a passivation layer 16 in the groove between the first heterojunction and the second heterojunction, and depositing a first metal 17 on the passivation layer 16, with both ends of the first metal 17 extending to a portion of the upper surface of the P-FET drain 10 and the upper surface of the N-FET drain 12 respectively;

[0048] Step 12: Deposit a passivation layer 18 to cover the entire device surface, and deposit a second metal 19 on the passivation layer 18. The two ends of the second metal 19 are respectively connected to a portion of the upper surface of the P-FET gate 14 and the upper surface between the N-FET gates 15.

[0049] The GaN CMOS device prepared by the above manufacturing method firstly grows a dielectric on the GaN cap layer and combines the photolithography and etching process to form a dielectric hard mask, and then selectively grows a p-GaN layer and a SiN layer on this structure. xThe passivation layer is then removed, and finally the dielectric hard mask is removed. After the ohmic source-drain contacts between the P-FET and N-FET are completed, dielectric is deposited to form the recessed MIS gate of the enhancement-mode P-FET. Simultaneously, the selectively epitaxially grown p-GaN layer also serves as the p-GaN gate of the N-FET, achieving enhancement mode. Finally, after metal interconnection between the electrodes of the N-FET and P-FET, a GaN CMOS inverter is formed. Compared to achieving enhancement-mode technology by partially or fully etching the p-GaN layer, this invention reduces lattice damage introduced by etching the p-GaN layer, improves interface quality, and reduces the reduction in channel electron and hole mobility, without requiring precise etching control.

Claims

1. A method for manufacturing a GaN CMOS inverter using a selective epitaxial process, characterized in that: The following steps are involved: Step 1: preparing a substrate, wherein the substrate comprises a substrate (1), a GaN buffer layer (2), a GaN channel layer (3), an AlGaN barrier layer (4) and a GaN cap layer (5) stacked from bottom to top; Step 2: using a chemical vapor deposition (CVD) process to deposit a dielectric layer on the GaN cap layer (5), and combining photolithography and etching techniques to form a dielectric hard mask (6) that is continuously distributed along the lateral direction of the device, and each section of the dielectric hard mask (6) has a different length; Step 3: Using metal organic chemical vapor deposition MOCVD process, a p-GaN layer (7) and a SiN layer are formed on the upper surface of the GaN cap layer (5) between the dielectric hard mask (6). x Passivation layer (8), SiN x The height of the passivation layer (8) is lower than that of the dielectric hard mask (6); Step 4: Etching and removing the dielectric hard mask (6) to obtain a first p-GaN layer (71), a second p-GaN layer (72), a third p-GaN layer (73) and a first SiN layer generated by selective epitaxy. x Passivation layer (81), second SiN x Passivation layer (82), third SiN x Passivation layer (83); wherein the first SiN x The passivation layer (81) is located on the upper surface of the first p-GaN layer (71), and the second SiN x The passivation layer (82) is located on the upper surface of the second p-GaN layer (72), and the third SiN x The passivation layer (83) is located on the upper surface of the third p-GaN layer (73), and the second p-GaN layer (72) is located between the first p-GaN layer (71) and the third p-GaN layer (73); Step 5: On the side of the second p-GaN layer (72) away from the first p-GaN layer (71), a GaN A GaN cap layer (5), an AlGaN barrier layer (4), and a portion of a GaN channel layer (3) are etched at both ends of the CMOS inverter, and the GaN cap layer (5) and the AlGaN barrier layer (4) are divided into a first GaN cap layer (51), a second GaN cap layer (52), a first AlGaN barrier layer (41), and a second AlGaN barrier layer (42); wherein the first GaN cap layer (51) is located on the upper surface of the first AlGaN barrier layer (41) to form a first heterojunction, and the first p-GaN layer (71) and the second p-GaN layer (72) are located at both ends of the upper surface of the first GaN cap layer (51); the second GaN cap layer (52) is located on the upper surface of the second AlGaN barrier layer (42) to form a second heterojunction, and the third p-GaN layer (73) is located in the middle of the upper surface of the second GaN cap layer (52); Step 6: depositing a material for forming an N-FET source (11) and an N-FET drain (12) ohmic contact at both ends of the upper surface of the second heterojunction, adopting a lift-off process and performing annealing to form the N-FET source (11) and the N-FET drain (12), wherein the N-FET source (11) is located at one end close to the first heterojunction; Step 7: Etch the first SiN x The side of the passivation layer (81) away from the second p-GaN layer (72) is adjacent to the second SiN layer. x The passivation layer (82) is located on a side away from the first p-GaN layer (71), and holes required for the P-FET source (9) and the P-FET drain (10) are exposed on the surfaces of the first p-GaN layer (71) and the second p-GaN layer (72); Step 8: depositing a material for forming an ohmic contact of a P-FET source (9) and a P-FET drain (10), using a lift-off process and performing annealing to form a P-FET source (9) and a P-FET drain (10) at the openings on the surfaces of the first p-GaN layer (71) and the second p-GaN layer (72); Step 9: Using low temperature dielectric deposition technology to deposit the first SiN between the P-FET source (9) and the P-FET drain (10) x The upper surface of the passivation layer (81), the second SiN x A gate dielectric (13) is deposited on the upper surface of the passivation layer (82) and the upper surface of the first GaN cap layer (51), and the third SiN is etched away at the same time. x a passivation layer (83); Step 10: depositing a Schottky metal required to form a P-FET gate (14) on the gate dielectric (13), depositing a Schottky metal required to form an N-FET gate (15) on the third p-GaN layer (73), and forming the P-FET gate (14) and the N-FET gate (15) by a lift-off process; Step 11: depositing a passivation layer (16) in the groove between the first heterojunction and the second heterojunction, and depositing a first metal (17) on the passivation layer (16), with both ends of the first metal (17) extending to a portion of the upper surface of the P-FET drain (10) and the upper surface of the N-FET drain (12); Step 12: Deposit a passivation layer (18) to cover the entire device surface, and deposit a second metal (19) on the passivation layer (18). The two ends of the second metal (19) are respectively connected to a portion of the upper surface of the P-FET gate (14) and the upper surface between the N-FET gate (15).

2. The method for manufacturing a GaN CMOS inverter using a selective epitaxial process according to claim 1, wherein: The gate dielectric (13) is made of an atomic layer deposition (ALD) process or a pulsed laser deposition (PLD) process, and the material used is SiN. x , Al2O3, HfO2 or a combination thereof.

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