Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes: sub-pixels arranged in a first direction to form sub-pixel rows and arranged in a second direction to form sub-pixel columns; the sub-pixel rows include a first sub-pixel row and a second sub-pixel row alternately arranged in the second direction, and the sub-pixel columns include adjacent first sub-pixel columns and second sub-pixel columns; the sub-pixels located in the first sub-pixel row are connected to a first signal line closest to the first edge of the sub-pixel; the sub-pixels located in the second sub-pixel row are connected to a first signal line closest to the second edge of the sub-pixel; a second signal line is located between the first sub-pixel column and the second sub-pixel column and is on the same layer as the first signal line; within a preset voltage range, the data writing voltages of at least one first sub-pixel and at least one second sub-pixel are equal, avoiding display differences between the first sub-pixel and the second sub-pixel and improving the display effect.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and more particularly, to a display panel and a display device. Background Art

[0002] With the continuous development of display technologies, people not only have higher and higher requirements for the display effect of display panels or display devices, but also pay more and more attention to the cost performance of display panels or display devices. Therefore, while ensuring the display effect, it is also necessary to reduce the cost of display panels.

[0003] In the prior art, a display panel with a zig-zag structure can achieve the effect of dot inversion in a column inversion manner, thereby reducing power consumption when the display panel is displaying, so as to improve the display effect. However, a display panel with a zig-zag structure cannot reduce costs by reducing the manufacturing process, because reducing the manufacturing process during the process of manufacturing a display panel with a zig-zag structure will cause a large number of wirings to be located in the same film layer, increasing the wiring area, and the active layer of some sub-pixels will form a capacitor with the wiring, affecting the data transmission of these sub-pixels and causing display differences.

[0004] Therefore, there is an urgent need for a display panel design that can avoid differences in sub-pixel data transmission. Summary of the Invention

[0005] In view of this, the present invention provides a display panel and a display device to avoid differences in data transmission of sub-pixels.

[0006] On the one hand, the present invention provides a display panel, including:

[0007] Sub-pixels arranged in an array, the sub-pixels include a first edge and a second edge oppositely arranged along a first direction, the sub-pixels are arranged along the first direction to form sub-pixel rows, the sub-pixels are arranged along a second direction to form sub-pixel columns, and the first direction intersects the second direction; the sub-pixel rows include first sub-pixel rows and second sub-pixel rows alternately arranged along the second direction, and the sub-pixel columns include adjacent first sub-pixel columns and second sub-pixel columns;

[0008] Also includes a substrate;

[0009] Multiple signal lines, located on one side of the substrate, the multiple signal lines include:

[0010] A plurality of first signal lines are arranged along the first direction and extend along the second direction. One sub-pixel column is provided between two adjacent first signal lines. The sub-pixels located in the first sub-pixel row are connected to the first signal line that is closest to the first edge of the sub-pixel along the first direction. The sub-pixels located in the second sub-pixel row are connected to the first signal line that is closest to the second edge of the sub-pixel along the first direction.

[0011] A second signal line extends along the second direction, is located between the first sub-pixel column and the second sub-pixel column, and is on the same layer as the first signal line.

[0012] The sub-pixel includes a first sub-pixel and a second sub-pixel. The first sub-pixel is located in the first sub-pixel column and in the second sub-pixel row. The second sub-pixel is located in the second sub-pixel column and in the first sub-pixel row.

[0013] The first signal line includes a first sub-signal line located between the first sub-pixel column and the second sub-pixel column. The orthographic projection of the active layer of at least one first sub-pixel on the substrate overlaps at least partially with the orthographic projection of the second signal line on the substrate, and the orthographic projection of the active layer of at least one second sub-pixel on the substrate overlaps at least partially with the orthographic projection of the second signal line on the substrate.

[0014] Within a preset voltage range, the data writing voltages of at least one first sub-pixel and at least one second sub-pixel are equal.

[0015] On the other hand, the present invention provides a display panel, including:

[0016] Sub-pixels arranged in an array. The sub-pixels include a first edge and a second edge that are oppositely arranged along the first direction. The sub-pixels are arranged along the first direction to form sub-pixel rows, and the sub-pixels are arranged along the second direction to form sub-pixel columns. The first direction intersects with the second direction. The sub-pixel rows include a first sub-pixel row and a second sub-pixel row that are alternately arranged along the second direction. The sub-pixel columns include adjacent first sub-pixel columns and second sub-pixel columns.

[0017] It further includes a substrate;

[0018] A plurality of signal lines are located on one side of the substrate. The plurality of signal lines include:

[0019] A plurality of first signal lines are arranged along the first direction and extend along the second direction. There is one sub-pixel column between two adjacent first signal lines. The sub-pixels in the first sub-pixel row are connected to the first signal line that is closest to the first edge of the sub-pixel along the first direction. The sub-pixels in the second sub-pixel row are connected to the first signal line that is closest to the second edge of the sub-pixel along the first direction.

[0020] A second signal line extends along the second direction, is located between the first sub-pixel column and the second sub-pixel column, and is partially on the same layer as the first signal line.

[0021] The sub-pixel includes a first sub-pixel and a second sub-pixel. The first sub-pixel is located in the first sub-pixel column and in the second sub-pixel row. The second sub-pixel is located in the second sub-pixel column and in the first sub-pixel row. The orthographic projection of the active layer of at least one first sub-pixel on the substrate does not overlap with the orthographic projection of the second signal line on the substrate, and the orthographic projection of the active layer of at least one second sub-pixel on the substrate does not overlap with the orthographic projection of the second signal line on the substrate. Within a preset voltage range, the data writing voltages of at least one first sub-pixel and at least one second sub-pixel are equal.

[0022] In another aspect, the present invention further provides a display device, including the display panel described in any one of the above.

[0023] Compared with the prior art, the display panel provided by the present invention at least achieves the following beneficial effects:

[0024] In the display panel provided by the present invention, a sub-pixel column is provided between two adjacent first signal lines; the sub-pixels located in the first sub-pixel row are connected to the first signal line closest to the first edge of the sub-pixel along the first direction; the sub-pixels located in the second sub-pixel row are connected to the first signal line closest to the second edge of the sub-pixel along the first direction, forming a display panel with a zig-zag structure to reduce power consumption and improve the display effect of the display panel; a second signal line extends along the second direction, is located between the first sub-pixel column and the second sub-pixel column, and is on the same layer as the first signal line; the sub-pixel includes a first sub-pixel and a second sub-pixel, the first sub-pixel is located in the first sub-pixel column and in the second sub-pixel row; the second sub-pixel is located in the second sub-pixel column and in the first sub-pixel row; the first signal line includes a first sub-signal line, the first sub-signal line is located between the first sub-pixel column and the second sub-pixel column, and the orthographic projection of the active layer of at least one first sub-pixel on the substrate overlaps at least partially with the orthographic projection of the second signal line on the substrate, and the orthographic projection of the active layer of at least one second sub-pixel on the substrate overlaps at least partially with the orthographic projection of the second signal line on the substrate; within a preset voltage range, the data writing voltages of at least one first sub-pixel and at least one second sub-pixel are equal. When the first sub-signal line is located between the first sub-pixel column and the second signal line, the orthographic projection of the active layer of the second sub-pixel on the substrate overlaps partially with the orthographic projection of the second signal line on the substrate, so a capacitor is formed between the active layer of the second sub-pixel and the second signal line, which will cause the data writing voltage of the second sub-pixel to decrease. By setting the orthographic projection of the active layer of the first sub-pixel on the substrate to overlap partially with the orthographic projection of the second signal line on the substrate, that is, extending the active layer of the first sub-pixel, a capacitor is formed between the active layer of the first sub-pixel and the second signal line, so that the data writing voltage of the first sub-pixel also decreases, realizing that within the preset voltage range, the data writing voltages of the first sub-pixel and the second sub-pixel are equal, avoiding display differences between the first sub-pixel and the second sub-pixel, and improving the display effect. Similarly, when the first sub-signal line is located between the second signal line and the second sub-pixel column, the orthographic projection of the active layer of the first sub-pixel on the substrate overlaps partially with the orthographic projection of the second signal line on the substrate, a capacitor is formed between the active layer of the first sub-pixel and the second signal line, resulting in a decrease in the data writing voltage of the first sub-pixel. By setting the orthographic projection of the active layer of the second sub-pixel on the substrate to overlap partially with the orthographic projection of the second signal line on the substrate, that is, extending the active layer of the second sub-pixel, a capacitor is formed between the active layer of the second sub-pixel and the second signal line, so that the data writing voltage of the second sub-pixel also decreases, realizing that within the preset voltage range, the data writing voltages of the first sub-pixel and the second sub-pixel are equal, avoiding display differences between the first sub-pixel and the second sub-pixel, and improving the display effect.

[0025] Of course, it is not necessary for any product implementing the present invention to simultaneously achieve all the above-mentioned technical effects.

[0026] Other features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0028] Figure 1 is a schematic structural diagram of a display panel provided by the present invention;

[0029] Figure 2 is Figure 1 a cross-sectional view taken along the line A-A' in

[0030] Figure 3 is another schematic structural diagram of a display panel provided by the present invention;

[0031] Figure 4 is yet another schematic structural diagram of a display panel provided by the present invention;

[0032] Figure 5 is yet another schematic structural diagram of a display panel provided by the present invention;

[0033] Figure 6 is yet another schematic structural diagram of a display panel provided by the present invention;

[0034] Figure 7 is yet another schematic structural diagram of a display panel provided by the present invention;

[0035] Figure 8 is yet another schematic structural diagram of a display panel provided by the present invention;

[0036] Figure 9 is Figure 8 a cross-sectional view taken along the line B-B' in

[0037] Figure 10 is yet another schematic structural diagram of a display panel provided by the present invention;

[0038] Figure 11 is Figure 10 a cross-sectional view taken along the line C-C' in

[0039] Figure 12 is yet another schematic structural diagram of a display panel provided by the present invention;

[0040] Figure 13 is Figure 12 a cross-sectional view taken along the line D-D' in

[0041] Figure 14 is yet another schematic structural diagram of a display panel provided by the present invention;

[0042] Figure 15 is Figure 14 The sectional view taken along the direction E - E’ in

[0043] Figure 16 Another schematic structural view of the display panel provided by the present invention;

[0044] Figure 17 Another schematic structural view of the display panel provided by the present invention;

[0045] Figure 18 A schematic structural view of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0046] Now, various exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that: unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention.

[0047] The following description of at least one exemplary embodiment is merely illustrative in nature and in no way serves as a limitation on the present invention or its application or use.

[0048] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be regarded as part of the specification.

[0049] In all examples shown and discussed herein, any specific values should be construed as merely exemplary and not as a limitation. Thus, other examples of exemplary embodiments may have different values.

[0050] It should be noted that: like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0051] Referring to Figure 1 、 Figure 2 、 Figure 3 and Figure 4 , Figure 1 A schematic structural view of a display panel provided by the present invention, Figure 2 is Figure 1 The sectional view taken along the direction A - A’ in Figure 3 Another schematic structural view of the display panel provided by the present invention, Figure 4 Another schematic structural view of the display panel provided by the present invention is used to illustrate a specific embodiment of the display panel 100 provided in this embodiment, including:

[0052] The sub-pixels 1 are arranged in an array. The sub-pixel 1 includes a first edge 2 and a second edge 3 that are oppositely arranged along the first direction X. The sub-pixels 1 are arranged along the first direction X to form sub-pixel rows 4, and the sub-pixels 1 are arranged along the second direction Y to form sub-pixel columns 5. The first direction X intersects with the second direction Y. The sub-pixel rows 4 include a first sub-pixel row 6 and a second sub-pixel row 7 that are alternately arranged along the second direction Y. The sub-pixel columns 5 include adjacent first sub-pixel columns 8 and second sub-pixel columns 9.

[0053] It further includes a substrate 16;

[0054] A plurality of signal lines 10, located on one side of the substrate 16. The plurality of signal lines 10 include:

[0055] A plurality of first signal lines 11, arranged along the first direction X and extending along the second direction Y. There is one sub-pixel column 5 between adjacent two first signal lines 11. The sub-pixel 1 located in the first sub-pixel row 6 is connected to the first signal line 11 that is the closest to the first edge 2 of the sub-pixel 1 along the first direction X. The sub-pixel 1 located in the second sub-pixel row 7 is connected to the first signal line 11 that is the closest to the second edge 3 of the sub-pixel 1 along the first direction X.

[0056] A second signal line 12, extending along the second direction Y, located between the first sub-pixel column 8 and the second sub-pixel column 9, and on the same layer as the first signal line 11;

[0057] The sub-pixel 1 includes a first sub-pixel 14 and a second sub-pixel 15. The first sub-pixel 14 is located in the first sub-pixel column 8 and in the second sub-pixel row 7. The second sub-pixel 15 is located in the second sub-pixel column 9 and in the first sub-pixel row 6.

[0058] The first signal line 11 includes a first sub-signal line 13. The first sub-signal line 13 is located between the first sub-pixel column 8 and the second sub-pixel column 9. The orthographic projection of the active layer 17 of at least one first sub-pixel 14 on the substrate 16 at least partially overlaps with the orthographic projection of the second signal line 12 on the substrate 16, and the orthographic projection of the active layer 17 of at least one second sub-pixel 15 on the substrate 16 at least partially overlaps with the orthographic projection of the second signal line 12 on the substrate 16.

[0059] Within a preset voltage range, the data writing voltages of at least one first sub-pixel 14 and at least one second sub-pixel 15 are equal.

[0060] It should be noted that in Figure 1 and Figure 3 only one arrangement manner of the sub-pixels 1 is schematically shown. Of course, it is not limited to this. The arrangement manner of the sub-pixels 1 or the number of sub-pixels 1 can be adjusted according to actual needs, and this embodiment does not make specific limitations thereto. Refer to Figure 1 and Figure 3, the sub-pixel 1 located in the first sub-pixel row 6 is connected to the first signal line 11 that is closest to the first edge 2 of the sub-pixel 1 along the first direction X. That is, the sub-pixel 1 in the first sub-pixel row 6 is connected to the first signal line 11 on the left side of the sub-pixel 1; the sub-pixel 1 located in the second sub-pixel row 7 is connected to the first signal line 11 that is closest to the second edge 3 of the sub-pixel 1 along the first direction X. That is, the sub-pixel 1 in the second sub-pixel row 7 is connected to the first signal line 11 on the right side of the sub-pixel 1. Of course, it is also possible to set the sub-pixel 1 in the first sub-pixel row 6 to be connected to the first signal line 11 on the right side of the sub-pixel 1; the sub-pixel 1 in the second sub-pixel row 7 is connected to the first signal line 11 on the left side of the sub-pixel 1. Refer to Figure 2 , the sub-pixel 1 includes a thin film transistor 18. The thin film transistor 18 includes a source electrode 19, a drain electrode 20, an active layer 17, and a gate electrode 21. In Figure 2 only the thin film transistor 18 is schematically shown as a top-gate structure. Of course, the thin film transistor 18 can also adopt a bottom-gate structure. In Figure 2 it is also schematically shown that the display panel 100 includes a substrate 16; the active layer 17 is located on one side of the substrate 16; the first metal layer 22 is located on the side of the active layer 17 away from the substrate 16; the second metal layer 23 is located on the side of the first metal layer 22 away from the substrate 16; the common electrode layer 24 is located on the side of the second metal layer 23 away from the substrate 16; the pixel electrode layer 26 is located on the side of the common electrode layer 24 away from the substrate 16. Among them, the common electrode layer 24 includes a common electrode 25, and the pixel electrode layer 26 includes a pixel electrode 27. The source electrode 19, the drain electrode 20, the first signal line 11, and the second signal line 12 are located in the second metal layer 23. The source electrode 19 is electrically connected to the first signal line 11, the drain electrode 20 is electrically connected to the pixel electrode 27, and the second signal line 12 is connected to the common electrode 25. Of course, the display panel 100 also includes other film layers, not limited to this. For the sake of simplicity of illustration, in Figure 1 the substrate 16 and the common electrode 25 are not schematically shown, and in Figure 2 the common electrode 25 is not pattern-filled. Figure 1 it is also schematically shown that there is a third signal line 61. The third signal line 61 can be a scan line.

[0061] It can be understood that Figure 1Only the second signal line 12 is shown to be located between the first sub-pixel column 8 and the first sub-signal line 13. When the first sub-pixel 14 is connected to the first sub-signal line 13 on its right side, the orthographic projection of the active layer 17 of the first sub-pixel 14 on the substrate 16 overlaps with the orthographic projection of the second signal line 12 on the substrate 16, and the active layer 17 of the first sub-pixel 14 and the second signal line 12 are not in the same layer, that is, a first capacitor is formed at the overlapping position of the active layer 17 of the first sub-pixel 14 and the second signal line 12, resulting in a decrease in the data writing voltage of the first sub-pixel 14. When the second sub-pixel 15 is connected to the first sub-signal line 13 on its left side, since the second signal line 12 is located on the side of the first sub-signal line 13 away from the second sub-pixel column 9, the second signal line 12 will not overlap with the active layer 17 of the second sub-pixel 15, that is, the data writing voltage of the second sub-pixel 15 does not change. In order to balance the data writing voltages of the first sub-pixel 14 and the second sub-pixel 15, the active layer 17 of the second sub-pixel 15 is extended, so that the orthographic projection of the active layer 17 of the second sub-pixel 15 on the substrate 16 overlaps with the orthographic projection of the second signal line 12 on the substrate 16, thereby forming a second capacitor at the overlapping position of the active layer 17 of the second sub-pixel 15 and the second signal line 12, and making the second capacitor equal to or approximately equal to the first capacitor, so as to achieve that within a preset voltage range, the data writing voltages of the first sub-pixel 14 and the second sub-pixel 15 are equal. The preset voltage range is usually the standard data writing voltage ±(5%×standard data writing voltage). Of course, the preset voltage range can also be adjusted according to different requirements, and this embodiment does not make specific limitations on this.

[0062] Similarly, Figure 3 Only the second signal line 12 is shown to be located between the first sub-signal line 13 and the second sub-pixel column 9. When the second sub-pixel 15 is connected to the first sub-signal line 13 on its left side, the orthographic projection of the active layer 17 of the second sub-pixel 15 on the substrate 16 overlaps with the orthographic projection of the second signal line 12 on the substrate 16, and the active layer 17 of the second sub-pixel 15 and the second signal line 12 are not in the same layer, that is, a second capacitor is formed at the overlapping position of the active layer 17 of the second sub-pixel 15 and the second signal line 12. And the second signal line 12 is located on the side of the first sub-signal line 13 away from the first sub-pixel 14. When the first sub-pixel 14 is connected to the first sub-signal line 13 on its right side, the active layer 17 of the first sub-pixel 14 will not overlap with the second signal line 12. Therefore, the active layer 17 of the first sub-pixel 14 is extended, so that the orthographic projection of the active layer 17 of the first sub-pixel 14 on the substrate 16 overlaps with the orthographic projection of the second signal line 12 on the substrate 16, thereby forming a first capacitor at the overlapping position of the active layer 17 of the first sub-pixel 14 and the second signal line 12, and making the first capacitor equal to or approximately equal to the second capacitor, so as to achieve that within a preset voltage range, the data writing voltages of the first sub-pixel 14 and the second sub-pixel 15 are equal, avoiding display differences and improving the display effect.

[0063] Optionally, Figure 4 only the second signal line 12 is shown between the first sub-pixel column 8 and the first sub-signal line 13. The first signal line 11 is connected to the driving chip 28, and the driving chip 28 provides a data writing voltage. There may be a voltage drop during the transmission of the data writing voltage along the first signal line 11. The display panel 100 includes a first area 29 and a second area 30. The first area 29 is located on the side of the second area 30 close to the driving chip 28. Therefore, the voltage drop in the first area 29 is small, and the voltage drop in the second area 30 is large. There may be a capacitance generated between the second signal line 12 and the active layer 17 of the sub-pixel 1 in the first area 29, which does not affect the display in the first area 29. However, a capacitance is generated between the second signal line 12 and the active layer 17 of the sub-pixel 1 in the second area 30, which affects the display effect in the second area 30. It can be set that in the first area 29, the orthographic projection of the active layer 17 of the first sub-pixel 14 on the substrate 16 partially overlaps with the orthographic projection of the second signal line 12 on the substrate 16, and the orthographic projection of the active layer 17 of the second sub-pixel 15 on the substrate 16 does not overlap with the orthographic projection of the second signal line 12 on the substrate 16; in the second area 30, the orthographic projection of the first sub-pixel 14 on the substrate 16 partially overlaps with the orthographic projection of the second signal line 12 on the substrate 16, and the orthographic projection of the second sub-pixel 15 on the substrate 16 partially overlaps with the orthographic projection of the second signal line 12 on the substrate 16.

[0064] Compared with the prior art, the display panel 100 provided in this embodiment has at least the following advantages:

[0065] In the display panel 100 provided by the present invention, a sub-pixel column 5 is provided between two adjacent first signal lines 11; the sub-pixel 1 located in the first sub-pixel row 6 is connected to the first signal line 11 closest to the first edge 2 of the sub-pixel 1 along the first direction X; the sub-pixel 1 located in the second sub-pixel row 7 is connected to the first signal line 11 closest to the second edge 3 of the sub-pixel 1 along the first direction X, forming a display panel 100 with a zig-zag structure to reduce power consumption and improve the display effect of the display panel 100; a second signal line 12 extends along the second direction Y, is located between the first sub-pixel column 8 and the second sub-pixel column 9, and is on the same layer as the first signal line 11; the sub-pixel 1 includes a first sub-pixel 14 and a second sub-pixel 15, the first sub-pixel 14 is located in the first sub-pixel column 8 and in the second sub-pixel row 7; the second sub-pixel 15 is located in the second sub-pixel column 9 and in the first sub-pixel row 6; the first signal line 11 includes a first sub-signal line 13, the first sub-signal line 13 is located between the first sub-pixel column 8 and the second sub-pixel column 9, and the orthographic projection of the active layer 17 of at least one first sub-pixel 14 on the substrate 16 at least partially overlaps with the orthographic projection of the second signal line 12 on the substrate 16, and the orthographic projection of the active layer 17 of at least one second sub-pixel 15 on the substrate 16 at least partially overlaps with the orthographic projection of the second signal line 12 on the substrate 16; within a preset voltage range, the data writing voltages of at least one first sub-pixel 14 and at least one second sub-pixel 15 are equal. When the first sub-signal line 13 is located between the first sub-pixel column 8 and the second signal line 12, the orthographic projection of the active layer 17 of the second sub-pixel 15 on the substrate 16 at least partially overlaps with the orthographic projection of the second signal line 12 on the substrate 16. Therefore, the active layer 17 of the second sub-pixel 15 forms a capacitor with the second signal line 12, which will cause the data writing voltage of the second sub-pixel 15 to decrease. By setting the orthographic projection of the active layer 17 of the first sub-pixel 14 on the substrate 16 to at least partially overlap with the orthographic projection of the second signal line 12 on the substrate 16, that is, extending the active layer 17 of the first sub-pixel 14, the active layer 17 of the first sub-pixel 14 forms a capacitor with the second signal line 12, so that the data writing voltage of the first sub-pixel 14 also decreases, realizing that within the preset voltage range, the data writing voltages of the first sub-pixel 14 and the second sub-pixel 15 are equal, avoiding display differences between the first sub-pixel 14 and the second sub-pixel 15, and improving the display effect.Similarly, when the first sub-signal line 13 is located between the second signal line 12 and the second sub-pixel column 9, the orthographic projection of the active layer 17 of the first sub-pixel 14 on the substrate 16 overlaps partially with the orthographic projection of the second signal line 12 on the substrate 16. The active layer 17 of the first sub-pixel 14 forms a capacitor with the second signal line 12, resulting in a decrease in the data writing voltage of the first sub-pixel 14. It is set that the orthographic projection of the active layer 17 of the second sub-pixel 15 on the substrate 16 overlaps partially with the orthographic projection of the second signal line 12 on the substrate 16, that is, the active layer 17 of the second sub-pixel 15 is extended, so that the active layer 17 of the second sub-pixel 15 forms a capacitor with the second signal line 12, thereby also reducing the data writing voltage of the second sub-pixel 15. Within the preset voltage range, the data writing voltages of the first sub-pixel 14 and the second sub-pixel 15 are equal, avoiding display differences between the first sub-pixel 14 and the second sub-pixel 15 and improving the display effect.

[0066] In some alternative embodiments, referring to Figure 1 and Figure 5 , Figure 5 is another structural schematic diagram of the display panel provided by the present invention. The length of the active layer 17 of the first sub-pixel 14 between the first sub-pixel column 8 and the first sub-signal line 13 is M, and the length of the active layer 17 of the second sub-pixel 15 between the second sub-pixel column 9 and the first sub-signal line 13 is N. Within the preset length range, M = N.

[0067] It can be understood that Figure 1 only shows that the first sub-signal line 13 is located exactly in the middle between the first sub-pixel column 8 and the second sub-pixel column 9, Figure 3 only shows that the distance between the first sub-signal line 13 and the first sub-pixel column 8 is greater than the distance between the first sub-signal line 13 and the second sub-pixel column 9. It is set that within the preset length range, M = N, that is, when the data writing voltage is transmitted from the first sub-signal line 13 to the first sub-pixel 14, the resistance effect of the active layer 17 of the first sub-pixel 14 is R1, and when the data writing voltage is transmitted from the first sub-signal line 13 to the second sub-pixel 15, the resistance effect of the active layer 17 of the second sub-pixel 15 is R2, and R1 = R2. This can avoid resistance differences, make the data writing voltages of the first sub-pixel 14 and the second sub-pixel 15 equal or approximately equal, thereby avoiding display differences between the first sub-pixel 14 and the second sub-pixel 15 and improving the display effect.

[0068] In some alternative embodiments, referring to Figure 6 , Figure 6 is another structural schematic diagram of the display panel provided by the present invention. The sub-pixel 1 not connected to the first sub-signal line 1 is connected to a compensation unit 31. Within the preset voltage range, the data writing voltages of the sub-pixels 1 are all equal.

[0069] It can be understood that in Figure 6 only the second signal line 12 is schematically shown to be located between the first sub-pixel column 8 and the first sub-signal line 13. The active layer 17 of the first sub-pixel 1 forms a capacitor with the second signal line 12. In order to make the data writing voltages of the first sub-pixel 1 and the second sub-pixel 1 equal or approximately equal, it is set that the active layer 17 of the second sub-pixel 1 also forms a capacitor with the second signal line 12. And in order to achieve the display uniformity of the display panel 100, or the display uniformity of a partial area of the display panel 100, the sub-pixel 1 not connected to the first sub-signal line 13, that is, the sub-pixel 1 whose active layer does not form a capacitor with the second signal line 12, can be connected to the compensation part 31. Specifically, the compensation part 31 connects the active layer 17 between the pixel electrode 27 and the first signal line 11, so as to make the data writing voltages of all or part of the sub-pixels 1 equal within a preset voltage range, and improve the uniformity of the display panel 100.

[0070] Referring to Figure 7 , Figure 7 which is another structural schematic diagram of the display panel provided by the present invention, to illustrate another specific embodiment of the display panel 100 provided in this embodiment, including:

[0071] Sub-pixels 1 arranged in an array. The sub-pixels 1 include a first edge 2 and a second edge 3 oppositely arranged along the first direction X. The sub-pixels 1 are arranged along the first direction X to form sub-pixel rows 4, and the sub-pixels 1 are arranged along the second direction Y to form sub-pixel columns 5. The first direction X intersects with the second direction Y; the sub-pixel rows 4 include a first sub-pixel row 6 and a second sub-pixel row 7 alternately arranged along the second direction Y, and the sub-pixel columns 5 include adjacent first sub-pixel columns 8 and second sub-pixel columns 9;

[0072] It further includes a substrate 16;

[0073] Multiple signal lines 10, located on one side of the substrate 16. The multiple signal lines 10 include:

[0074] Multiple first signal lines 11, arranged along the first direction X and extending along the second direction Y. There is a sub-pixel column 5 between two adjacent first signal lines 11; the sub-pixels 1 in the first sub-pixel row 6 are connected to the first signal line 11 that is the closest to the first edge 2 of the sub-pixel 1 along the first direction X; the sub-pixels 1 in the second sub-pixel row 7 are connected to the first signal line 11 that is the closest to the second edge 3 of the sub-pixel 1 along the first direction X;

[0075] A second signal line 12, extending along the second direction Y, located between the first sub-pixel column 8 and the second sub-pixel column 9, and partially on the same layer as the first signal line 11;

[0076] The sub-pixel 1 includes a first sub-pixel 14 and a second sub-pixel 15. The first sub-pixel 14 is located in the first sub-pixel column 8 and the second sub-pixel row 7. The second sub-pixel 15 is located in the second sub-pixel column 9 and the first sub-pixel row 6. The orthographic projection of the active layer 17 of at least one first sub-pixel 14 on the substrate 16 does not overlap with the orthographic projection of the second signal line 12 on the substrate 16, and the orthographic projection of the active layer 17 of at least one second sub-pixel 15 on the substrate 16 does not overlap with the orthographic projection of the second signal line 12 on the substrate 16. Within a preset voltage range, the data writing voltages of at least one first sub-pixel 14 and at least one second sub-pixel 15 are equal.

[0077] It should be noted that Figure 7 only shows a schematic diagram in which the orthographic projection of the active layer 17 of the first sub-pixel 14 on the substrate 16 does not overlap with the orthographic projection of the second signal line 12 on the substrate 16, and the orthographic projection of the active layer 17 of the second sub-pixel 15 on the substrate 16 does not overlap with the orthographic projection of the second signal line 12 on the substrate 16. Of course, it is not limited to this. The sub-pixel 1 in the first sub-pixel row 6 is connected to the first signal line 11 that is closest to the first edge 2 of the sub-pixel 1 along the first direction X. That is, the sub-pixel 1 in the first sub-pixel row 6 is connected to the first signal line 11 on the left side of the sub-pixel 1. The sub-pixel 1 in the second sub-pixel row 7 is connected to the first signal line 11 that is closest to the second edge 3 of the sub-pixel 1 along the first direction X. That is, the sub-pixel 1 in the second sub-pixel row 7 is connected to the first signal line 11 on the right side of the sub-pixel 1 to form a zigzag-shaped display panel 100. Of course, it is also possible to set the sub-pixel 1 in the first sub-pixel row 6 to be connected to the first signal line 11 on the right side of the sub-pixel 1, and the sub-pixel 1 in the second sub-pixel row 7 to be connected to the first signal line 11 on the left side of the sub-pixel 1.

[0078] It can be understood that between the first sub-pixel column 8 and the second sub-pixel column 9, there are a first signal line 11 and a second signal line 12. The first signal line 11 and the second signal line 12 extend along the second direction Y, and the first signal line 11 and the second signal line 12 are on the same layer. In order to avoid the overlap between the active layer 17 of the first sub-pixel 14 or the active layer 17 of the second sub-pixel 15 and the second signal line 12 to generate capacitance, a part of the first signal line 11 is wound, so that the active layer 17 of the first sub-pixel 14 and the active layer 17 of the second sub-pixel 15 will not overlap with the second signal line 12 to generate capacitance, realizing that the data writing voltages of the first sub-pixel 14 and the second sub-pixel 15 are equal within a preset voltage range. That is, to avoid the difference in the data writing voltages of the first sub-pixel 14 and the second sub-pixel 15, make the display of the first sub-pixel 14 and the second sub-pixel 15 uniform, and improve the display effect. And the wound part can be set to be on a different layer from the second signal line 12 in order to avoid short circuit caused by contact with the second signal line 12. In Figure 7Only the case where the first signal line 11 is partially wound is taken as an example. Of course, the second signal line 12 can also be wound to avoid the capacitance generated between the second signal line 12 and the active layer 17 of the first sub-pixel 14 or the active layer 17 of the second sub-pixel 15, which affects the data writing voltage of the first sub-pixel 14 or the data writing voltage of the second sub-pixel 15.

[0079] Optionally, the first signal line 11 is connected to the driving chip 28, and the driving chip 28 provides a data writing voltage. There may be a voltage drop during the transmission of the data writing voltage along the first signal line 11. Figure 7 Only the display panel 100 including the third area 32 and the fourth area 33 is schematically shown. The third area 32 is located on the side of the fourth area 33 close to the driving chip 28. Therefore, the voltage drop in the third area 32 is small, and the voltage drop in the fourth area 33 is large. In order to avoid further affecting the data writing voltage of the first sub-pixel 14 or the second sub-pixel 15 in the fourth area 33, only the first signal line 11 in the fourth area 33 can be wound, so that in the fourth area 33, the orthographic projection of the first sub-pixel 14 on the substrate 16 does not overlap with the orthographic projection of the second signal line 12 on the substrate 16, and the orthographic projection of the second sub-pixel 15 on the substrate 16 does not overlap with the orthographic projection of the second signal line 12 on the substrate 16. In this embodiment, only the winding of the first signal line 11 in the fourth area 33 is schematically shown. Of course, it is not limited to this, and the area can be set according to actual needs.

[0080] In some alternative embodiments, refer to Figure 8 , Figure 8 is another schematic structural diagram of the display panel provided by the present invention. The orthographic projections of the active layers 17 of all the first sub-pixels 14 on the substrate 16 do not overlap with the orthographic projection of the second signal line 12 on the substrate 16, and the orthographic projections of the active layers 17 of all the second sub-pixels 15 on the substrate 16 do not overlap with the orthographic projection of the second signal line 12 on the substrate 16.

[0081] It can be understood that in Figure 8 only the orthographic projection of the active layer 17 of the first sub-pixel 14 on the substrate 16 does not overlap with the orthographic projection of the second signal line 12 on the substrate 16, and the orthographic projection of the active layer 17 of the second sub-pixel 15 on the substrate 16 does not overlap with the orthographic projection of the second signal line 12 on the substrate 16, so as to ensure that the data writing voltages of the first sub-pixel 14 and the second sub-pixel 15 are equal within a preset voltage range, thereby realizing the uniform display of the entire display panel 100.

[0082] Optionally, refer to Figure 8, since the first signal line 11 is wound around to the side of the second signal line 12 close to the first sub-pixel 14, when the first sub-pixel 14 is connected to the first signal line 11, it may cause the length of the active layer 17 of the first sub-pixel 14 to be shortened, thereby causing the data writing voltage of the first sub-pixel 14 to be unequal to that of other sub-pixels 1. Therefore, a compensation part 31 is provided. The compensation part 31 connects the active layer 17 of the first sub-pixel 14 between the first signal line 11 and the pixel electrode 27 of the first sub-pixel 14, so that the data writing voltages of all the sub-pixels 1 in the display panel 100 are equal within a preset voltage range, realizing display uniformity. Similarly, if the winding of the first signal line 11 causes the length of the active layer 17 of the second sub-pixel 15 to be shortened, the compensation part 31 can also be provided. The compensation part 31 connects the active layer 17 of the second sub-pixel 15 between the pixel electrode 27 of the second sub-pixel 15 and the first signal line 11. The specific setting of the compensation part 31 can be adjusted according to actual needs, and this embodiment does not make specific limitations on this.

[0083] In some alternative embodiments, continue to refer to Figure 8 , the first signal line 11 includes a first sub-signal line 13. The first sub-signal line 13 is located between the first sub-pixel column 8 and the second sub-pixel column 9. The first sub-signal line 13 includes alternately connected first parts 34 and second parts 35. The first parts 34 are located in the first sub-pixel row 6, and the second parts 35 are located in the second sub-pixel row 7;

[0084] The first parts 34 are located between the second signal line 12 and the second sub-pixel column 9. The second part 35 includes sequentially connected first sub-parts 36, second sub-parts 37, third sub-parts 38, and fourth sub-parts 39. The first sub-parts 36 and the fourth sub-parts 39 are located between the second signal line 12 and the second sub-pixel column 9. The connection part of the second sub-parts 37 and the third sub-parts 38 is located between the first sub-pixel column 8 and the second signal line 12.

[0085] It can be understood that in Figure 8Only the second sub - part 37 and the third sub - part 38 of the second part 35 are shown as winding parts. The connection between the first sub - part 36 and the second sub - part 37 is located between the second signal line 12 and the second sub - pixel column 9. The connection between the second sub - part 37 and the third sub - part 38 is located between the first sub - pixel column 8 and the second signal line 12. The connection between the third sub - part 38 and the fourth sub - part 39 is located between the second signal line 12 and the second sub - pixel column 9. When the second sub - pixel 15 is connected to the first sub - signal line 13, the active layer 17 of the second sub - pixel 15 does not overlap with the second signal line 12. The active layer 17 of the first sub - pixel 14 is connected to the connection between the second sub - part 37 and the third sub - part 38, and the active layer 17 of the first sub - pixel 14 also does not overlap with the second signal line 12. Thus, it is ensured that the data writing voltages of the first sub - pixel 14 and the second sub - pixel 15 are equal within a preset voltage range, avoiding display differences between the first sub - pixel 14 and the second sub - pixel 15 and improving the display effect.

[0086] In some alternative embodiments, referring to Figure 8 and Figure 9 , Figure 9 is Figure 8 a sectional view taken along the B - B' direction in

[0087] The display panel 100 provided in this embodiment further includes a metal film layer 000, which is located on one side of the substrate 16;

[0088] It should be noted that the sub - pixel 1 includes a thin - film transistor 18. The thin - film transistor 18 includes a source electrode 19, a drain electrode 20, an active layer 17, and a gate electrode 21. In Figure 9 only the thin - film transistor 18 is shown as a top - gate structure. Of course, the thin - film transistor 18 can also adopt a bottom - gate structure. Referring to Figure 9 , the metal film layer 000 is located on one side of the substrate 16. The metal film layer 000 includes a first metal layer 22 and a second metal layer 23. The second metal layer 23 is located on the side of the first metal layer 22 away from the substrate 16. The gate electrode 21 is located in the first metal layer 22, and the source electrode 19 and the drain electrode 20 are located in the second metal layer 23. The display panel 100 further includes other film layers. For example, the active layer 17 is located between the substrate 16 and the first metal layer 22; the common electrode layer 24 is located on the side of the second metal layer 23 away from the substrate 16; the pixel electrode layer 26 is located on the side of the common electrode layer 24 away from the substrate 16. Among them, the common electrode layer 24 includes a common electrode 25, and the pixel electrode layer 26 includes a pixel electrode 27. For the sake of simplicity in illustration, the common electrode 25 is not shown in Figure 8 thus, inFigure 9 Nor is the common electrode 25 pattern-filled. Of course, the display panel 100 may further include other film layers, which are not limited thereto.

[0089] It can be understood that, with reference to Figure 9 , the source electrode 19, the drain electrode 20, the second signal line 12, the first part 34, the first sub-part 36, and the fourth sub-part 39 are located in the second metal layer 23, the second sub-part 37 and the third sub-part 38 are located in the first metal layer 22. The source electrode 19 is connected to the connection between the second sub-part 37 and the third sub-part 38 through a via. One end of the first sub-part 36 far from the first part 34 is connected to one end of the second sub-part 37 far from the third sub-part 38 through a via. One end of the third sub-part 38 far from the second sub-part 37 is connected to one end of the fourth sub-part 39 through a via, enabling the second sub-part 37 and the third sub-part 38 to wind wires in the first metal layer 22, which can avoid the second sub-part 37 and the third sub-part 38 contacting the second signal line 12 during wire winding and causing a short circuit.

[0090] In some alternative embodiments, with reference to Figure 10 , Figure 10 is another structural schematic diagram of the display panel provided by the present invention. The first signal line 11 includes a first sub-signal line 13. The first sub-signal line 13 is located between the first sub-pixel column 8 and the second sub-pixel column 9. The first sub-signal line 13 includes an alternately connected third part 40 and fourth part 41. The third part 40 is located in the first sub-pixel row 6, and the fourth part 41 is located in the second sub-pixel row 7;

[0091] The third part 40 is located between the second signal line 12 and the second sub-pixel column 9. The fourth part 41 includes a fifth sub-part 42, a sixth sub-part 43, and a seventh sub-part 44 connected in sequence. The sixth sub-part 43 is located between the first sub-pixel column 8 and the second signal line 12.

[0092] It can be understood that Figure 10 only shows that in the first sub-pixel row 6, the third part 40 is located between the second signal line 12 and the second sub-pixel 15. The second sub-pixel 15 is connected to the third part 40. The orthographic projection of the active layer 17 of the second sub-pixel 15 on the substrate 16 does not overlap with the orthographic projection of the second signal line 12 on the substrate 16. The winding part is the fifth sub-part 42, the sixth sub-part 43, and the seventh sub-part 44. In the second sub-pixel row 7, the sixth sub-part 43 is located between the first sub-pixel 14 and the second signal line 12. The active layer 17 of the first sub-pixel 14 is connected to the sixth sub-part 43, thereby avoiding the orthographic projection of the active layer 17 of the first sub-pixel 14 on the substrate 16 overlapping with the orthographic projection of the second signal line 12 on the substrate 16, ensuring that the data writing voltages of the first sub-pixel 14 and the second sub-pixel 15 are the same, avoiding display differences between the first sub-pixel 14 and the second sub-pixel 15, and improving the display effect.

[0093] In some alternative embodiments, with continued reference to Figure 10 , the second signal line 12 includes a fifth portion 45 and a sixth portion 46 that are alternately connected. The fifth portion 45 is located in the first sub-pixel row 6, and the sixth portion 46 is located in the second sub-pixel row 7;

[0094] The sixth portion 46 includes an eighth sub-portion 47, a ninth sub-portion 48, and a tenth sub-portion 49 that are sequentially connected. The ninth sub-portion 48 is located between the second sub-pixel column 9 and the sixth sub-portion 43. The width of the eighth sub-portion 47 is R, the width of the ninth sub-portion 48 is S, and the width of the tenth sub-portion 49 is T, where R < S and T < S.

[0095] It can be understood that in Figure 10 , only the winding of the fourth portion 41 of the first signal line 11 and the winding of the sixth portion 46 of the second signal line 12 are shown. This can further prevent the second signal line 12 from overlapping with the active layers 17 of the first sub-pixel 14 and the second sub-pixel 15, thereby avoiding the capacitance effect on the data writing voltages of the first sub-pixel 14 and the second sub-pixel 15. The orthographic projection of the eighth sub-portion 47 on the substrate 16 partially overlaps with the orthographic projection of the fifth portion 42 on the substrate 16, and the orthographic projection of the tenth sub-portion 49 on the substrate 16 partially overlaps with the orthographic projection of the seventh sub-portion 44 on the substrate 16. By setting R < S and T < S, that is, reducing the widths of the eighth sub-portion 47 and the tenth sub-portion 49, the overlapping areas between the eighth sub-portion 47 and the fifth portion 42 and between the tenth sub-portion 49 and the seventh sub-portion 44 can be reduced, thereby reducing the capacitance generated between the second signal line 12 and the first signal line 13, which helps to reduce the voltage drop of the first signal line 13 and avoid the data writing voltage of sub-pixel 1 from being too low.

[0096] In some alternative embodiments, with reference to Figure 11 , Figure 11 is Figure 10 a cross-sectional view taken along the C-C' direction in

[0097] The display panel 100 provided in this embodiment further includes a metal film layer 000 located on one side of the substrate 16;

[0098] It should be noted that the sub-pixel 1 includes a thin-film transistor 18, and the thin-film transistor 18 includes a source electrode 19, a drain electrode 20, an active layer 17, and a gate electrode 21. In Figure 11Only the thin film transistor 18 is schematically shown as a top-gate structure. The metal film layer 000 is located on one side of the substrate 16. The metal film layer 000 includes a first metal layer 22 and a second metal layer 23. The second metal layer 23 is located on the side of the first metal layer 22 away from the substrate 16. The gate 21 is located on the first metal layer 22, and the source 19 and the drain 20 are located on the second metal layer 23. The display panel 100 further includes other film layers. For example, the active layer 17 is located between the substrate 16 and the first metal layer 22; the common electrode layer 24 is located on the side of the second metal layer 23 away from the substrate 16; the pixel electrode layer 26 is located on the side of the common electrode layer 24 away from the substrate 16. Among them, the common electrode layer 24 includes the common electrode 25, and the pixel electrode layer 26 includes the pixel electrode 27. For the sake of convenience of illustration, in Figure 10 the common electrode 25 is not shown, so in Figure 11 the common electrode 25 is not pattern-filled either. Of course, the display panel 100 may further include other film layers, which are not limited thereto.

[0099] It can be understood that the source 19, the drain 20, the second signal line 12, the third part 40, and the sixth sub-part 43 are located on the second metal layer 23, the fifth sub-part 42 and the seventh sub-part 44 are located on the first metal layer 22. The source 19 is connected to the sixth sub-part 43 through a via. One end of the sixth sub-part 43 is connected to one end of the fifth sub-part 42 away from the third part 40 through a via, and the other end of the sixth sub-part 43 is connected to the first end of the seventh sub-part 44 through a via. The arrangement of the fifth sub-part 42 and the seventh sub-part 44 on the first metal layer 22 can avoid short circuits caused by contact with the second signal line 12 during wire winding.

[0100] In some alternative embodiments, referring to Figure 12 , Figure 12 is another schematic structural diagram of the display panel provided by the present invention. The first signal line 11 includes a first sub-signal line 13. The first sub-signal line 13 is located between the first sub-pixel column 8 and the second sub-pixel column 9. The second signal line 12 includes alternately connected seventh part 50 and eighth part 51. The seventh part 50 is located in the first sub-pixel row 6, and the eighth part 51 is located in the second sub-pixel row 7;

[0101] The seventh part 50 is located between the first sub-signal line 13 and the first sub-pixel column 8. The eighth part 51 includes successively connected eleventh sub-part 52, twelfth sub-part 53, thirteenth sub-part 54, and fourteenth sub-part 55. The eleventh sub-part 52 and the fourteenth sub-part 55 are located between the first sub-signal line 13 and the first sub-pixel 14, and the connection point of the twelfth sub-part 53 and the thirteenth sub-part 54 is located between the first sub-signal line 13 and the second sub-pixel column 9.

[0102] It can be understood that Figure 12Only the eighth part 51 is schematically shown for winding setting to avoid the capacitance generated by the overlap of the second signal line 12 and the active layer 17 of the first sub-pixel 14. Of course, it is not limited to this. The connection between the eleventh sub-part 52 and the twelfth sub-part 53 is located between the first sub-pixel column 8 and the first sub-signal line 13. The connection between the twelfth sub-part 53 and the thirteenth sub-part 54 is located between the first sub-signal line 13 and the second sub-pixel column 9. The connection between the thirteenth sub-part 54 and the fourteenth sub-part 55 is located between the first sub-pixel column 8 and the first sub-signal line 13, so that the twelfth sub-part 53 and the thirteenth sub-part 54 bypass the position where the active layer 17 of the first sub-pixel 14 is connected to the first signal line 11, thereby avoiding the capacitance generated by the second signal line 12 and the active layer 17 of the first sub-pixel 14, thus avoiding the difference in the data writing voltage of the first sub-pixel 14 and the second sub-pixel 15 and ensuring the display effect of the first sub-pixel 14 and the second sub-pixel 15.

[0103] In some alternative embodiments, referring to Figure 12 and Figure 13 , Figure 13 is Figure 12 the cross-sectional view in the D-D' direction in, the display panel 100 provided in this embodiment further includes a metal film layer 000, located on one side of the substrate 16;

[0104] The metal film layer 000 includes a first metal layer 22 and a second metal layer 23. The second metal layer 23 is located on the side of the first metal layer 22 away from the substrate 16. The twelfth sub-part 53 and the thirteenth sub-part 54 are located on the first metal layer 22. The seventh part 50, the eleventh sub-part 52, the fourteenth sub-part 55 and the first sub-signal line 13 are located on the second metal layer 23.

[0105] It should be noted that the sub-pixel 1 includes a thin film transistor 18. The thin film transistor 18 includes a source electrode 19, a drain electrode 20, an active layer 17 and a gate electrode 21. In Figure 13 only the thin film transistor 18 is schematically shown as a top-gate structure. The metal film layer 000 is located on one side of the substrate 16. The metal film layer 000 includes a first metal layer 22 and a second metal layer 23. The second metal layer 23 is located on the side of the first metal layer 22 away from the substrate 16. The gate electrode 21 is located on the first metal layer 22. The source electrode 19 and the drain electrode 20 are located on the second metal layer 23. The display panel 100 further includes other film layers. For example, the active layer 17 is located between the substrate 16 and the first metal layer 22; the common electrode layer 24 is located on the side of the second metal layer 23 away from the substrate 16; the pixel electrode layer 26 is located on the side of the common electrode layer 24 away from the substrate 16. Among them, the common electrode layer 24 includes a common electrode 25, and the pixel electrode layer 26 includes a pixel electrode 27. For the convenience of illustration, the common electrode 25 is not shown in Figure 12 so in Figure 13Nor is the common electrode 25 patterned. Of course, the display panel 100 may also include other film layers, which are not limited thereto.

[0106] It can be understood that the source electrode 19, the drain electrode 20, the first signal line 11, the seventh section 50, the eleventh sub-section 52, and the fourteenth sub-section 55 are located in the second metal layer 23. When the second signal line 12 is wound, in order to prevent the second signal line 12 from contacting the first sub-signal line 13, the twelfth sub-section 53 and the thirteenth sub-section 54 are disposed in the first metal layer 22. One end of the twelfth sub-section 53 far from the thirteenth sub-section 54 is connected to one end of the eleventh sub-section 52 far from the seventh section 50 through a via, and the thirteenth sub-section 54 is connected to one end of the fourteenth sub-section 55 through a via, so that the orthographic projection of the second signal line 12 on the substrate 16 does not overlap with the orthographic projection of the active layer 17 of the sub-pixel 1 on the substrate 16, making the data writing voltages of the first sub-pixel 14 and the second sub-pixel 15 equal within a preset voltage range and improving the display effect.

[0107] In some alternative embodiments, referring to Figure 14 , Figure 14 is another structural schematic diagram of the display panel provided by the present invention. The first signal line 11 includes a first sub-signal line 13, and the first sub-signal line 13 is located between the first sub-pixel column 8 and the second sub-pixel column 9. The second signal line 12 includes alternately connected ninth sections 56 and tenth sections 57. The ninth section 56 is located in the first sub-pixel row 6, and the tenth section 57 is located in the second sub-pixel row 7;

[0108] The ninth section 56 is located between the first sub-signal line 13 and the first sub-pixel column 8. The tenth section 57 includes successively connected fifteenth sub-sections 58, sixteenth sub-sections 59, and seventeenth sub-sections 60. The sixteenth sub-section 59 is located between the second sub-pixel column 9 and the first sub-signal line 13.

[0109] It can be understood that in Figure 14 only the winding of the second signal line 12 is shown. Of course, it may also be that the second signal line 12 and the first sub-signal line 13 are wound simultaneously. Referring to Figure 14 , the ninth section 56 is located on the side of the first sub-signal line 13 far from the second sub-pixel 15, the sixteenth sub-section 59 is located on the side of the first sub-signal line 13 far from the first sub-pixel 14, one end of the sixteenth sub-section 59 is connected to one end of the fifteenth sub-section 58 far from the ninth section 56, and the other end of the sixteenth sub-section 59 is connected to one end of the seventeenth sub-section 60. Therefore, the tenth section 57 bypasses the active layer 17 of the first sub-pixel 14, thereby avoiding overlapping with the active layer 17 of the first sub-pixel 14 to generate capacitance, making the data writing voltages of the first sub-pixel 14 and the second sub-pixel 15 equal within a preset voltage range, avoiding display differences between the first sub-pixel 14 and the second sub-pixel 15, and improving the display effect.

[0110] In some alternative embodiments, referring to Figure 14 and Figure 15 , Figure 15 is Figure 14 a cross-sectional view taken along the E-E' direction in , the display panel 100 provided in this embodiment further includes a metal film layer 000 located on one side of the substrate 16;

[0111] The metal film layer 000 includes a first metal layer 22 and a second metal layer 23. The second metal layer 23 is located on the side of the first metal layer 22 away from the substrate 16. The fifteenth sub-part 58 and the seventeenth sub-part 60 are located on the first metal layer 22. The ninth part 56, the sixteenth sub-part 59, and the first sub-signal line 13 are located on the second metal layer 23.

[0112] It should be noted that the sub-pixel 1 includes a thin-film transistor 18. The thin-film transistor 18 includes a source electrode 19, a drain electrode 20, an active layer 17, and a gate electrode 21. In Figure 15 only the thin-film transistor 18 is shown as a top-gate structure. The metal film layer 000 is located on one side of the substrate 16. The metal film layer 000 includes a first metal layer 22 and a second metal layer 23. The second metal layer 23 is located on the side of the first metal layer 22 away from the substrate 16. The gate electrode 21 is located on the first metal layer 22. The source electrode 19 and the drain electrode 20 are located on the second metal layer 23. The display panel 100 further includes other film layers. For example, the active layer 17 is located between the substrate 16 and the first metal layer 22; the common electrode layer 24 is located on the side of the second metal layer 23 away from the substrate 16; the pixel electrode layer 26 is located on the side of the common electrode layer 24 away from the substrate 16. Among them, the common electrode layer 24 includes a common electrode 25, and the pixel electrode layer 26 includes a pixel electrode 27. For the sake of simplicity in illustration, the common electrode 25 is not shown in Figure 14 , so the common electrode 25 is not pattern-filled in Figure 15 either. Of course, the display panel 100 may further include other film layers, and is not limited thereto.

[0113] It can be understood that the source electrode 19, the drain electrode 20, the ninth part 56, the sixteenth sub-part 59, and the first signal line 11 are located on the second metal layer 23. In Figure 14 only the tenth part 57 is shown for wire winding. In order to prevent the tenth part 57 from contacting the first sub-signal line 13 during wire winding, the positions in the tenth part 57 that can overlap with the first sub-signal line 13 are arranged on the first metal layer 22, that is, the fifteenth sub-part 58 and the seventeenth sub-part 60 are arranged on the first metal layer 22. Optionally, Figure 15Only the widths of the fifteenth sub - portion 58 and the seventeenth sub - portion 60 are schematically shown to be reduced, so as to reduce the overlapping area between the fifteenth sub - portion 58 and the first sub - signal line 13, and the overlapping area between the seventeenth sub - portion 60 and the first sub - signal line 13, thereby reducing the impedance of the first sub - signal line 13. Of course, the overlapping area between the fifteenth sub - portion 58 and the first sub - signal line 13, and the overlapping area between the seventeenth sub - portion 60 and the first sub - signal line 13 can also be reduced by reducing the widths of the corresponding positions of the first sub - signal line 13 and the fifteenth sub - portion 58, and the corresponding positions of the first sub - signal line 13 and the seventeenth sub - portion 60. This embodiment does not make specific limitations on this.

[0114] In some alternative embodiments, continue to refer to Figure 10 and Figure 16 , Figure 16 is another schematic structural diagram of the display panel provided by the present invention. The display panel 100 provided in this embodiment further includes a third signal line 61 arranged along the second direction Y, which includes an eleventh portion 62, a twelfth portion 63, and a thirteenth portion 64 connected in sequence along the first direction X. The eleventh portion 62 and the thirteenth portion 64 extend along the first direction X, and the third signal line 61 is correspondingly arranged with the sub - pixel row 4;

[0115] The orthographic projection of the twelfth portion 63 on the substrate 16 at least partially overlaps with the orthographic projection of the second signal line 12 on the substrate 16, and the twelfth portion 63 protrudes towards the nearest first sub - pixel row 6.

[0116] It can be understood that the third signal line 61 can be a scanning line. In Figure 10 only the twelfth portion 63 of a part of the third signal line 61 is schematically shown to protrude towards the first sub - pixel row 6. Of course, it is not limited to this. Refer to Figure 10 , because the winding part winds around the second sub - pixel row 7, and for the third signal line 61 corresponding to the second sub - pixel row 7, the twelfth portion 63 is set to protrude towards the first sub - pixel 14, which can reserve space for winding. Of course, it is not limited to this. The winding position and the orientation of the twelfth portion 63 can also be adjusted according to actual needs. This embodiment does not make specific limitations on this. Optionally, refer to Figure 16 , it can also be set that the twelfth portions 63 of all the third signal lines 61 protrude towards the next row, which can make the impedances of the third signal lines 61 equal or approximately equal, thereby ensuring the uniformity of data transmission of the third signal lines 61.

[0117] In some alternative embodiments, refer to Figure 17 , Figure 17 is another schematic structural diagram of the display panel provided by the present invention. The display panel 100 provided in this embodiment further includes a light - shielding portion 65 extending along the first direction X, and the light - shielding portion 65 is correspondingly arranged with the third signal line 61;

[0118] The orthographic projection of the third signal line 61 on the substrate 16 is within the orthographic projection range of the light-shielding portion 65 on the substrate 16. Along the second direction Y, the width of the light-shielding portion 65 is greater than 6 um.

[0119] It can be understood that, for the convenience of illustration, the substrate 16 is not shown in Figure 17 , and only the orthographic projection of the twelfth portion 63 on the substrate 16 is shown as a broken line in Figure 17 . Of course, it can also be an arc, or a connection of a broken line and an arc. This embodiment does not make specific limitations on this. Referring to Figure 17 , the twelfth portion 63 includes a connected first broken line 631 and a second broken line 632. One end of the first broken line 631 far from the second broken line 632 is connected to the eleventh portion 62, and one end of the second broken line 632 far from the first broken line 631 is connected to the thirteenth portion 64. The included angle between the first broken line 631 and the second broken line 632 is θ, 90° ≤ θ ≤ 180°. Usually, the eleventh portion 62 and the thirteenth portion 64 are on the same straight line. Along the second direction Y, the distance from the connection of the first broken line 631 and the second broken line 632 to the straight line where the eleventh portion 62 is located is less than or equal to 6 um. Therefore, by setting the width of the light-shielding portion 65 along the second direction Y to be greater than 6 um, it can be ensured that the light-shielding portion 65 covers the third signal line 61, avoiding incomplete occlusion of the third signal line 61 and affecting the display effect. Of course, the width of the light-shielding portion 65 along the second direction Y can be modified according to the shape or width of the third signal line 61. This embodiment does not make specific limitations on this.

[0120] In some alternative embodiments, continuing to refer to Figure 1 , the first signal line 11 is a data line, and the second signal line 12 is a power supply voltage signal line 10 or a sensing line.

[0121] It can be understood that the first signal line 11 is a data line for transmitting a data writing voltage to the sub-pixel 1; the second signal line 12 is a power supply voltage signal line 10, which is electrically connected to the common electrode 25. The common electrode 25 is reused as a touch electrode for realizing the touch function; the third signal line 61 is a sensing line, which is electrically connected to the common electrode 25 and can be used for fingerprint recognition.

[0122] Based on the same inventive concept, the present invention also provides a display device 200. Please refer to Figure 18 , Figure 18 which is a schematic structural diagram of the display device provided by the embodiment of the present invention. The display device 200 provided in this embodiment includes the display panel 100 in the above embodiment. Figure 18The embodiments are described by taking a mobile phone as an example for the display device 200. It can be understood that the display device 200 provided by the embodiments of the present invention can be other display devices 200 with a display function, such as a computer, a television, an electronic paper, a vehicle-mounted display device 200, etc. The present invention does not make specific limitations thereto. The display device 200 provided by the embodiments of the present invention has the beneficial effects of the display panel 100 provided by the embodiments of the present invention, and will not be elaborated herein again.

[0123] As can be seen from the above embodiments, the display panel provided by the present invention achieves at least the following beneficial effects:

[0124] In the display panel provided by the present invention, a sub-pixel column is provided between two adjacent first signal lines; the sub-pixels located in the first sub-pixel row are connected to the first signal line closest to the first edge of the sub-pixel along the first direction; the sub-pixels located in the second sub-pixel row are connected to the first signal line closest to the second edge of the sub-pixel along the first direction, forming a display panel with a zig-zag structure to reduce power consumption and improve the display effect of the display panel; a second signal line extends along the second direction, is located between the first sub-pixel column and the second sub-pixel column, and is on the same layer as the first signal line; the sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel is located in the first sub-pixel column and in the second sub-pixel row; the second sub-pixel is located in the second sub-pixel column and in the first sub-pixel row; the first signal line includes a first sub-signal line, the first sub-signal line is located between the first sub-pixel column and the second sub-pixel column, and the orthographic projection of the active layer of at least one first sub-pixel on the substrate overlaps at least partially with the orthographic projection of the second signal line on the substrate, and the orthographic projection of the active layer of at least one second sub-pixel on the substrate overlaps at least partially with the orthographic projection of the second signal line on the substrate; within a preset voltage range, the data writing voltages of at least one first sub-pixel and at least one second sub-pixel are equal. When the first sub-signal line is located between the first sub-pixel column and the second signal line, the orthographic projection of the active layer of the second sub-pixel on the substrate overlaps at least partially with the orthographic projection of the second signal line on the substrate, so a capacitor is formed between the active layer of the second sub-pixel and the second signal line, which will cause the data writing voltage of the second sub-pixel to decrease. By setting the orthographic projection of the active layer of the first sub-pixel on the substrate to overlap at least partially with the orthographic projection of the second signal line on the substrate, that is, extending the active layer of the first sub-pixel, a capacitor is formed between the active layer of the first sub-pixel and the second signal line, so that the data writing voltage of the first sub-pixel also decreases, realizing that within the preset voltage range, the data writing voltages of the first sub-pixel and the second sub-pixel are equal, avoiding display differences between the first sub-pixel and the second sub-pixel, and improving the display effect. Similarly, when the first sub-signal line is located between the second signal line and the second sub-pixel column, the orthographic projection of the active layer of the first sub-pixel on the substrate overlaps at least partially with the orthographic projection of the second signal line on the substrate, a capacitor is formed between the active layer of the first sub-pixel and the second signal line, causing the data writing voltage of the first sub-pixel to decrease. By setting the orthographic projection of the active layer of the second sub-pixel on the substrate to overlap at least partially with the orthographic projection of the second signal line on the substrate, that is, extending the active layer of the second sub-pixel, a capacitor is formed between the active layer of the second sub-pixel and the second signal line, so that the data writing voltage of the second sub-pixel also decreases, realizing that within the preset voltage range, the data writing voltages of the first sub-pixel and the second sub-pixel are equal, avoiding display differences between the first sub-pixel and the second sub-pixel, and improving the display effect.

[0125] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration purposes and not for limiting the scope of the present invention. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, Comprising: Sub-pixels arranged in an array, the sub-pixels including a first edge and a second edge oppositely arranged along a first direction, the sub-pixels being arranged along the first direction to form sub-pixel rows, the sub-pixels being arranged along a second direction to form sub-pixel columns, the first direction intersecting the second direction; the sub-pixel rows including a first sub-pixel row and a second sub-pixel row alternately arranged along the second direction, the sub-pixel columns including adjacent first sub-pixel columns and second sub-pixel columns; Also including a substrate; Multiple signal lines, located on one side of the substrate, the multiple signal lines including: Multiple first signal lines, arranged along the first direction and extending along the second direction, with one sub-pixel column provided between adjacent two of the first signal lines; the sub-pixels located in the first sub-pixel row are connected to the first signal line that is the closest to the first edge of the sub-pixel along the first direction; the sub-pixels located in the second sub-pixel row are connected to the first signal line that is the closest to the second edge of the sub-pixel along the first direction; A second signal line, extending along the second direction, located between the first sub-pixel column and the second sub-pixel column, and on the same layer as the first signal line; The sub-pixels include a first sub-pixel and a second sub-pixel, the first sub-pixel being located in the first sub-pixel column and in the second sub-pixel row; the second sub-pixel being located in the second sub-pixel column and in the first sub-pixel row; The first signal line includes a first sub-signal line, the first sub-signal line being located between the first sub-pixel column and the second sub-pixel column, the orthographic projection of the active layer of at least one of the first sub-pixels on the substrate at least partially overlaps with the orthographic projection of the second signal line on the substrate, and the orthographic projection of the active layer of at least one of the second sub-pixels on the substrate at least partially overlaps with the orthographic projection of the second signal line on the substrate; Within a preset voltage range, the data writing voltages of at least one of the first sub-pixels and at least one of the second sub-pixels are equal.

2. The display panel according to claim 1, wherein The length of the active layer of the first sub-pixel between the first sub-pixel column and the first sub-signal line is M, the length of the active layer of the second sub-pixel between the second sub-pixel column and the first sub-signal line is N, and within a preset length range, M = N.

3. The display panel according to claim 2, wherein The sub-pixels not connected to the first sub-signal line are connected with a compensation part, and within the preset voltage range, the data writing voltages of the sub-pixels are all equal.

4. A display panel, characterized in that, Comprising: Sub-pixels arranged in an array, the sub-pixels including a first edge and a second edge oppositely arranged along a first direction, the sub-pixels being arranged along the first direction to form sub-pixel rows, the sub-pixels being arranged along a second direction to form sub-pixel columns, the first direction intersecting the second direction; the sub-pixel rows including a first sub-pixel row and a second sub-pixel row alternately arranged along the second direction, the sub-pixel columns including adjacent first sub-pixel columns and second sub-pixel columns; Also including a substrate; Multiple signal lines, located on one side of the substrate, the multiple signal lines including: A plurality of first signal lines are arranged along the first direction and extend along the second direction. There is one sub-pixel column between adjacent two of the first signal lines; the sub-pixels located in the first sub-pixel row are connected to the first signal line that is closest to the first edge of the sub-pixel along the first direction; the sub-pixels located in the second sub-pixel row are connected to the first signal line that is closest to the second edge of the sub-pixel along the first direction; A second signal line extends along the second direction, is located between the first sub-pixel column and the second sub-pixel column, and is partially in the same layer as the first signal line; The sub-pixel includes a first sub-pixel and a second sub-pixel. The first sub-pixel is located in the first sub-pixel column and in the second sub-pixel row; the second sub-pixel is located in the second sub-pixel column and in the first sub-pixel row; the orthographic projection of the active layer of at least one first sub-pixel on the substrate does not overlap with the orthographic projection of the second signal line on the substrate, and the orthographic projection of the active layer of at least one second sub-pixel on the substrate does not overlap with the orthographic projection of the second signal line on the substrate; Within a preset voltage range, the data writing voltages of at least one first sub-pixel and at least one second sub-pixel are equal.

5. The display panel according to claim 4, wherein The orthographic projections of the active layers of all the first sub-pixels on the substrate do not overlap with the orthographic projection of the second signal line on the substrate, and the orthographic projections of the active layers of all the second sub-pixels on the substrate do not overlap with the orthographic projection of the second signal line on the substrate.

6. The display panel according to claim 5, wherein The first signal line includes a first sub-signal line. The first sub-signal line is located between the first sub-pixel column and the second sub-pixel column. The first sub-signal line includes alternately connected first parts and second parts. The first parts are located in the first sub-pixel row, and the second parts are located in the second sub-pixel row; The first part is located between the second signal line and the second sub-pixel column. The second part includes sequentially connected first sub-parts, second sub-parts, third sub-parts, and fourth sub-parts. The first sub-parts and the fourth sub-parts are located between the second signal line and the second sub-pixel column. The connection of the second sub-parts and the third sub-parts is located between the first sub-pixel column and the second signal line.

7. The display panel according to claim 6, wherein It further includes a metal film layer located on one side of the substrate; The metal film layer includes a first metal layer and a second metal layer. The second metal layer is located on the side of the first metal layer away from the substrate. The second sub-parts and the third sub-parts are located in the first metal layer. The first parts, the first sub-parts, the fourth sub-parts, and the second signal line are located in the second metal layer.

8. The display panel according to claim 5, wherein The first signal line includes a first sub-signal line. The first sub-signal line is located between the first sub-pixel column and the second sub-pixel column. The first sub-signal line includes alternately connected third parts and fourth parts. The third parts are located in the first sub-pixel row, and the fourth parts are located in the second sub-pixel row; The third part is located between the second signal line and the second sub-pixel column. The fourth part includes a fifth sub-part, a sixth sub-part, and a seventh sub-part connected in sequence. The sixth sub-part is located between the first sub-pixel column and the second signal line.

9. The display panel according to claim 8, wherein The second signal line includes a fifth part and a sixth part connected alternately. The fifth part is located in the first sub-pixel row, and the sixth part is located in the second sub-pixel row. The sixth part includes an eighth sub-part, a ninth sub-part, and a tenth sub-part connected in sequence. The ninth sub-part is located between the second sub-pixel column and the sixth sub-part. The width of the eighth sub-part is R, the width of the ninth sub-part is S, and the width of the tenth sub-part is T, where R < S and T < S.

10. The display panel according to claim 8, wherein, It further includes a metal film layer located on one side of the substrate. The metal film layer includes a first metal layer and a second metal layer. The second metal layer is located on the side of the first metal layer away from the substrate. The fifth sub-part and the seventh sub-part are located on the first metal layer, and the third part, the sixth sub-part, and the second signal line are located on the second metal layer.

11. The display panel according to claim 5, wherein The first signal line includes a first sub-signal line located between the first sub-pixel column and the second sub-pixel column. The second signal line includes a seventh part and an eighth part connected alternately. The seventh part is located in the first sub-pixel row, and the eighth part is located in the second sub-pixel row. The seventh part is located between the first sub-signal line and the first sub-pixel column. The eighth part includes an eleventh sub-part, a twelfth sub-part, a thirteenth sub-part, and a fourteenth sub-part connected in sequence. The eleventh sub-part and the fourteenth sub-part are located between the first sub-signal line and the first sub-pixel, and the connection between the twelfth sub-part and the thirteenth sub-part is located between the first sub-signal line and the second sub-pixel column.

12. The display panel according to claim 11, wherein, It further includes a metal film layer located on one side of the substrate. The metal film layer includes a first metal layer and a second metal layer. The second metal layer is located on the side of the first metal layer away from the substrate. The twelfth sub-part and the thirteenth sub-part are located on the first metal layer, and the seventh part, the eleventh sub-part, the fourteenth sub-part, and the first sub-signal line are located on the second metal layer.

13. The display panel according to claim 5, characterized in that, The first signal line includes a first sub-signal line located between the first sub-pixel column and the second sub-pixel column. The second signal line includes a ninth part and a tenth part connected alternately. The ninth part is located in the first sub-pixel row, and the tenth part is located in the second sub-pixel row. The ninth part is located between the first sub-signal line and the first sub-pixel column. The tenth part includes a fifteenth sub-part, a sixteenth sub-part, and a seventeenth sub-part connected in sequence. The sixteenth sub-part is located between the second sub-pixel column and the first sub-signal line.

14. The display panel according to claim 13, characterized in that, It further includes a metal film layer located on one side of the substrate. The metal film layer includes a first metal layer and a second metal layer. The second metal layer is located on a side of the first metal layer away from the substrate. The fifteenth sub - part and the seventeenth sub - part are located in the first metal layer, and the ninth part, the sixteenth sub - part and the first sub - signal line are located in the second metal layer.

15. The display panel according to claim 5, wherein, It further includes a third signal line arranged along the second direction, which includes an eleventh part, a twelfth part and a thirteenth part sequentially connected along the first direction. The eleventh part and the thirteenth part extend along the first direction, and the third signal line is correspondingly arranged with the sub - pixel row. The orthographic projection of the twelfth part on the substrate overlaps at least partially with the orthographic projection of the second signal line on the substrate, and the twelfth part protrudes towards the nearest first sub - pixel row.

16. The display panel according to claim 15, wherein It further includes a light - shielding part extending along the first direction, and the light - shielding part is correspondingly arranged with the third signal line. The orthographic projection of the third signal line on the substrate is within the orthographic projection range of the light - shielding part on the substrate. Along the second direction, the width of the light - shielding part is greater than 6um.

17. The display panel according to claim 4, wherein The first signal line is a data line, and the second signal line is a power supply voltage signal line or a sensing line.

18. A display device, characterized in that, It includes the display panel according to any one of claims 1 to 17 above.

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