Controller and control method for quasi-resonant controlled switching converter

Abstract

The present invention discloses a controller and a control method for a quasi-resonant control switching converter, wherein the switching converter includes an energy storage element and a power switch, and the controller includes a time sampling circuit, a first conversion unit, an opening enabling circuit, a second conversion unit, and a logic circuit. The time sampling circuit samples the time interval between a first time point and a second time point in real time. The first conversion unit provides a control voltage proportional to the time interval. The opening enabling circuit provides an opening enabling signal corresponding to a target number of valleys for valley conduction of the power switch. The second conversion unit provides a delayed enabling signal, wherein the delayed enabling signal has a first time delay relative to the opening enabling signal, and the first time delay is proportional to the control voltage output by the first conversion unit. The logic circuit controls the power switch to conduct based on the delayed enabling signal. By adopting the embodiments of the present invention, valley conduction can still be effectively guaranteed in mass production.

Description

Technical Field

[0001] The present invention relates to an electronic circuit, and in particular to a controller and a control method for a quasi-resonant controlled switching converter. Background Art

[0002] Quasi-resonant flyback converters are widely used in low-power applications. In quasi-resonant control, the flyback converter operates in critical mode. When the current flowing through the energy storage element drops to zero, the parasitic capacitance of the energy storage element and the power switch begins to resonate. When the resonant voltage across the power switch is at its minimum voltage value, the main switch is turned on (usually called valley switching), thereby reducing switching losses.

[0003] Figure 1 is a circuit diagram of the resonant flyback converter 100. Figure 1 As shown, the quasi-resonant switching converter 100 includes a transformer T, a power switch MP coupled to the primary winding of the transformer T, a diode D0, an output capacitor Co, and a controller. The controller has a ZCD pin, a current detection pin CS, a power switch drive pin DRV, a zero-crossing comparison circuit 101, a delay circuit 102, a current comparison circuit 103, and a logic circuit 104.

[0004] Figure 2 for Figure 1 The working waveform diagram of the switching converter 100 is shown in FIG. Figure 1 and Figure 2 As shown, the zero-crossing comparison circuit 101 detects the voltage V across the power switch MP through the ZCD pin. DS Whether it crosses zero, and when the zero crossing point is detected (for example Figure 2 After the time t1 shown in the figure, the delay circuit 102 adds a fixed delay t QR_Delay (e.g. 200nS), or add a fixed capacitor to the ZCD pin (e.g. Figure 1 The current comparison circuit 103 compares the current detection signal representing the current flowing through the power switch MP with the first threshold voltage, and generates a shutdown control signal S_off at the output terminal to control the shutdown of the power switch MP. The logic circuit 104 generates a control signal at the output terminal to control the conduction and shutdown of the power switch MP based on the conduction control signal S_on and the shutdown control signal S_off.

[0005] Figure 1The fixed delay method for valley conduction is feasible during the early stage of product development. However, in the mass production stage, due to the change in the distribution of transformer inductance parameters (about 3%), the parasitic junction capacitance of the power switch tube and the parasitic junction capacitance of the secondary freewheeling tube D0 (about 1%), the distribution of the oscillation period after the demagnetization of the product will be very wide. If the fixed delay solution described above is adopted, the power switch tube in some products cannot be effectively turned on at the valley bottom, resulting in quasi-resonance failure, thereby causing damage to efficiency and resulting in a higher defective rate of the product. Summary of the invention

[0006] The purpose of the present invention is to solve the above problems in the prior art and to provide an improved controller and control method for a quasi-resonant controlled switching converter.

[0007] According to an embodiment of the present invention, a controller for a switching converter for quasi-resonant control includes an energy storage element and a power switch, and the controller includes: a sampling and holding circuit, coupled to a detection circuit to receive a voltage detection signal representing the voltage across the power switch, and providing a platform voltage representing the maximum value of the voltage detection signal when the sampling and holding signal is valid; a first voltage divider circuit, coupled to the sampling and holding circuit to receive the platform voltage, and providing a first divided voltage at the output end based on the platform voltage; a timing circuit, providing a duration detection signal at the output end, wherein the timing circuit starts timing from a first time point when the voltage detection signal decreases to the first divided voltage, and ends when the voltage detection signal decreases to a zero-crossing threshold voltage The timing ends at a second time point, and the time interval between the first time point and the second time point is the pulse width of the time detection signal; a first conversion unit, in response to the time detection signal, provides a control voltage proportional to the time interval; an enable circuit, provides an enable signal corresponding to a target number of valleys for valley conduction of the power switch; a second conversion unit, receives the enable signal and the control voltage output by the first conversion unit, and provides a delayed enable signal at an output end, wherein the delayed enable signal has a first time delay relative to the enable signal, and the first time delay is proportional to the control voltage; and a logic circuit, receives the delayed enable signal, and controls the conduction of the power switch based on the delayed enable signal.

[0008] According to another embodiment of the present invention, a controller for a switching converter for quasi-resonant control includes an energy storage element, a power switch, and an auxiliary switch. The controller includes: a sampling and holding circuit, coupled to the detection circuit to receive a voltage detection signal representing the voltage across the power switch, and providing a platform voltage representing the maximum value of the voltage detection signal when the sampling and holding signal is valid; a first voltage divider circuit, coupled to the sampling and holding circuit to receive the platform voltage, and providing a first divided voltage at the output end based on the platform voltage; a timing circuit, providing a duration detection signal at the output end, wherein the timing circuit starts timing from a first time point when the voltage detection signal decreases to the first divided voltage, and ends timing at a second time point when the voltage detection signal decreases to a zero-crossing threshold voltage, and the first time point is equal to the time point when the voltage detection signal decreases to the zero-crossing threshold voltage. The time interval between the second time points is the pulse width of the time detection signal; the first conversion unit, in response to the time detection signal, provides a control voltage proportional to the time interval; the auxiliary turn-on enable circuit provides an auxiliary turn-on enable signal corresponding to the target number of valleys for valley conduction of the auxiliary switch; the second conversion unit receives the auxiliary turn-on enable signal and the control voltage output by the first conversion unit, and provides a delayed enable signal at the output end, wherein the delayed enable signal has a first time delay relative to the auxiliary turn-on enable signal, and the first time delay is proportional to the control voltage; the first logic circuit receives the delayed enable signal and controls the conduction of the auxiliary switch based on the delayed enable signal; and the second logic circuit outputs a conduction control signal to turn on the power switch after the auxiliary switch is turned off.

[0009] According to an embodiment of the present invention, a control method for a quasi-resonant switching converter is provided. The switching converter includes an energy storage element and a power switch coupled to the energy storage element. The control method includes: providing a voltage detection signal representing the voltage across the power switch; providing a platform voltage representing the maximum value of the voltage detection signal when the sample and hold signal is valid; dividing the platform voltage to provide a first divided voltage; determining a first time point when the voltage detection signal decreases to the first divided voltage; determining a second time point when the voltage detection signal decreases to a zero-crossing threshold voltage; in response to a time interval between the first time point and the second time point, providing a control voltage proportional to the time interval; providing an on-enable signal corresponding to a target number of valleys for valley conduction of the power switch; providing a delayed enable signal based on the on-enable signal and the control voltage, wherein the delayed enable signal has a first time delay relative to the on-enable signal, and the first time delay is proportional to the control voltage; and turning on the power switch based on the delayed enable signal.

[0010] In an embodiment of the present invention, the time interval between the first time point and the second time point is sampled, and the first conversion unit converts the time interval into a control voltage. Then, when the turn-on enable signal is valid, the second conversion unit converts the control voltage into a first time delay to control the power switch to achieve true valley bottom conduction. In addition, when the switching converter adopts quasi-resonant zero voltage control, when the auxiliary turn-on enable signal is valid, the control voltage is converted into the first time delay to control the valley bottom conduction of the auxiliary switch, and then after the auxiliary switch is turned off, the power switch is controlled to achieve zero voltage conduction. Through the present invention, the existing parameter distribution fluctuation problem can be effectively solved in mass production, and valley bottom conduction and / or zero voltage conduction can be truly achieved in real time. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic block diagram of a quasi-resonant controlled switching converter 100;

[0012] Figure 2 for Figure 1 The working waveform diagram of the switching converter 100 is shown;

[0013] Figure 3 is a circuit diagram of a quasi-resonant controlled switching converter 200 according to an embodiment of the present invention;

[0014] Figure 4 According to an embodiment of the present invention Figure 2 The circuit diagram of the duration sampling circuit 20A shown;

[0015] Figure 5 is a circuit diagram of a first conversion unit 204A and a second conversion unit 206A according to an embodiment of the present invention;

[0016] Figure 6 is a circuit diagram of an enable circuit 205A according to an embodiment of the present invention;

[0017] Figure 7 According to an embodiment of the present invention Figure 6 The operation waveform diagram of the turn-on enabling circuit 205A shown;

[0018] Figure 8 According to an embodiment of the present invention Figure 3 The working waveform diagram of the switching converter 200 is shown;

[0019] Fig. 9 is a flow chart of a control method 300 for a quasi-resonant switching converter according to an embodiment of the present invention;

[0020] Fig.10 is a circuit schematic diagram of a quasi-resonant zero-voltage controlled switching converter 400 according to an embodiment of the present invention;

[0021] Fig.11 According to an embodiment of the present invention Fig.10 The operating waveform diagram of the switching converter 400 is shown.

[0022] Fig.12 FIG. 6 is a flow chart of a control method 600 for a quasi-resonant switching converter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present invention. However, it is obvious to those of ordinary skill in the art that these specific details do not have to be used to implement the present invention. In other examples, in order to avoid confusing the present invention, known circuits, materials or methods are not specifically described.

[0024] Throughout the specification, reference to "one embodiment", "embodiment", "one example" or "example" means that a particular feature, structure or characteristic described in conjunction with the embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment", "in an embodiment", "one example" or "example" that appear in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, specific features, structures or characteristics can be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it should be understood by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes, and the drawings are not necessarily drawn to scale. It should be understood that when an element is said to be "connected to" or "coupled to" another element, it can be directly connected or coupled to another element or there can be an intermediate element. On the contrary, when an element is said to be "directly connected to" or "directly coupled to" another element, there is no intermediate element. The same reference numerals indicate the same element. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0025] Figure 3 FIG. 2 is a schematic block diagram of a quasi-resonant controlled switching converter 200 according to an embodiment of the present invention. Figure 3 As shown, the switching converter 200 includes a transformer T1, a power switch M1 coupled to the primary winding of the transformer T1, a diode D0, an output capacitor Co, and a controller. The controller includes a time sampling circuit 20, a first conversion unit 204, an enable circuit 205, a second conversion unit 206, a current comparison circuit 207, and a logic circuit 208.

[0026] In one embodiment, the switching converter 200 further includes a detection circuit 209. Figure 3 In the embodiment shown, the detection circuit 209 is coupled to an auxiliary winding of the transformer T1 and generates a voltage detection signal V according to a voltage VAUX across the auxiliary winding. ZCD In one embodiment, the detection circuit 209 includes a resistor voltage divider circuit coupled to the auxiliary winding. In another embodiment, the detection circuit 209 is directly coupled to the power switch M1 to detect the voltage V across the power switch M1. DS Detection is performed to provide a voltage V representing the voltage across the power switch M1 DS The voltage detection signal V ZCD .

[0027] exist Figure 3 In the embodiment shown, the duration sampling circuit 20 is used to sample the duration interval TD1 between the first time point and the second time point. Figure 3 As shown, the duration sampling circuit 20 includes a sampling and holding circuit 201, a first voltage dividing circuit 202 and a timing circuit 203. The sampling and holding circuit 201 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the detection circuit 209 to receive the current detection signal V ZCD When the sample-and-hold signal S / H is valid, the sample-and-hold circuit 201 provides a representative voltage detection signal V ZCD In one embodiment, after the power switch M1 is turned off, a blanking time T is counted. blank After that, the sample and hold signal S / H is valid.

[0028] The first voltage divider circuit 202 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the sample and hold circuit 201 to receive the platform voltage ZCD_P. Based on the platform voltage ZCD_P, the first voltage divider circuit 202 provides a first divided voltage ZCD_D at the output terminal. In one embodiment, the first divided voltage ZCD_D is proportional to the platform voltage ZCD_P. In one embodiment, ZCD_D=0.9*ZCD_P. The timing circuit 203 is used to provide a duration detection signal TDS at the output terminal, wherein the timing circuit 203 is based on the voltage detection signal V ZCD The timing starts from the first time point when the voltage detection signal V ZCD The timing is ended at the second time point when the voltage decreases to the zero-crossing threshold voltage ZCD_TH, and the time interval TD1 between the first time point and the second time point is the pulse width of the time detection signal TDS.

[0029] The first conversion unit 204 has an input terminal and an output terminal, wherein the input terminal receives the time detection signal TDS, and in response to the time detection signal TDS, the first conversion unit 204 provides a control voltage V proportional to the time interval TD1 at the output terminal. C2 The turn-on enable circuit 205 provides a turn-on enable signal ZCD_locked corresponding to the target valley number Valley_T of valley conduction of the power switch M1 based on the operation of the switching converter 200. The second conversion unit 206 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the first conversion unit to receive the control voltage V C2 The second input terminal is coupled to the lock-on enable circuit 205 to receive the lock-on enable signal ZCD_locked, based on the control voltage V C2 and the turn-on enable signal ZCD_locked, the second conversion unit provides a delay enable signal DRV_on at the output terminal. The delay enable signal DRV_on has a first time delay TD2 relative to the turn-on enable signal ZCD_locked, and the first time delay TD2 is related to the control voltage V C2 In one embodiment, when the difference between the target valley number and the current valley number decreases to 1, that is, the current valley number is about to reach the target valley number, the detection voltage detection signal V ZCD are all reduced to the zero-crossing threshold voltage ZCD_TH, and when the voltage detection signal V ZCD When the voltage decreases to the zero-crossing threshold voltage ZCD_TH, the turn-on enable signal ZCD_locked is valid. The current comparison circuit 207 compares the current detection signal representing the current flowing through the power switch M1 with the first threshold voltage, and generates a shutdown control signal DRV_off at the output terminal to control the shutdown of the power switch M1. The logic circuit 208 generates a control signal DRV at the output terminal based on the delayed enable signal DRV_on and the shutdown control signal DRV_off to control the conduction and shutdown of the power switch MP.

[0030] exist Figure 3 In the embodiment shown, the time interval TD1 between the first time point and the second time point is sampled in real time, and the first conversion unit 204 converts the time interval TD1 into the control voltage V C2 Then, when the enable signal ZCD_locked is valid, the second conversion unit 206 converts the control voltage V C2 The first time delay TD2 is converted to control the power switch M1 to achieve true and real-time valley conduction.

[0031] Figure 4 According to an embodiment of the present invention Figure 2 The circuit diagram of the time sampling circuit 20A is shown in FIG. Figure 4In the illustrated embodiment, the duration sampling circuit 20A includes a sample-and-hold circuit 201A, a first voltage divider circuit 202A, and a timing circuit 203A.

[0032] like Figure 4 As shown, the sampling and holding circuit 201A is used to sample and hold the voltage V representing the two ends of the power switch M1 during the off period of the power switch M1. DS In one embodiment, when the power switch M1 is turned off and a blanking time T is delayed, blank After that, the sampling and holding signal S / H is valid, and the voltage detection signal V ZCD Perform sampling and holding to provide a platform voltage ZCD_P. Figure 4 In the embodiment shown, the sample-and-hold circuit 201A includes an operational amplifier 211, a unidirectional device D1, a capacitor C1, and a switch S1. The operational amplifier 211 has a non-inverting input terminal, a reverse input terminal, and an output terminal, wherein the non-inverting input terminal is coupled to the detection circuit 209 to receive the voltage detection signal V ZCD , the output end is coupled to the input end of the unidirectional device D1, the output end of the unidirectional device D1 is coupled to the first end of the capacitor C1, and the second end of the capacitor C1 is grounded. The switch S1 is connected in parallel to both ends of the capacitor C1, and its control end receives the sampling and holding signal S / H. The inverting input end of the operational amplifier 211 is coupled to the first end of the capacitor C1. When the sampling and holding signal S / H is valid, the switch S1 is disconnected, and the operational amplifier 211 charges the capacitor C1 through the unidirectional device D1 to convert the voltage detection signal V ZCD The value of is maintained on capacitor C1. When the power switch M1 is turned on, switch S1 will be turned on, and the voltage on capacitor C1 will be reset to zero until the next cycle of the sampling and holding signal S / H comes and the voltage detection signal V is detected again. ZCD Perform sample and hold.

[0033] In one embodiment, the unidirectional device D1 includes a diode. In another embodiment, the unidirectional device D1 includes a transistor. The transistor has a base, a collector, and an emitter, wherein the base and the collector are coupled to the output terminal of the operational amplifier 211, and the emitter is coupled to the first terminal of the capacitor C1.

[0034] The first voltage divider circuit 202A is coupled to the output terminal of the sample and hold circuit 201A to receive the platform voltage ZCD_P, and provides a first divided voltage ZCD_D at the output terminal based on the platform voltage ZCD_P. Figure 4 In the illustrated embodiment, the first voltage divider circuit 202A includes an operational amplifier 212 and a resistor voltage divider circuit composed of resistors R1 and R2.

[0035] The timing circuit 203A includes a first time point determination circuit 213, a second time point determination circuit 204, and a timing logic circuit 215. The first time point determination circuit 213 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a voltage detection signal V ZCD , the second input terminal is coupled to the first voltage divider circuit 202A to receive the first divided voltage ZCD_D, and the first comparison signal CP1 is provided at the output terminal. In one embodiment, the first time point determination circuit 213 includes a comparator COM1. The comparator COM1 has a non-inverting input terminal receiving the first divided voltage ZCD_D, and an inverting input terminal receiving the current detection signal V ZCD When the voltage detection signal V ZCD When the voltage decreases to the first divided voltage ZCD_D, the first comparison signal CP1 changes from a low level to a high level to indicate a first time point.

[0036] The second time point determination circuit 214 converts the voltage detection signal V ZCD Compared with the zero-crossing threshold voltage ZCD_TH, a second comparison signal CP2 is provided at the output terminal. Figure 4 In the illustrated embodiment, the second time point determination circuit 214 includes a comparator COM2. The inverting input terminal of the comparator COM2 receives the voltage detection signal V ZCD , the non-inverting input terminal receives the zero-crossing threshold voltage ZCD_TH. When the voltage detection signal V ZCD When the voltage decreases to the zero-crossing threshold voltage ZCD_TH, the second comparison signal CP2 changes from a low level to a high level to indicate a second time point.

[0037] The timing logic circuit 215 includes a flip-flop FF1. The flip-flop FF1 has a set terminal, a reset terminal and an output terminal, wherein the reset terminal receives the first comparison signal CP1, the set terminal receives the second comparison signal CP2, and the output terminal provides a time detection signal TDS. Figure 4 In the embodiment shown, the time interval TD1 between the first time point and the second time point is the pulse width of the time detection signal TDS maintaining a low level. In another embodiment, the time interval TD1 is the pulse width of the time detection signal TDS maintaining a high level.

[0038] Figure 5 FIG. 2 is a circuit diagram of a first conversion unit 204A and a second conversion unit 206A according to an embodiment of the present invention. Figure 5 In the embodiment shown, the first conversion unit 204A is a time-to-voltage converter. The first conversion unit 204A includes a first current source I1, a capacitor C2, a unidirectional device D2, and a switch S2. Figure 5As shown, the first current source I1 has a power supply terminal coupled to the power supply voltage VDD and an output terminal providing a first charging current. The capacitor C2 has a first terminal and a second terminal, wherein the second terminal is grounded. The unidirectional device D2 includes a transistor. The transistor has a base, a collector and an emitter, wherein the base and the collector are coupled to the output terminal of the first current source I1, and the emitter is coupled to the first terminal of the capacitor C2. The switch S2 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the output terminal of the first current source I1, the second terminal is grounded, and the control terminal receives the duration detection signal TDS. When the duration detection signal TDS is at a low level, the switch S2 remains in an off state, the unidirectional device D2 is in an on state, and the first current source I1 charges the capacitor C2 via the unidirectional device D2. That is, within the duration interval TD1 between the first time point and the second time point, the first current source I1 continuously charges the capacitor C2 to store the charge representing the duration interval TD1 on the capacitor C2. When the time detection signal TDS is at a high level, the switch S2 is turned on, the unidirectional device D2 remains in the off state because the base is pulled low, and the first current source I1 stops charging the capacitor C2. The voltage V across the capacitor C2 C2 As the control voltage is maintained. C2 Proportional to the duration interval TD1.

[0039] exist Figure 5 In the illustrated embodiment, the second conversion unit 206A is a voltage-time converter. The second conversion unit 206A includes a second current source I2, a capacitor C3, a switch S3, a trigger circuit 241, and a comparison circuit 242. The second current source I2 is coupled to the first current source I1, forming a mirror current source therewith, and providing a second charging current at the output end. In one embodiment, the first charging current is equal to the second charging current. In another embodiment, the first charging current is proportional to the second charging current. The capacitor C3 has a first end and a second end, wherein the first end is coupled to the output end of the second current source I2, and the second end is grounded.

[0040] The trigger circuit 241 includes a trigger FF2, which has a set terminal, a reset terminal and an output terminal, wherein the set terminal receives the turn-on enable signal ZCD_locked, and the reset terminal receives the delay enable signal DRV_on. The switch S3 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first terminal of the capacitor C3, the second terminal is grounded, and the control terminal is coupled to the output terminal of the trigger circuit 241. The comparison circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first terminal of the capacitor C3, the second input terminal is coupled to the output terminal of the first conversion unit 204A, and the delay enable signal DRV_on is provided at the output terminal.

[0041] In a further embodiment, the second conversion unit 206A further includes a second voltage divider circuit 240. The second voltage divider circuit 240 is used to shorten the first time delay TD2 to compensate for the transmission delay when the power switch M1 is turned on. The second voltage divider circuit 240 is coupled between the output terminal of the first conversion unit 204A and the second output terminal of the comparison circuit 242. The second voltage divider circuit 240 includes a buffer circuit 261 and a resistor voltage divider circuit 262, wherein the resistor voltage divider circuit 262 is composed of resistors R3 and R4. The buffer circuit 261 includes an operational amplifier to isolate the resistor voltage divider circuit 262 from the control voltage V C2 The resistor voltage divider circuit 262 is based on the isolated control voltage V C2 , providing a second divided voltage k*V at the output C2 The comparison circuit 242 includes a comparator CMP3. A non-inverting input terminal of the comparator CMP3 is coupled to a first terminal of the capacitor C3 to receive a voltage V C3 , the inverting input terminal is coupled to the output terminal of the second voltage divider circuit 240 to receive the second divided voltage k*V C2 , providing a delay enable signal DRV_on at the output end.

[0042] Figure 6 2 is a circuit diagram of an enable circuit 205A according to an embodiment of the present invention. The enable circuit 205A includes a valley pulse generating circuit 251 , a counter 252 , a target valley determining circuit 253 , a digital comparison circuit 254 and an AND gate circuit 255 .

[0043] exist Figure 6 In the illustrated embodiment, the valley pulse generating circuit 251 includes a valley comparison circuit 51, an inverter 52, an RS trigger 53, an AND gate circuit 54, and a single pulse circuit 55. The valley comparison circuit 51 has a non-inverting input terminal, a reverse input terminal, and an output terminal, wherein the non-inverting input terminal receives the voltage V across the power switch M1. DS , the inverting input terminal receives the valley reference signal ZCD_ref, based on the voltage V DS The valley comparison circuit 51 outputs a valley comparison signal VCP at the output terminal. Figure 4 The second time point determination circuit 214 shown in the figure may be used to replace the valley comparison signal VCP, and the second comparison signal CP2 may be multiplexed.

[0044] Continue as Figure 6As shown, the inverter 52 has an input terminal and an output terminal, wherein the input terminal receives the valley comparison signal VCP. The RS flip-flop 53 has a set terminal, a reset terminal and an output terminal, wherein the set terminal receives the valley comparison signal VCP, and the reset terminal receives the control signal DRV of the power switch M1. The AND gate circuit 54 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the inverter 52, and the second input terminal is coupled to the output terminal of the RS flip-flop 53. The single pulse circuit 55 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the AND gate 54, and the valley pulse signal VP is provided at the output terminal. When the switch voltage V DS When the voltage V is greater than the valley reference signal ZCD_ref, the valley comparison signal VCP has a high level, the output of the AND gate circuit 54 is a low level, the single pulse circuit 55 does not work, and does not output any pulse signal. DS When the control signal DRV comes, the RS trigger 53 is set, the output of the AND gate circuit 54 is low, and the single pulse circuit 55 stops working. The valley pulse generating circuit 251 is not limited to Figure 6 Any circuit known in the art that can detect the valley bottom of the resonant waveform and output a pulse signal at each valley bottom can be used as the valley pulse generating circuit.

[0045] The counter 252 has a clock terminal, a reset terminal and an output terminal, wherein the clock terminal is coupled to the output terminal of the valley pulse generating circuit 251 to receive the valley pulse signal VP, and the reset terminal receives the control signal DRV. Based on the valley pulse signal VP and the control signal DRV, the counter 252 outputs the valley count Valley_CNT at the output terminal.

[0046] The target valley number determination circuit 253 provides the target valley number Valley_T of the current cycle at the output end. The digital comparison circuit 254 compares the current valley number Valley_CNT with the target valley number Valley_T. When the difference between the target valley number Valley_T and the current valley number Valley_CNT decreases to 1, that is, the current valley number Valley_CNT is about to reach the target valley number Valley_T, the control gate circuit 255 outputs a valid pulse signal when the pulse of the next valley pulse signal VP comes, that is, the opening enable signal ZCD_locked is valid. When the output of the digital comparison circuit 254 remains at a low level, the AND gate circuit 255 shields the valley pulse signal VP. When the output of the digital comparison circuit 254 changes from a low level to a high level, the AND gate circuit 255 allows the valid pulse of the valley pulse signal VP to be transmitted to the output end to provide a valid opening enable signal ZCD_locked.

[0047] Figure 7 According to an embodiment of the present invention Figure 6 The operation waveform diagram of the turn-on enabling circuit 205A is shown in FIG. Figure 7 As shown, the waveforms from top to bottom are the control signal DRV, the voltage V across the power switch M1, DS , voltage detection signal V ZCD , valley comparison signal VCP, valley pulse signal VP, valley counting signal Valley_CNT, target valley number Valley_T and opening enable signal ZCD_locked. Figure 7 In the embodiment shown, the target valley number Valley_T is locked at the third valley. Before time t1, the valley pulse signal VP is shielded by the AND gate circuit 255. Until time t1, the current valley number Valley_CNT is updated to 2, the difference between the target valley number Valley_T and the current valley number Valley_CNT is reduced to 1, and the output of the digital comparison circuit 254 changes from a low level to a high level. Then at time t3, when the pulse signal of the valley pulse signal VP comes, the enable signal ZCD_locked is valid.

[0048] Figure 8 According to an embodiment of the present invention Figure 3 The working waveform diagram of the switching converter 200 is shown in FIG. Figure 8 As shown, at time t1, the power switch M1 is turned on. At time t2, the power switch M1 is turned off. After a blanking time T blank Then, at time t3, the sample-and-hold circuit 201A detects the voltage signal V ZCD The sampling and holding is performed (as shown at point A) to provide a platform voltage ZCD_P. At time t4, the voltage detection signal VZCD The first time point is determined, as shown at point B. The first current source I1 starts charging the capacitor C2, and the control voltage V C2 Start to grow.

[0049] At time t5, the voltage detection signal V ZCD The voltage V C2 is maintained. The time interval TD1 between the first time point and the second time point is shown in the figure. At the same time, at time t5, the enable signal ZCD_locked is valid, and the second current source I2 starts to charge the capacitor C3. The voltage V C3 At time t6, when the voltage V C3 Increase to the second divided voltage K*V C2 , the delay enable signal DRV_on is valid, the power switch M1 is turned on, the current cycle ends, and the switching converter 200 begins to enter the next cycle. There is a first time delay TD2 between the actual turn-on time of the power switch M1 and the turn-on enable signal ZCD_locked.

[0050] Continue as Figure 8 As shown, the time interval TD1 between the first time point t7 and the second time point t8 is sampled, and a control voltage V proportional to the time interval TD1 is provided. C2 Then at time t9, when the enable signal ZCD_locked is valid, the control voltage V C2 At time t10, when the first time delay TD2 ends, the power switch M1 is turned on.

[0051] Fig. 9It is a flow chart of a control method 300 for a quasi-resonant switching converter according to an embodiment of the present invention. The switching converter includes an energy storage element and a power switch coupled to the energy storage element, and the control method 300 includes steps 301 to 308. In step 301, a voltage detection signal representing the voltage across the power switch is provided. In step 302, a platform voltage representing the maximum value of the voltage detection signal is provided when the sampling and holding signal is valid. In step 303, the platform voltage is divided to provide a first divided voltage. And determine the first time point when the voltage detection signal decreases to the first divided voltage. In step 304, determine the second time point when the voltage detection signal decreases to the zero-crossing threshold voltage. In step 305, in response to the time interval between the first time point and the second time point, provide a control voltage proportional to the time interval. In step 306, provide an enable signal corresponding to the target number of valleys for valley conduction of the power switch. In step 307, based on the turn-on enable signal and the control voltage, a delayed enable signal is provided, wherein the delayed enable signal has a first time delay relative to the turn-on enable signal, and the first time delay is proportional to the control voltage. In step 308, the power switch is turned on based on the delayed enable signal.

[0052] In one embodiment, the method for providing the control voltage includes charging the first capacitor with a first charging current within the time interval. In a further embodiment, the method for providing the delayed enable signal includes: dividing the control voltage to provide a second divided voltage; when the turn-on enable signal is valid, charging the second capacitor with a second charging current, wherein the second charging current is proportional to the first charging current; comparing the voltage across the second capacitor with the second divided voltage, and providing the delayed enable signal according to the comparison result; and when the power switch is turned on, resetting the voltage across the second capacitor to zero.

[0053] Fig.10 FIG. 4 is a circuit diagram of a quasi-resonant zero voltage controlled switching converter 400 according to an embodiment of the present invention. Fig.10 As shown, the switching converter 400 includes a transformer T1, a power switch M1 coupled to the primary winding of the transformer T1, a diode D0, an output capacitor Co, and a controller. The controller includes a sample-and-hold circuit 401, a first voltage divider circuit 402, a timing circuit 403, a first conversion unit 404, an on-enabling circuit 405, a second conversion unit 406, a current comparison circuit 407, a first logic circuit 408, a conduction control circuit 409, a shutdown control circuit 410, and a second logic circuit 412.

[0054] In one embodiment, the switching converter 400 further includes a detection circuit 412. Fig.10In the embodiment shown, the detection circuit 412 is coupled to an auxiliary winding of the transformer T1 and generates a voltage detection signal V according to a voltage VAUX across the auxiliary winding. ZCD , to represent the voltage V across the power switch M1 DS .

[0055] The sample-and-hold circuit 401 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the detection circuit 412 to receive the current detection signal V ZCD When the sample-and-hold signal S / H is valid, the sample-and-hold circuit 401 provides a representative voltage detection signal V ZCD Maximum platform voltage ZCD_P.

[0056] The first voltage divider circuit 402 has an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the sample and hold circuit 401 to receive the platform voltage ZCD_P. Based on the platform voltage ZCD_P, the first voltage divider circuit 402 provides a first divided voltage ZCD_D at the output terminal. The timing circuit 403 is used to provide a time detection signal TDS at the output terminal, wherein the timing circuit 403 is based on the voltage detection signal V ZCD The timing starts from the first time point when the voltage detection signal V ZCD The timing is ended at the second time point when the voltage decreases to the zero-crossing threshold voltage ZCD_TH, and the time interval TD1 between the first time point and the second time point is the pulse width of the time detection signal TDS.

[0057] The first conversion unit 404 has an input terminal and an output terminal, wherein the input terminal receives the time detection signal TDS, and in response to the time detection signal TDS, the first conversion unit 404 provides a control voltage V proportional to the time interval TD1 at the output terminal. C2 The turn-on enable circuit 405 provides an auxiliary turn-on enable signal ZCD1_locked corresponding to the target valley number Valley_T of the valley conduction of the auxiliary switch M2 based on the operation of the switching converter 400. The second conversion unit 406 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the first conversion unit to receive the control voltage V C2 The second input terminal is coupled to the turn-on enable circuit 405 to receive the auxiliary turn-on enable signal ZCD1_locked, based on the control voltage V C2 and the auxiliary turn-on enable signal ZCD_locked, the second conversion unit provides a delayed enable signal DRV_on at the output terminal for controlling the auxiliary switch M2 to turn on. The delayed enable signal DRV_on has a first time delay TD2 relative to the auxiliary turn-on enable signal ZCD1_locked, and the first time delay TD2 is related to the control voltage V C2In one embodiment, when the difference between the target valley number and the current valley number decreases to 1, that is, when the current valley number is about to reach the target valley number, the detection voltage detection signal V ZCD Whether it decreases to the zero-crossing threshold voltage ZCD_TH, and when the voltage detection signal V ZCD When the auxiliary switch M2 is reduced to the zero-crossing threshold voltage ZCD_TH, the auxiliary turn-on enable signal ZCD1_locked is valid. The current comparison circuit 407 compares the current detection signal representing the current flowing through the auxiliary switch M2 with the second threshold voltage, and generates a shutdown control signal DRVA_off at the output terminal to control the shutdown of the auxiliary switch M2. The first logic circuit 408 generates a control signal DRVA at the output terminal to control the conduction and shutdown of the auxiliary switch M2 based on the delayed enable signal DRVA_on and the shutdown control signal DRVA_off. The conduction control circuit 409 receives the shutdown control signal DRVA_off, and after detecting that the auxiliary switch M2 is turned off, provides a conduction control signal DRV_ON to the second logic circuit 411 to control the conduction of the power switch M1. The shutdown control circuit 410 provides a shutdown control signal DRV_OFF to the second logic circuit 411 to control the shutdown of the power switch M1.

[0058] exist Fig.10 In the embodiment shown, the switching converter 400 adopts quasi-resonant zero voltage control. By real-time sampling of the time interval TD1 between the first time point and the second time point, the first conversion unit 404 converts the time interval TD1 into a control voltage V C2 Then, when the auxiliary opening enable signal ZCD_locked is valid, the second conversion unit 406 converts the control voltage V C2 is converted into the first time delay TD2 to control the auxiliary switch M2 to be valley-turned on. Then, after the auxiliary switch M2 is turned off, the voltage V DS When the voltage is reduced to the minimum value, the power switch M1 is controlled to realize zero voltage conduction. The present invention can effectively solve the existing parameter distribution fluctuation problem in mass production, and truly realize valley bottom conduction and zero voltage conduction in real time.

[0059] Fig.11 According to an embodiment of the present invention Fig.10 The working waveform diagram of the switching converter 400 is shown in FIG. Fig.11As shown, at time t1, a cycle begins and the power switch M1 is turned on. At time t2, the power switch M1 is turned off. At time t3, the sample and hold circuit 401 samples and holds the maximum value of the voltage detection signal VZCD to provide a platform voltage ZCD_P. At time t4, the first time point is determined, as shown at point B. Starting from time t4, the capacitor C2 is charged until time t5, when the second time point is determined, and the charging of the capacitor C2 stops. The charge related to the time interval TD1 is stored on the capacitor C2. At time t6, the auxiliary turn-on enable signal ZCD1_locked is valid, and the capacitor C3 is charged. Until time t7, the voltage V C3 Reach the second divided voltage K*V C2 At t8, the auxiliary switch M2 is turned off. At t9, when the auxiliary switch M2 is turned off and the voltage V DS When it decreases to its minimum value, the power switch M1 is turned on by zero voltage. One cycle ends and a new cycle begins. Fig.11 As shown, the zero voltage turn-on of the power switch M1 has a second time delay TD3 relative to the turn-off of the auxiliary switch M2 .

[0060] Fig.12 The flowchart of the control method 600 for a quasi-resonant switching converter according to an embodiment of the present invention is shown. The switching converter includes an energy storage element and a power switch and an auxiliary switch coupled to the energy storage element. The control method 600 includes steps 601 to 609. In step 601, a voltage detection signal representing the voltage across the power switch is provided. In step 602, a platform voltage representing the maximum value of the voltage detection signal is provided when the sampling and holding signal is valid. In step 603, the platform voltage is divided to provide a first divided voltage. And determine the first time point when the voltage detection signal decreases to the first divided voltage. In step 604, determine the second time point when the voltage detection signal decreases to the zero-crossing threshold voltage. In step 605, in response to the time interval between the first time point and the second time point, provide a control voltage proportional to the time interval. In step 606, provide an auxiliary turn-on enable signal corresponding to the target number of valleys for valley conduction of the auxiliary switch. In step 607, based on the auxiliary turn-on enable signal and the control voltage, a delayed enable signal is provided, wherein the delayed enable signal has a first time delay relative to the auxiliary turn-on enable signal, and the first time delay is proportional to the control voltage. In step 608, the auxiliary switch is turned on based on the delayed enable signal. In step 609, when the auxiliary switch is turned off and the voltage across the power switch reaches its minimum value, the power switch is turned on.

[0061] Note that in the flowchart described above, the functions marked in the blocks may also occur in an order different from that shown in the figure. For example, two blocks represented in succession may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the specific functions involved.

[0062] In the specification and claims of the present application, relevant terms such as first and second, etc. may be used only to distinguish one entity or action from another entity or action, without necessarily or implying the existence of such an order between these entities or actions. Numerical sequences such as first, second and third, etc., refer only to different individuals in a plurality and do not imply any order or sequence unless specifically defined in the claim language. The order of the text in any claim does not mean that the processing steps must be performed in such an order or logical order unless specifically defined in the claim language. Without departing from the scope of the present invention, these processing steps may be interchanged in any order, as long as such interchange does not cause the claim language to contradict and does not appear logically absurd.

[0063] Although the switching converters in the aforementioned embodiments are all based on flyback as an example, those skilled in the art will appreciate that the switching converters may also be based on other DC converters that can operate in quasi-resonance. Other converters using quasi-resonance control, whether isolated or non-isolated, are also applicable to the present invention. In addition, it should be noted that the turn-on enable signal of the present invention may be a synchronization signal received from the secondary side through an isolation circuit to control the conduction of the primary side.

[0064] Although the present invention has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present invention can be embodied in a variety of forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A controller for a quasi-resonant controlled switching converter, the switching converter comprising an energy storage element and a power switch coupled to the energy storage element, the controller comprising: A sampling and holding circuit is coupled to the detection circuit to receive a voltage detection signal representing the voltage across the power switch, and provides a platform voltage representing the maximum value of the voltage detection signal when the sampling and holding signal is valid; A first voltage divider circuit is coupled to the sample-and-hold circuit to receive the platform voltage and provide a first divided voltage at an output terminal based on the platform voltage; A timing circuit, providing a duration detection signal at an output terminal, wherein the timing circuit starts timing from a first time point when the voltage detection signal decreases to a first divided voltage, and ends timing at a second time point when the voltage detection signal decreases to a zero-crossing threshold voltage, and the duration interval between the first time point and the second time point is a pulse width of the duration detection signal; A first conversion unit, in response to the duration detection signal, provides a control voltage proportional to the duration interval; The turn-on enabling circuit provides a turn-on enabling signal corresponding to a target number of valleys for valley conduction of the power switch; a second conversion unit, receiving the on-enable signal and the control voltage output by the first conversion unit, and providing a delayed enable signal at an output terminal, wherein the delayed enable signal has a first time delay relative to the on-enable signal, and the first time delay is proportional to the control voltage; and The logic circuit receives the delayed enable signal and controls the power switch to be turned on based on the delayed enable signal.

2. The controller of claim 1, wherein the timing circuit comprises: A first time point determination circuit compares the voltage detection signal with the first divided voltage and provides a first comparison signal at an output terminal; A second time point determination circuit compares the voltage detection signal with the zero-crossing threshold voltage and provides a second comparison signal at an output terminal; as well as The timing logic circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives a second comparison signal, the second input terminal receives a second comparison signal, and the output terminal provides a duration detection signal.

3. The controller as claimed in claim 1, wherein a blanking time is started to be counted after the power switch is turned off, and after the blanking time is over, the sampling and holding signal is valid.

4. The controller according to claim 1, wherein the first conversion unit comprises: A first current source having a power supply terminal coupled to a power supply voltage and an output terminal providing a first charging current; A first capacitor having a first end and a second end, wherein the second end is grounded; A first transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal and the control terminal are coupled to the output terminal of the first current source, and the second terminal is coupled to the first terminal of the first capacitor; as well as The first switch has a first end, a second end and a control end, wherein the first end is coupled to the output end of the first current source, the second end is grounded, and the control end receives a duration detection signal.

5. The controller according to claim 4, wherein the second conversion unit comprises: A second current source is coupled to the first current source to form a mirror current source therewith, and provides a second charging current at an output end; A second capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the output terminal of the second current source and the second terminal is grounded; A trigger circuit has a set terminal, a reset terminal and an output terminal, wherein the set terminal receives an enable signal, and the reset terminal receives a delay enable signal; A second switch having a first end, a second end and a control end, wherein the first end is coupled to the first end of the second capacitor, the second end is grounded, and the control end is coupled to the output end of the trigger circuit; as well as The comparison circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first terminal of the second capacitor, the second input terminal is coupled to the output terminal of the first conversion unit, and a delay enable signal is provided at the output terminal.

6. The controller as claimed in claim 5, wherein the second conversion unit further comprises a second voltage divider circuit coupled between the output terminal of the first conversion unit and the second input terminal of the comparison circuit, the second voltage divider circuit comprising: A buffer circuit having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the first conversion unit to receive a control voltage; as well as The second voltage divider circuit divides the control voltage and provides a second divided voltage at an output terminal to a second input terminal of the comparison circuit. 7 . The controller of claim 1 , wherein when the difference between the target valley number and the current valley number decreases to 1, and the voltage detection signal decreases to a zero-crossing threshold voltage, the turn-on enable signal is valid.

8. A controller for a quasi-resonant controlled switching converter, the switching converter comprising an energy storage element and a power switch and an auxiliary switch coupled to the energy storage element, the controller comprising: A sampling and holding circuit is coupled to the detection circuit to receive a voltage detection signal representing the voltage across the power switch, and provides a platform voltage representing the maximum value of the voltage detection signal when the sampling and holding signal is valid; A first voltage divider circuit is coupled to the sample-and-hold circuit to receive the platform voltage and provide a first divided voltage at an output terminal based on the platform voltage; A timing circuit, providing a duration detection signal at an output terminal, wherein the timing circuit starts timing from a first time point when the voltage detection signal decreases to a first divided voltage, and ends timing at a second time point when the voltage detection signal decreases to a zero-crossing threshold voltage, and the duration interval between the first time point and the second time point is a pulse width of the duration detection signal; A first conversion unit, in response to the duration detection signal, provides a control voltage proportional to the duration interval; an auxiliary turn-on enabling circuit, providing an auxiliary turn-on enabling signal corresponding to a target number of valleys for valley conduction of the auxiliary switch; a second conversion unit, receiving the auxiliary opening enable signal and the control voltage output by the first conversion unit, and providing a delay enable signal at an output terminal, wherein the delay enable signal has a first time delay relative to the auxiliary opening enable signal, and the first time delay is proportional to the control voltage; A first logic circuit receives a delay enable signal and controls the auxiliary switch to be turned on based on the delay enable signal; as well as The second logic circuit outputs a turn-on control signal to turn on the power switch after the auxiliary switch is turned off.

9. The controller of claim 8, wherein the timing circuit comprises: A first time point determination circuit compares the voltage detection signal with the first divided voltage and provides a first comparison signal at an output terminal; A second time point determination circuit compares the voltage detection signal with the zero-crossing threshold voltage and provides a second comparison signal at an output terminal; as well as The timing logic circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives a first comparison signal, the second input terminal receives a second comparison signal, and the output terminal provides a duration detection signal.

10. The controller according to claim 8, wherein the first conversion unit comprises: A first current source having a power supply terminal coupled to a power supply voltage and an output terminal providing a first charging current; A first capacitor having a first end and a second end, wherein the second end is grounded; A unidirectional device having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the first current source, and the output terminal is coupled to the first terminal of the first capacitor; as well as The first switch has a first end, a second end and a control end, wherein the first end is coupled to the output end of the first current source, the second end is grounded, and the control end receives a duration detection signal.

11. The controller according to claim 10, wherein the second conversion unit comprises: A second current source is coupled to the first current source to form a mirror current source therewith, and provides a second charging current at an output end; A second capacitor having a first terminal and a second terminal, wherein the first terminal is coupled to the output terminal of the second current source and the second terminal is grounded; A trigger circuit has a set terminal, a reset terminal and an output terminal, wherein the set terminal receives an enable signal, and the reset terminal receives a delay enable signal; A second switch having a first end, a second end and a control end, wherein the first end is coupled to the first end of the second capacitor, the second end is grounded, and the control end is coupled to the output end of the trigger circuit; as well as The comparison circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first terminal of the second capacitor, the second input terminal is coupled to the output terminal of the first conversion unit, and a delay enable signal is provided at the output terminal. 12 . The controller of claim 8 , wherein when the difference between the target valley number and the current valley number decreases to 1, and the voltage detection signal decreases to a zero-crossing threshold voltage, the auxiliary turn-on enable signal is valid.

13. A control method for a quasi-resonant switching converter, the switching converter comprising an energy storage element and a power switch coupled to the energy storage element, the control method comprising: providing a voltage detection signal representing the voltage across the power switch; Providing a platform voltage representing the maximum value of the voltage detection signal when the sample-and-hold signal is valid; Dividing the platform voltage to provide a first divided voltage; Determine a first time point at which the voltage detection signal decreases to a first divided voltage; Determine a second time point at which the voltage detection signal decreases to a zero-crossing threshold voltage; In response to a time interval between a first time point and a second time point, providing a control voltage proportional to the time interval; Providing a turn-on enable signal corresponding to a target number of valleys for valley conduction of the power switch; Based on the turn-on enable signal and the control voltage, providing a delay enable signal, wherein the delay enable signal has a first time delay relative to the turn-on enable signal, and the first time delay is proportional to the control voltage; and The power switch is turned on based on the delayed enable signal.

14. The control method of claim 13, wherein the method of providing the control voltage comprises charging the first capacitor with a first charging current during the time interval.

15. The control method according to claim 13, wherein the method of providing the delay enable signal comprises: dividing the control voltage to provide a second divided voltage; When the enable signal is valid, charging the second capacitor with a second charging current, wherein the second charging current is proportional to the first charging current; as well as The voltage across the second capacitor is compared with the second divided voltage, and a delay enable signal is provided according to the comparison result.

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