An intelligent voltage-limited full-bridge rectifier chip and power converter

Abstract

The present invention provides an intelligent voltage-limited full-bridge rectifier chip and a power converter, wherein the full-bridge rectifier chip includes a full-bridge rectifier circuit, a pre-clamping voltage generating circuit and a clamping current absorbing circuit; after the voltage is input from the first rectifier pin and the second rectifier pin of the full-bridge rectifier chip, it is respectively input to the two input ends of the pre-clamping voltage generating circuit; the output end of the pre-clamping voltage generating circuit outputs the pre-clamping voltage to the clamping current absorbing circuit; the clamping current absorbing circuit uses the pre-clamping voltage as a reference voltage, and when the high potential pin voltage of the full-bridge rectifier chip is greater than the pre-clamping voltage, it absorbs the clamping current from the high potential pin and flows to the low potential pin. The present invention effectively prevents the output voltage of the converter from floating high and improves the conversion efficiency of the converter. The intelligent voltage-limited full-bridge rectifier chip of the present invention changes with the change of the voltage output by the converter, has nothing to do with the specification of the output voltage, and is conducive to the normalization of the product.

Description

Technical Field

[0001] The present invention relates to the technical field of rectifier chips, and in particular to an intelligent voltage-limited full-bridge rectifier chip and a power converter. Background Art

[0002] Push-pull converter and full-bridge converter are two widely used power converters. The working principle of push-pull converter is as follows: Figure 1 and Figure 2 As shown. The push-pull converter includes two isolated transmission paths. Figure 1 This is the schematic diagram of the first isolated transmission circuit of the push-pull converter. The thick solid line is the current path of isolated transmission. When switch Q1 is turned on, the current flows from the positive terminal V IN Starting from the transformer main winding N P1 After that, it flows through Q1 to the negative terminal of the converter input power supply. Due to the coupling effect of the isolation converter, the current flows from the secondary winding N S1 The same-name terminal flows out, and the rectifier diode D1 is turned on to supply power to the output capacitor and the resistive load. In this way, the energy is transferred from the primary power supply V IN Delivered to the secondary side of the converter V OUT In the first isolated transmission loop, switch Q2 is closed and the transformer winding N P2 No current flows through the secondary winding N S2 The opposite end, that is, the anode of the rectifier diode D2 is negative, and the diode D2 is reversely cut off. S2 No current flows through the rectifier diode D2. Figure 2 This is the schematic diagram of the second isolated transmission circuit of the push-pull converter. The current transmission path is shown as the thick solid line. In contrast to the first transmission circuit, switch Q1 is open and Q2 is closed. The primary current flows from V IN Through the winding N P2 , the secondary side passes through winding N S2 and rectifier diode D2 to the output terminal V OUT , winding N P1 、N S1 No current flows through the rectifier diode D1. It can be seen that when the first circuit transmits energy, the device on the second circuit is cut off. Conversely, when the second circuit transmits energy, the device on the first circuit is cut off. The first circuit and the second circuit transmit energy to the output terminal V alternately at the same time. OUT The process is similar to a push and a pull, hence the name "push-pull" converter.

[0003] The working principle of the full-bridge converter is as follows Figure 3 and Figure 4 As shown. Unlike the push-pull converter, the primary side of the transformer has only one winding N PThe current transmission direction is controlled by four switching tubes Q1, Q2, Q3, and Q4. Figure 3 The thick solid line and its arrow in the figure indicate the first isolated transmission loop. Q1 and Q3 form one bridge arm and are turned on at the same time; Q2 and Q4 form another bridge arm and are turned off at the same time. P On the contrary, in the second transmission loop, the bridge arm formed by Q1 and Q3 is turned off, while the bridge arm formed by Q2 and Q4 is turned on, and the current flows from the transformer N P The opposite-name end flows into the same-name end and flows out. The two bridge arms are opened and closed alternately at the same time, which can achieve the same effect as the push-pull converter. The circuit topology of the push-pull converter has one more winding in the transformer, which is relatively complex, but only two power tubes are needed to drive the transformer; the circuit topology of the full-bridge converter has a simpler transformer, but four switches are needed to drive the transformer, so the two topologies have their own advantages.

[0004] Both full-bridge converters and push-pull converters are forward converters. They are named according to whether the primary winding of the isolation transformer is push-pull driven or full-bridge driven. Figures 1 to 4 The secondary side rectifier circuit is the same, only one winding and rectifier diode are turned on at a time, while the other winding and rectifier diode are not turned on, so it is often called half-bridge rectification. In fact, the secondary side of the transformer can also use one winding to achieve the rectification function, such as Figure 5 and Figure 6 As shown in the figure, they are the paths of the first and second isolation transmission loops respectively. The primary side of the transformer adopts a push-pull drive mode, which can also be like Figure 3 and Figure 4 The current transmission path of the first loop is as follows: Figure 5 As shown by the thick solid line and arrow in the figure, the primary current flows through the winding N P1 and switch Q1, the secondary current flows from winding N S The opposite end flows into the same end and then passes through the two rectifier diodes D1 and D3 to transfer the energy to V OUT , the primary switch Q2 and the two rectifier diodes D2 and D4 on the secondary side are all turned off. The current transmission path of the second loop is as follows Figure 6 As shown by the thick solid line and arrow in the figure, the primary current flows through the winding N P2 and switch Q2, the secondary current flows from winding N S The energy flows into the same-name end and out of the opposite-name end, and then passes through the two rectifier diodes D2 and D4 to transfer the energy to V OUT, the primary switch Q1 and the two rectifier diodes D1 and D3 on the secondary side are both closed. It can be seen that the rectifier diodes D1 and D3 form a bridge arm, and the rectifier diodes D2 and D4 form another bridge arm. The two bridge arms are alternately turned on and off, forming a common full-bridge rectifier circuit. Since the secondary side of the transformer only requires one winding, the production cost is reduced. However, it requires four diodes, and there will be two diode voltage drops when each bridge arm is turned on, resulting in low efficiency and poor load regulation. For this reason, the patent with application number 202220361448.6 proposes "A full-bridge rectifier chip and power converter", such as Figure 7 As shown, it utilizes semiconductor technology to integrate a pair of rectifier diodes and a pair of N-channel MOS tubes on a wafer to form a full-bridge rectifier chip, solving the problems encountered in the full-bridge rectifier formed by four diodes.

[0005] However, the above output rectifier circuits or chips all use the unidirectional conduction characteristics of the diode to achieve the rectification function. Therefore, when the load of the switching converter is extremely light, especially when it is no-load, that is, Figures 1 to 6 Medium load resistance R L When the output voltage V OUT The voltage spikes are caused by the transformer leakage inductance or wiring inductance. The mechanism is as follows: Without considering the transformer leakage inductance and parasitic inductance, Figure 7 The ideal waveform of the voltage at the pins VD1 and VD2 of the full-bridge rectifier chip is shown in Figure 8. It is an approximate square wave without voltage spikes. The voltage magnitude is proportional to the converter input voltage V IN In fact, the transformer inevitably has leakage inductance and parasitic inductance. The actual voltage waveform at the pins VD1 and VD2 of the full-bridge rectifier chip is as follows: Fig. 9 As shown, the energy of the leakage inductance voltage spike is also transferred to the output terminal V through the rectifier diode. OUT , then when the converter output load is extremely light, especially when it is unloaded (i.e. load R L Disconnect) Output voltage V OUT Floating high, for example, for V OUT =5V output specification converter, when no load V OUT To avoid this voltage rise, a common method is to add a voltage OUT Connect an additional resistor to dissipate the energy of leakage inductance and parasitic inductance. Since the power consumption of this additional resistor is not the load R L The power is not consumed by the converter, but by the converter itself, so this resistor is often called a "fake load".

[0006] The value of the dummy load resistor should be moderate. On the one hand, it should effectively suppress the converter output voltage V OUT The floating height, the dummy load resistance value should be small, more power consumption is consumed to print VOUT On the other hand, the loss of the dummy load resistor will reduce the output efficiency of the converter, so the value of the added load resistor cannot be too small. OUT Different specifications of converters have different power consumption on the same resistance value of the dummy load, so it is necessary to adjust the output voltage V OUT Choose different dummy load resistors of different resistance values, V OUT The larger the voltage, the larger the resistance of the dummy load resistor. Conversely, the smaller the resistance of the dummy load resistor. OUT ≈5V converter, the dummy load resistance is about 5kΩ, and for V OUT For a ≈24V converter, the value of the dummy load is approximately 24kΩ.

[0007] It can be seen that the conventional technology of using a dummy load to consume the energy of inductance and parasitic inductance has the following four defects:

[0008] 1. The dummy load resistor is connected to the output end of the converter. Regardless of whether the converter is loaded or not, it will lose power, reducing the output efficiency of the converter;

[0009] 2. In order to effectively suppress the output voltage from drifting high, the dummy load resistor must be smaller than the required resistance value to ensure the consistency of converter product production;

[0010] 3. Different output voltage V OUT Different specifications of converters require different resistors to be selected and cannot be normalized, which increases the cost of product debugging and verification;

[0011] 4. The dummy load resistor increases the area of ​​the circuit board, and also makes the converter larger and more expensive. Summary of the invention

[0012] The purpose of the present invention is to provide an intelligent voltage-limited full-bridge rectifier chip and a power converter, which can solve the problem of using a dummy load to consume the energy of transformer leakage inductance and parasitic inductance in the prior art.

[0013] The objective of the present invention is achieved through the following technical solutions:

[0014] In a first aspect, the present invention provides an intelligent voltage-limiting full-bridge rectifier chip, including a full-bridge rectifier circuit and an intelligent voltage limiter; the intelligent voltage limiter includes a pre-clamping voltage generating circuit and a clamping current absorbing circuit; after the voltage is input from the first rectifier pin VD1 and the second rectifier pin VD2 of the intelligent voltage-limiting full-bridge rectifier chip, it is respectively input to the two input ends of the full-bridge rectifier circuit and the two input ends of the pre-clamping voltage generating circuit; the two output ends of the full-bridge rectifier circuit are respectively connected to the low potential pin GND and the high potential pin VCC of the intelligent voltage-limiting full-bridge rectifier chip; the output end of the pre-clamping voltage generating circuit A pre-clamping voltage which is one diode threshold voltage lower than the high level voltage of the first rectifier pin VD1 and the second rectifier pin VD2 is output to the first input end of the clamping current absorption circuit; the second input end of the clamping current absorption circuit is connected to the high potential pin VCC; the output end of the clamping current absorption circuit and the ground end of the pre-clamping voltage generating circuit are connected to the low potential pin GND; the clamping current absorption circuit uses the pre-clamping voltage as a reference voltage, and when the voltage of the high potential pin of the intelligent voltage-limiting full-bridge rectifier chip is greater than the pre-clamping voltage, the clamping current is absorbed from the high potential pin and flows to the low potential pin.

[0015] Furthermore, the pre-clamping voltage generating circuit includes a third diode D3, a fourth diode D4 and a filter capacitor C O The anode of the third diode D3 is connected to the first rectifier pin VD1 as one input terminal of the pre-clamp voltage generating circuit; the anode of the fourth diode D4 is connected to the second rectifier pin VD2 as another input terminal of the pre-clamp voltage generating circuit; the cathode of the third diode D3 and the cathode of the fourth diode D4 are connected to the filter capacitor C O The positive electrode of the filter capacitor C O The negative electrode of is used as the ground terminal of the pre-clamping voltage generating circuit.

[0016] Furthermore, the clamp current absorption circuit includes a current source I1 and a current mirror composed of a first P-channel MOS transistor PM1 and a second P-channel MOS transistor PM2; the source of the second P-channel MOS transistor PM2 is used as the first input end of the clamp current absorption circuit to input the pre-clamp voltage, and the source of the first P-channel MOS transistor PM1 is used as the second input end of the clamp current absorption circuit to connect to the high potential pin VCC; the gate and drain of the second P-channel MOS transistor PM2 are connected to the positive electrode of the current source I1, and the voltage generated at the gate of the second P-channel MOS transistor PM2 acts on the gate of the first P-channel MOS transistor PM1, and the drain of the first P-channel MOS transistor PM1 and the negative electrode of the current source I1 are connected to the low potential pin GND.

[0017] Furthermore, the pre-clamping voltage generating circuit further includes a resistor R0, and the cathode of the third diode D3 and the cathode of the fourth diode D4 are connected to a resistor R O One end of the resistor R O The other end of the filter capacitor C O The positive terminal of the pre-clamp voltage is from the resistor R O With filter capacitor C O Connection node for the positive output.

[0018] Furthermore, the clamping current absorption circuit includes an operational amplifier AMP1, a first P-channel MOS transistor PM1 and a current source I1; the positive input terminal of the operational amplifier AMP1 inputs the pre-clamping voltage, the negative input terminal is connected to the source of the first P-channel MOS transistor PM1 and the high potential pin VCC, and the output terminal is connected to the gate of the first P-channel MOS transistor PM1; the drain of the first P-channel MOS transistor PM1 is connected to the low potential pin GND; the positive electrode of the current source I1 is connected to the positive input terminal of the operational amplifier AMP1, and the negative electrode is connected to the low potential pin GND.

[0019] Furthermore, the clamping current absorption circuit includes an operational amplifier AMP2, an N-channel MOS tube NM3 and a current source I1; the negative input terminal of the operational amplifier AMP2 inputs the pre-clamping voltage, the positive input terminal is connected to the drain of the N-channel MOS tube NM3 and the high potential pin VCC, and the output terminal is connected to the gate of the N-channel MOS tube NM3; the source of the N-channel MOS tube is connected to the low potential pin GND; the positive electrode of the current source I1 is connected to the negative input terminal of the operational amplifier AMP2, and the negative electrode is connected to the low potential pin GND.

[0020] In a second aspect, the present invention provides a power converter, comprising the above-mentioned intelligent voltage-limiting full-bridge rectifier chip, wherein the first rectifier pin VD1 and the second rectifier pin VD2 of the intelligent voltage-limiting full-bridge rectifier chip are respectively connected to the two ends of the secondary winding of the power converter; the high potential pin VCC of the intelligent voltage-limiting full-bridge rectifier chip is connected to the positive end of the output voltage of the power converter, and the low potential pin GND of the intelligent voltage-limiting full-bridge rectifier chip is connected to the negative end of the output voltage of the power converter.

[0021] Furthermore, the power converter is a push-pull converter or a full-bridge converter.

[0022] Compared with the prior art, the intelligent voltage-limited full-bridge rectifier chip and power converter of the present invention have the following beneficial effects:

[0023] 1. When the power converter is under extremely light load or no load, the clamp current absorption circuit absorbs the leakage inductance peak energy and stabilizes the converter output voltage at the ideal value V CC(0) Nearby, effectively preventing the converter output voltage from drifting high;

[0024] 2. When the converter is under load, the converter output voltage is lower than the pre-clamp voltage, so the clamp tube is in the cut-off state and does not absorb current, thereby improving the conversion efficiency of the converter;

[0025] 3. The intelligent clamp of the present invention changes with the change of the voltage output by the converter. Whether there is clamping absorption current is determined only by the load and has nothing to do with the specification of the output voltage, which is conducive to the normalization of the product;

[0026] 4. The intelligent clamp of the present invention is integrated with the full-bridge rectifier circuit in the same chip, and does not occupy additional space on the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the first isolation transmission loop of the push-pull converter in the prior art;

[0028] Figure 2 It is a schematic diagram of the second isolation transmission loop of the push-pull converter in the prior art;

[0029] Figure 3 It is a schematic diagram of the first isolation transmission loop of the full-bridge converter in the prior art;

[0030] Figure 4 It is a schematic diagram of the second isolation transmission loop of the full-bridge converter in the prior art;

[0031] Figure 5 It is a schematic diagram of the first isolation transmission loop of the full-bridge rectification in the prior art;

[0032] Figure 6 It is a schematic diagram of the second isolation transmission loop of the full-bridge rectification in the prior art;

[0033] Figure 7 It is the circuit principle diagram of the full-bridge control chip in the prior art;

[0034] Figure 8 The ideal voltage waveform at the rectifier pins VD1 and VD2 of the full-bridge control chip in the prior art;

[0035] Fig. 9 The actual voltage waveform at the rectifier pins VD1 and VD2 of the full-bridge control chip in the prior art;

[0036] Fig.10 The circuit block diagram of the full-bridge rectifier chip with intelligent voltage limiter of the present invention;

[0037] Fig.11 This is a first circuit schematic diagram of the full-bridge rectifier chip of the present invention;

[0038] Fig.12 This is a second circuit schematic diagram of the full-bridge rectifier chip of the present invention;

[0039] Fig.13 This is a third circuit schematic diagram of the full-bridge rectifier chip of the present invention;

[0040] Fig.14 This is a fourth circuit schematic diagram of the full-bridge rectifier chip of the present invention;

[0041] Fig.15 The push-pull converter circuit diagram of the present invention;

[0042] Fig.16 It is the circuit principle diagram of the full-bridge converter of the present invention. DETAILED DESCRIPTION

[0043] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0044] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0045] Embodiment 1

[0046] like Fig.10 As shown, the intelligent voltage-limiting full-bridge rectifier chip 100 of the present invention includes a full-bridge rectifier circuit 101 and an intelligent voltage limiter. The pins of the intelligent voltage-limiting full-bridge rectifier chip 100 include at least a first rectifier pin VD1, a second rectifier pin VD2, a low potential pin GND and a high potential pin VCC. The intelligent voltage limiter includes a pre-clamping voltage generating circuit 102 and a clamping current absorbing circuit 103. After the rectified voltage is input from the first rectifier pin VD1 and the second rectifier pin VD2 of the intelligent voltage-limiting full-bridge rectifier chip 100, it is respectively input into the two input ends of the full-bridge rectifier circuit 101 and the two input ends of the pre-clamping voltage generating circuit 102. The two output ends of the full-bridge rectifier circuit 101 are respectively connected to the low potential pin GND and the high potential pin VCC of the intelligent voltage-limiting full-bridge rectifier chip 100. The output end of the pre-clamping voltage generating circuit 102 outputs the pre-clamping voltage V CTo the first input end of the clamp current absorption circuit 103. The second input end of the clamp current absorption circuit 103 is connected to the high potential pin VCC of the intelligent voltage limiting full-bridge rectifier chip 100, and the output end of the clamp current absorption circuit 103 and the ground end of the pre-clamp voltage generation circuit 102 are connected to the low potential pin GND of the intelligent voltage limiting full-bridge rectifier chip 100. The clamp current absorption circuit 103 generates a pre-clamp voltage V C As a reference voltage, when the voltage V of the high potential pin VCC of the intelligent voltage-limiting full-bridge rectifier chip 100 is CC (i.e. the voltage between the low potential pin GND and the high potential pin VCC) is greater than the pre-clamp voltage V C When the clamp current I is absorbed from the high potential pin VCC SNK Then it flows to the low potential pin GND.

[0047] The full-bridge rectifier circuit 101 is implemented by using the full-bridge rectifier circuit of the prior art, and plays the role of bridge rectification. It includes a first diode D1, a second diode D2, a first rectifier MOS tube NM1, and a second rectifier MOS tube NM2. When the first rectifier pin VD1 is at a high level and the second rectifier pin VD2 is at a low level, the first diode D1 and the second rectifier MOS tube NM2 are turned on to form a first rectifier path, and the second diode D2 and the first rectifier MOS tube NM1 are both turned off. When the second rectifier pin VD2 is at a high level and the first rectifier pin VD1 is at a low level, the second diode D2 and the first rectifier MOS tube NM1 are turned on to form a second rectifier path, and the first diode D1 and the second rectifier MOS tube NM2 are both turned off.

[0048] The pre-clamping voltage generating circuit 102 is used to generate a pre-clamping voltage V that is lower than the high level voltage of the two rectifier pins by a diode threshold voltage. C , and outputs the voltage to the clamp current absorption circuit 103. In this embodiment, the pre-clamp voltage generation circuit 102 includes a third diode D3, a fourth diode D4 and a filter capacitor C O The anode of the third diode D3 is connected to the first rectifier pin VD1 as one input terminal of the pre-clamp voltage generating circuit 102. The anode of the fourth diode D4 is connected to the second rectifier pin VD2 as another input terminal of the pre-clamp voltage generating circuit 102. The cathode of the third diode D3 and the cathode of the fourth diode D4 are connected to the filter capacitor C O The positive terminal generates a pre-clamp voltage V C Filter capacitor C OThe negative electrode of is used as the ground terminal of the pre-clamping voltage generating circuit 102. The current source I1 is also a necessary part for generating the pre-clamping voltage. Because it is multiplexed with the bias current source of the clamping current absorption circuit 103, there is no need to add an additional current source in the pre-clamping voltage generating circuit 102. The present invention uses the junction voltage drop of the third diode D3 and the fourth diode D4 to offset the junction voltage drop of the first diode D1 and the second diode D2 in the full-bridge rectifier circuit 101. Therefore, the third diode D3 and the fourth diode D4 have a junction voltage drop offset function. In the present invention, the third diode D3 and the fourth diode D4 are named as junction voltage drop offset diodes.

[0049] The clamp current absorption circuit 103 is based on the pre-clamp voltage V C The clamp current absorption circuit 103 absorbs current from the high potential pin VCC to prevent the output voltage VCC from floating high. In this embodiment, the clamp current absorption circuit 103 includes a current source I1 and a current mirror composed of a first P-channel MOS transistor PM1 and a second P-channel MOS transistor PM2. The source of the second P-channel MOS transistor PM2 is used as the first input terminal of the clamp current absorption circuit 103 to input the pre-clamp voltage V C , the source of the first P-channel MOS transistor PM1 is connected to the high potential pin VCC as the second input terminal of the clamp current absorption circuit 103. The gate and drain of the second P-channel MOS transistor PM2 are connected to the positive electrode of the current source I1, and the voltage generated at the gate of the second P-channel MOS transistor PM2 acts on the gate of the first P-channel MOS transistor PM1. The drain of the first P-channel MOS transistor PM1 and the negative electrode of the current source I1 are connected to the low potential pin GND. In this way, when the voltage of the VCC pin is higher than the source voltage of PM2, that is, the pre-clamp voltage V C When the clamping current I SNK After passing through PM1, it flows to GND. The P-channel MOS tube plays a clamping role and is also called the clamping tube below.

[0050] Next, the working principle of the intelligent voltage limiter is used as the center to explain in detail how it solves the problems of the prior art. In order to facilitate understanding and simplify the formula, the on-resistance of the rectifier MOS tubes NM1 and NM2 in the full-bridge rectifier circuit 101 is ignored, and the high-level voltage at the rectifier pins VD1 and VD2 is recorded as V D12 .

[0051] According to the physics knowledge of semiconductor devices, a threshold voltage V is generated during the formation of a PN junction diode or a Schottky junction diode. th , only when the voltage between the anode Anode and cathode Cathode of the diode exceeds this voltage can it be forward-conducted; at the same time, the diode has a certain internal resistance r D , the forward voltage drop of the diode can be approximately equivalent to V D(ON) =V th +ID *r D , where I D is the forward current through the diode.

[0052] Since the time when the rectifier pins VD1 and VD2 are both low level voltages is very short, the VCC pin voltage V CC , that is, the converter output voltage V OUT , approximately V D12 The load current of the converter is also approximately the current through diodes D1 and D2, which is the difference between the forward voltage drop of the diodes. Then:

[0053] When the converter output is loaded, the voltage V CC It can be approximated as:

[0054] V CC =V D12 -V D(ON) =V D12 -V th -I D *r D …………………………(1)

[0055] When the converter output is in no-load state, I D =0 instead of the above formula is the output voltage of the converter under ideal conditions:

[0056] V CC(0) =V D12 -V th ………………………………(2)

[0057] Then, the voltage spike energy generated by the transformer leakage inductance and the parasitic inductance of the wiring is stored in the converter output capacitor C after passing through diodes D1 and D2, causing the output voltage V OUT High, greater than V in formula (2) CC(0) Therefore, the purpose of the present invention is to prevent the output voltage of the converter from exceeding the ideal value V when the converter output is in a no-load state. CC(0) To this end, the present invention first generates a pre-clamping voltage V through a pre-clamping voltage generating circuit. C , a relatively small current source I1 can be designed, and then the junction voltage drop can be ignored to offset the internal resistance of diodes D3 and D4, then:

[0058] V c =V D12 -V th ………………………………(3)

[0059] It can be seen that the pre-clamp voltage is exactly equal to V when the converter output is in the no-load state. OUT The ideal value.

[0060] The clamp current absorption circuit is used to pre-clamp the voltage V C As a reference voltage, when the voltage V CC (i.e. V OUT ) is greater than V C When the VCC pin absorbs current I SNK , to prevent V CC The voltage rises, so that V CC Voltage clamped at V C Nearby, that is, when the converter is in no-load state, V CC Approximately equal to the ideal value V CC(0) This is due to the clamp absorption current I of the clamp tube PM1. SNK , its size can be easily calculated as:

[0061]

[0062] where u n is the electron mobility, C ox is the gate oxide capacitance per unit area, W is the width of PM1, and L is the channel length of PM1. From formula (4), we can see that if V CC Greater than V CC(0) , PM1 absorbs current I from the VCC pin according to the square relationship of their difference SNK , to prevent V CC The voltage is high.

[0063] In addition, it can be seen from equations (1) and (3) that the voltage drop I generated by the internal resistance of diodes D1 and D2 when the converter is loaded is D *r D , V CC Voltage is less than V C , then the clamping tube PM1 will be in the cut-off state and no longer absorb current. Compared with the existing technology that uses a resistor as a dummy load, this significantly improves the efficiency of the converter.

[0064] From formula (3), we can see that the pre-clamp voltage V C Follow V D12 This means that the intelligent voltage limiter of the present invention absorbs current when the converter is unloaded or lightly loaded to prevent the output voltage from floating high, and stops absorbing current when loaded to improve efficiency. These two excellent characteristics are not affected by the converter output voltage V OUT The effect of the specifications for different V OUT (For example, the commonly used 5V, 12V, 15V, 24V) can use the same full-bridge rectifier chip with an intelligent voltage limiter.

[0065] The capacitor C0 in the pre-clamp voltage generation circuit plays a filtering role. Because the rectifier pins VD1 and VD2 are both low-level voltages for a short period of time, generally about 100nS, the energy storage effect of the filter capacitor C0 prevents the pre-clamp voltage V C In the integrated circuit, it is easy to design I1 = 0.5uA, C0 = 2pF, so within 100nS, V C Only 25mV drops, when VD1 or VD2 returns to high level, V C Recovery soon followed.

[0066] More preferably, the junction voltage drop canceling diodes D3 and D4 are of the same type as the diodes D1 and D2 in the full-bridge rectifier circuit, so that their threshold voltages are the same and can easily cancel each other out, that is, equations (2) and (3) are completely equal.

[0067] As described above, the intelligent voltage-limited full-bridge rectifier chip of the present invention is applied to a power converter, and the beneficial effects that can be achieved include:

[0068] 1. When the converter is under extremely light load or no load, the converter output voltage is higher than the pre-clamp voltage. The clamp current absorption circuit absorbs the leakage inductance peak energy and stabilizes the converter output voltage at the ideal value V CC(0) Nearby, effectively preventing it from floating high;

[0069] 2. When the converter is under load, the converter output voltage is lower than the pre-clamp voltage, so the clamp tube is in the cut-off state and does not absorb current, thereby improving the conversion efficiency of the converter;

[0070] 3. The intelligent clamp of the present invention changes with the change of the voltage output by the converter. Whether there is clamp absorption current is determined only by the load and has nothing to do with the specification of the output voltage, which is conducive to the normalization of the product;

[0071] 4. The intelligent clamp of the present invention is integrated with the full-bridge rectifier circuit in the same chip, and does not occupy additional area on the circuit board.

[0072] Embodiment 2

[0073] like Fig.12 1 is a circuit diagram of the second embodiment of the present invention. The difference from the first embodiment is that the pre-clamping voltage generating circuit 102 of this embodiment adds a resistor R0, and the cathode of the third diode D3 and the cathode of the fourth diode D4 are connected to the resistor R O One end of the resistor R O The other end of the filter capacitor C O The positive electrode, pre-clamp voltage V C From the resistor R O With filter capacitor C OThe other parts of this embodiment are the same as those of the first embodiment and will not be described in detail here.

[0074] The pre-clamp voltage V C The calculation formula is:

[0075] V′ C =V D12 -V th -I1*R0……………………(5)

[0076] Take I1 = 0.5uA, R0 = 100k, C0 = 2pF, and compare equations (2) and (5). The pre-clamp voltage is higher than the ideal voltage value V at no load. CC(0) Therefore, one of the functions of the pre-clamp resistor R0 is to generate the clamping current I in advance. SNK , clamp the output voltage of the converter in advance to more effectively suppress its high drift; another function of the pre-clamp resistor R0 is that it forms an RC filter with a time constant of 200nS with the filter capacitor C0 to avoid the pre-clamp voltage V C Affected by the leakage inductance spike voltage.

[0077] Embodiment 3

[0078] The difference between the first embodiment and the second embodiment is that the present embodiment further improves the clamp current absorption circuit. The first embodiment and the second embodiment use a current mirror to form a clamp current absorption circuit, which has a simple circuit and the current I absorbed by the clamp is SNK As the output voltage V CC and the pre-clamp voltage V C The voltage difference increases in square relation, that is, the voltage V CC With the pre-clamp voltage V C There must be a certain voltage difference between them to absorb a larger current, for example, a voltage difference of 100mV. This clamping current absorption circuit can meet most application requirements, but if you want higher clamping accuracy, operational amplifiers are often used in integrated circuit design to achieve this. Fig.13 As shown, the clamp current absorption circuit 103 of this embodiment includes an operational amplifier AMP1, a first P-channel MOS transistor PM1 and a current source I1. The positive input terminal of the operational amplifier AMP1 inputs the pre-clamp voltage V C The negative input terminal is connected to the source of the first P-channel MOS transistor PM1 and the high potential pin VCC, and the output terminal is connected to the gate of the first P-channel MOS transistor PM1. The drain of the first P-channel MOS transistor PM1 is connected to the low potential pin GND. The positive electrode of the current source I1 is connected to the positive input terminal of the operational amplifier AMP1, and the negative electrode is connected to the low potential pin GND.

[0079] The working principle is: if V CCThe voltage is greater than the pre-clamp voltage V C , the output of the operational amplifier AMP1 decreases, making V CC The voltage decreases; on the contrary, if V CC The voltage is less than the pre-clamp voltage V C , the output of the operational amplifier AMP1 increases so that V CC voltage increases. Since the gain of the operational amplifier is large, V CC Very close to V C , V CC V C Just greater than 1mV is also easily achievable.

[0080] Furthermore, the clamp current absorption circuit 103 may also adopt Fig.14 The circuit structure includes an operational amplifier AMP2, an N-channel MOS tube NM3 and a current source I1. The negative input terminal of the operational amplifier AMP2 inputs a pre-clamp voltage V C The positive input end is connected to the drain of the N-channel MOS tube NM3 and the high potential pin VCC, and the output end is connected to the gate of the N-channel MOS tube NM3. The source of the N-channel MOS tube is connected to the low potential pin GND. The positive electrode of the current source I1 is connected to the negative input end of the operational amplifier AMP2, and the negative electrode is connected to the low potential pin GND.

[0081] Because N-channel MOS tube is used as the clamp tube, the polarity of the operational amplifier in the circuit connection is Fig.13 The working principles are the same, so I will not go into details.

[0082] Embodiment 4

[0083] like Fig.15 As shown, this embodiment provides a push-pull converter with an intelligent voltage-limiting full-bridge rectifier chip, and its transformer primary side has two windings N P1 and N P2 , the switch tubes Q1 and Q2 drive the winding N in a push-pull manner. P1 and N P2 ; The secondary side of the transformer has only one winding N S The full-bridge rectifier function is realized by using any intelligent voltage-limiting full-bridge rectifier chip of Embodiments 1 to 3 of the present invention, and the secondary winding N S One end of the chip is connected to the rectifier pin VD1, and the other end is connected to the rectifier pin VD2 of the chip; the high potential pin VCC of the chip is connected to the output voltage V OUT The positive terminal of the chip is connected to the low potential pin GND of the converter output voltage V OUT The negative terminal of the capacitor is connected, and the output capacitor C is connected between the high potential pin VCC and the low potential pin GND.

[0084] The working principle is:

[0085] When switch Q2 is open and Q1 is closed, the primary current of the converter flows from the input power supply V IN Starting from the positive end, from winding N P1 The same-name terminal flows into the same-name terminal, flows out from the opposite-name terminal, and then flows back to the input power supply V after closing the switch Q1. IN The negative end of the converter secondary current flows from winding N S The same-name end flows out and enters the rectifier pin VD1 of the full-bridge rectifier chip, and passes through the diode D1 of the full-bridge rectifier circuit to V OUT Positive terminal, through output capacitor C and output load R L Then it flows to the low potential pin GND of the chip, passes through NM2 in the full-bridge rectifier circuit, and then flows out from the rectifier pin VD2, and flows back to the winding N S The first isolated transmission circuit thus formed connects the primary input power supply V IN The energy isolation is transmitted to the secondary side V OUT .

[0086] When switch Q1 is open and Q2 is closed, the primary current of the converter flows from the input power supply V IN Starting from the positive end, from winding N P2 The current flows into the opposite end of the switch, flows out from the same end, and then flows back to the input power supply V after closing the switch Q2. IN The negative end of the converter secondary current flows from winding N S The opposite end flows out and enters the rectifier pin VD2 of the full-bridge rectifier chip, and passes through the diode D2 of the full-bridge rectifier circuit to V OUT Positive terminal, through output capacitor C and output load R L Then it flows to the low potential pin GND of the chip, flows out from the rectifier pin VD1 after passing through NM1 in the full-bridge rectifier circuit, and flows back to the winding N S The second isolated transmission circuit thus formed connects the primary input power supply V IN The energy isolation is transmitted to the secondary side V OUT .

[0087] At the converter output with load R L When the primary power supply V IN Isolation transmission to the secondary side V OUT All the energy is consumed by the load R L Consumption, V OUT will not be increased due to the energy of the transformer leakage inductance spike; the intelligent voltage limiter does not OUT Absorbing current; when the converter output is not loaded, the energy of the transformer leakage inductance spike is also transferred to V OUT , it cannot be consumed because there is no load. If the intelligent voltage-limiting full-bridge rectifier chip of the present invention is not used, V OUTIncrease, but the intelligent voltage-limited full-bridge rectifier chip from V OUT Absorption current I SNK To prevent V OUT Raise to avoid damaging the device.

[0088] Embodiment 5

[0089] like Fig.16 As shown, this embodiment provides a full-bridge converter with an intelligent voltage-limiting full-bridge rectifier chip, and its transformer primary side has only one winding N P , the switch tubes Q1 and Q3 are a group of switches that are turned on or off at the same time, and the switch tubes Q2 and Q4 are another group of switches that are turned on or off at the same time. The two groups of switches complement each other to drive the winding N in a full-bridge manner. P ; The secondary side of the transformer also has only one winding N S The intelligent voltage-limited full-bridge rectifier chip of the present invention is used to realize the full-bridge rectifier function. The winding N S One end of the chip is connected to the rectifier pin VD1, and the other end is connected to the rectifier pin VD2 of the chip; the high potential pin VCC of the chip is connected to the output voltage V OUT The positive terminal of the chip is connected to the low potential pin GND of the converter output voltage V OUT The negative terminal of the output capacitor C is connected between them.

[0090] The working principle is:

[0091] When switches Q2 and Q4 are open and Q1 and Q3 are closed, the primary current of the converter flows from the input power supply V IN Starting from the positive end, through switch Q3, from winding N P The same-name terminal flows into the same-name terminal, flows out from the opposite-name terminal, and then flows back to the input power supply V after closing the switch Q1. IN The negative end of the converter secondary current flows from winding N S The same-name end flows out and enters the rectifier pin VD1 of the full-bridge rectifier chip, and passes through the diode D1 of the full-bridge rectifier circuit to V OUT Positive terminal, through output capacitor C and output load R L Then it flows to the low potential pin GND of the chip, passes through NM2 in the full-bridge rectifier circuit, and then flows out from the rectifier pin VD2, and flows back to the winding N S The first isolated transmission circuit thus formed connects the primary input power supply V IN The energy isolation is transmitted to the secondary side V OUT .

[0092] When switches Q1 and Q3 are open and Q2 and Q4 are closed, the primary current of the converter flows from the input power supply V IN Starting from the positive end, through switch Q4, from winding N PThe current flows into the opposite end of the switch, flows out from the same end, and then flows back to the input power supply V after closing the switch Q2. IN The negative end of the converter secondary current flows from winding N S The opposite end flows out and enters the rectifier pin VD2 of the full-bridge rectifier chip, and passes through the diode D2 of the full-bridge rectifier circuit to V OUT Positive terminal, through output capacitor C and output load R L Then it flows to the low potential pin GND of the chip, flows out from the rectifier pin VD1 after passing through NM1 in the full-bridge rectifier circuit, and flows back to the winding N S The second isolated transmission circuit thus formed connects the primary input power supply V IN The energy isolation is transmitted to the secondary side V OUT .

[0093] At the converter output with load R L When the primary power supply V IN Isolation transmission to the secondary side V OUT All the energy is consumed by the load R L Consumption, V OUT will not be increased due to the energy of the transformer leakage inductance spike; the intelligent voltage limiter does not OUT Absorbing current; when the converter output is not loaded, the energy of the transformer leakage inductance spike is also transferred to V OUT , which cannot be consumed due to no load, would otherwise make V OUT rises, but the smart voltage limiter OUT Absorption current I SNK To prevent V OUT Raise to avoid damaging the device.

[0094] In the present invention, the P-channel MOS tube can also be replaced by a PNP transistor, the N-channel MOS tube can also be replaced by an NPN transistor, and the constant current source can also be replaced by a resistor with a large resistance value. This simple replacement can achieve the same or similar effect as described in the present invention, but does not change its basic principle and is still within the protection scope of the present invention. The push-pull converter of Example 4 and the full-bridge converter of Example 5 are both power converters. According to the tips of Example 4 and Example 5, the intelligent voltage-limited full-bridge rectifier chip of the present invention can also be applied to other power converters, which are not listed here one by one.

[0095] In the present invention, unless otherwise clearly specified and limited, the first feature "on" the second feature may be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. "Multiple" means at least two, such as two, three, etc., unless otherwise clearly and specifically limited.

[0096] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0097] The above is only for explaining the implementation mode of the present invention and is not intended to limit the present invention. For those skilled in the art, any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention without creative work should be included in the protection scope of the present invention.

Claims

1. An intelligent voltage-limited full-bridge rectifier chip, comprising a full-bridge rectifier circuit, characterized in that: The invention also includes an intelligent voltage limiter; the intelligent voltage limiter includes a pre-clamping voltage generating circuit and a clamping current absorbing circuit; after the voltage is input from the first rectifier pin (VD1) and the second rectifier pin (VD2) of the intelligent voltage-limiting full-bridge rectifier chip, it is respectively input to the two input ends of the full-bridge rectifier circuit and the two input ends of the pre-clamping voltage generating circuit; the two output ends of the full-bridge rectifier circuit are respectively connected to the low potential pin (GND) and the high potential pin (VCC) of the intelligent voltage-limiting full-bridge rectifier chip; the output end of the pre-clamping voltage generating circuit outputs a voltage higher than the first rectifier pin (VD1) and the second rectifier pin (VD2). The high level voltage of the pin (VD2) is lower than the pre-clamping voltage of a diode threshold voltage to the first input end of the clamping current absorption circuit; the second input end of the clamping current absorption circuit is connected to the high potential pin (VCC); the output end of the clamping current absorption circuit and the ground end of the pre-clamping voltage generating circuit are connected to the low potential pin (GND); the clamping current absorption circuit uses the pre-clamping voltage as a reference voltage, and when the voltage of the high potential pin of the intelligent voltage-limiting full-bridge rectifier chip is greater than the pre-clamping voltage, the clamping current is absorbed from the high potential pin (VCC) and then flows to the low potential pin (GND).

2. The intelligent voltage-limited full-bridge rectifier chip according to claim 1, characterized in that: The pre-clamping voltage generating circuit comprises a third diode (D3), a fourth diode (D4) and a filter capacitor (C O ); the anode of the third diode (D3) is connected to the first rectifier pin (VD1) as one input end of the pre-clamping voltage generating circuit; the anode of the fourth diode (D4) is connected to the second rectifier pin (VD2) as the other input end of the pre-clamping voltage generating circuit; the cathode of the third diode (D3) and the cathode of the fourth diode (D4) are connected to the filter capacitor (C O ) and generates a pre-clamp voltage here; the filter capacitor (C O ) serves as the ground terminal of the pre-clamping voltage generating circuit.

3. The intelligent voltage-limited full-bridge rectifier chip according to claim 1, characterized in that: The clamp current absorption circuit comprises a current source (I1) and a current mirror composed of a first P-channel MOS tube (PM1) and a second P-channel MOS tube (PM2); the source of the second P-channel MOS tube (PM2) is used as the first input end of the clamp current absorption circuit to input a pre-clamp voltage, and the source of the first P-channel MOS tube (PM1) is used as the second input end of the clamp current absorption circuit to connect a high potential pin (VCC); the gate and drain of the second P-channel MOS tube (PM2) are connected to the positive electrode of the current source (I1), the voltage generated at the gate of the second P-channel MOS tube (PM2) acts on the gate of the first P-channel MOS tube (PM1), and the drain of the first P-channel MOS tube (PM1) and the negative electrode of the current source (I1) are connected to a low potential pin (GND).

4. The intelligent voltage-limited full-bridge rectifier chip according to claim 2, characterized in that: The pre-clamping voltage generating circuit further comprises a resistor (R0), a cathode of the third diode (D3) and a cathode of the fourth diode (D4) are connected to one end of the resistor (R0), and the other end of the resistor (R0) is connected to a filter capacitor (C O ) positive terminal, the pre-clamp voltage is generated by the resistor (R0) and the filter capacitor (C O ) positive connection node output.

5. The intelligent voltage-limited full-bridge rectifier chip according to claim 1, characterized in that: The clamp current absorption circuit comprises an operational amplifier (AMP1), a first P-channel MOS transistor (PM1) and a current source (I1); the positive input end of the operational amplifier (AMP1) inputs a pre-clamp voltage, the negative input end is connected to the source of the first P-channel MOS transistor (PM1) and a high potential pin (VCC), and the output end is connected to the gate of the first P-channel MOS transistor (PM1); the drain of the first P-channel MOS transistor (PM1) is connected to a low potential pin (GND); the positive electrode of the current source (I1) is connected to the positive input end of the operational amplifier (AMP1), and the negative electrode is connected to the low potential pin (GND).

6. The intelligent voltage-limited full-bridge rectifier chip according to claim 1, characterized in that: The clamp current absorption circuit comprises an operational amplifier (AMP2), an N-channel MOS tube (NM3) and a current source (I1); a pre-clamp voltage is input to the negative input end of the operational amplifier (AMP2), the positive input end is connected to the drain of the N-channel MOS tube (NM3) and a high potential pin (VCC), and the output end is connected to the gate of the N-channel MOS tube (NM3); the source of the N-channel MOS tube is connected to a low potential pin (GND); the positive electrode of the current source (I1) is connected to the negative input end of the operational amplifier (AMP2), and the negative electrode is connected to the low potential pin (GND).

7. A power converter, characterized in that: It comprises the intelligent voltage-limiting full-bridge rectifier chip as described in any one of claims 1 to 6, wherein the first rectifier pin (VD1) and the second rectifier pin (VD2) of the intelligent voltage-limiting full-bridge rectifier chip are respectively connected to the two ends of the secondary winding of the power converter; the high potential pin (VCC) of the intelligent voltage-limiting full-bridge rectifier chip is connected to the positive end of the output voltage of the power converter, and the low potential pin (GND) of the intelligent voltage-limiting full-bridge rectifier chip is connected to the negative end of the output voltage of the power converter.

8. The power converter according to claim 7, characterized in that: The power converter is a push-pull converter or a full-bridge converter.

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