Output phase controllable frequency synthesizer design method

Abstract

The application provides a frequency synthesizer design method with controllable output phase, comprising the following steps: step one, after power-on, FPGA completes local program loading from FLASH and acquires phase compensation parameters; step two, FPGA converts output signal frequency information from a control bus into DAC control data and transmits the data to a DAC chip, and simultaneously performs real-time tracking on data phase information transmitted to the FPGA; step three, the DAC generates a baseband signal according to the written data under clock driving; step four, a frequency multiplier performs frequency multiplication processing on the DAC output baseband signal, and improves the frequency of the output signal to an external setting value; step five, a filter completes filtering on the output signal, suppresses a frequency component set by a previous stage link, and improves the final output signal noise ratio; and step six, when the output signal frequency information on the control bus changes, the FPGA judges whether phase control needs to be implemented.

Description

TECHNICAL FIELD

[0001] The present application relates to the radar technical field, specifically relates to a kind of output phase controllable frequency synthesizer design method. BACKGROUND

[0002] Microwave frequency synthesizer provides output frequency controllable signal as local oscillator for radar, electronic warfare and communication system, completes the required up / down conversion processing function.

[0003] Current microwave frequency synthesizer is divided into direct synthesis mode and phase-locked loop mode, and the required output frequency controllable function can be realized.But the above two technical solutions have respective shortcomings:

[0004] Main shortcoming one: direct synthesis mode output signal frequency is limited by hardware scheme and cannot be set arbitrarily.

[0005] Main shortcoming two: the transition time of phase-locked loop mode changing output frequency is long, and the speed is slow (tens of microseconds).

[0006] Main shortcoming three: the above two existing ways cannot control the phase of output signal. SUMMARY

[0007] Therefore, the present application provides a kind of output phase controllable frequency synthesizer design method to realize the accurate control of output signal phase.

[0008] The embodiment of the present application provides the following technical scheme: a kind of output phase controllable frequency synthesizer design method, comprising the following steps: step one, after power on, FPGA completes the loading of local program and the acquisition of phase compensation parameter from FLASH;Step two, FPGA converts the output signal frequency information from control bus into DAC control data and transmits to DAC chip, while real-time tracking the data phase information transmitted to FPGA;Step three, DAC completes baseband signal generation according to the data written under clock driving;Step four, frequency multiplier carries out frequency multiplication processing to DAC output baseband signal, and improves the frequency of output signal to external setting value;Step five, filter completes the filtering of output signal, suppresses the frequency component set by previous stage link, and improves the final output signal-to-noise ratio;Step six, when the output signal frequency information on control bus changes, FPGA judges whether phase control needs to be realized.

[0009] Further, the local program in step one is specifically: frequency generation model, phase compensation model and the storage function of phase compensation parameter.

[0010] Further, step two includes:

[0011] Step 2.1, the host computer calculates the corresponding frequency control word, and the phase control word, and sends to the FPGA through the bus form;

[0012] Step 2.2, the FPGA inside according to the frequency signal generation model and phase compensation model, conversion DAC control data, through the high-speed bus between FPGA and DAC chip to DAC.

[0013] Further, the host computer calculates the corresponding frequency control word in step 2.1 specifically:

[0014] Where, fo is the required to produce the baseband frequency; fs is the clock sampling frequency of DAC.

[0015] Further, the host computer calculates the corresponding phase control word in step 2.1 specifically:

[0016] Where, Po is the required to adjust the phase value.

[0017] Further, step three is specifically: based on the parameterized real-time waveform data calculation and output to the DAC as driving data, DAC completes the baseband signal generation.

[0018] Further, step six includes:

[0019] When the phase control is needed, then the FPGA rewrites the data to the DAC after completing the phase transformation processing based on the current time baseband phase;

[0020] When the phase control is not needed, then directly complete the new data write.

[0021] Compared with the prior art, the above at least one technical scheme adopted by the embodiment of the present application can achieve the beneficial effects at least including: the characteristics of DAC and DDS output frequency can be quickly changed to realize the output signal frequency conversion of nanosecond level and the frequency can be arbitrarily controlled, and the 1° accurate control of the final output signal is realized through the control of the baseband signal phase. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of these drawings.

[0023] Figure 1 is the structure diagram of the frequency synthesizer of the embodiment of the present application;

[0024] Figure 2is a flowchart of an embodiment of the present application. DETAILED DESCRIPTION

[0025] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0026] It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0027] The embodiment of the present application is composed of FLASH (flash memory), FPGA (field programmable logic gate array chip), DAC (digital analog converter), frequency multiplier and filter, and the connection relationship is as shown in Figure 1 FLASH is used for program and compensation parameter storage, FPGA completes the working state control of the frequency synthesizer and the data exchange with the outside, DAC completes the generation of baseband signals, frequency multiplier completes the frequency multiplication processing of baseband signals, and the filter completes the filtering of the output signals.

[0028] As shown in Figure 2 The present application also provides a frequency synthesizer design method with controllable output phase, and the specific working steps are as follows:

[0029] Step one, after power on, FPGA completes the loading of local program and the acquisition of phase compensation parameters from FLASH;

[0030] The local program contains frequency generation model, phase compensation model, and phase compensation parameter storage function.

[0031] Step two, FPGA converts the output signal frequency information from the control bus into DAC control data and transmits it to the DAC chip, and simultaneously performs real-time tracking on the data phase information transmitted to FPGA;

[0032] a. The host computer calculates the corresponding frequency control word and phase control word according to the conversion formula, and sends them to FPGA in the form of bus;

[0033] b. FPGA converts DAC control data according to the frequency signal generation model and the phase compensation model, and transmits it to DAC through the high-speed bus between FPGA and DAC chip;

[0034] Frequency control:

[0035]

[0036] fo: the required generated intermediate frequency; fs: the clock sampling frequency of DAC; 32 represents the frequency resolution accuracy (which can be adjusted according to actual conditions).

[0037] Phase control:

[0038]

[0039] Po: phase value of required adjustment; 32 represents phase resolution accuracy (which can be adjusted according to actual adjustment).

[0040] Step three, the DAC generates the intermediate frequency signal according to the written data under the clock driving;

[0041] The parameterized real-time waveform data is calculated and output to the DAC as driving data, and the DAC generates the intermediate frequency signal.

[0042] Step four, the frequency multiplier performs frequency multiplication processing on the DAC output baseband signal, and improves the frequency of the output signal to an externally set value;

[0043] Step five, the filter completes the filtering of the output signal, suppresses the remaining frequency components of the previous stage link, and improves the final output signal-to-noise ratio;

[0044] Step six, when the output signal frequency information on the control bus changes, the FPGA judges whether phase control is needed, and when needed, the FPGA completes phase transformation processing based on the current time baseband phase and then rewrites the data of the DAC, and if not needed, directly completes new data writing.

[0045] The beneficial effects of the present application are as follows:

[0046] The present application utilizes the characteristics that the output frequency of the DAC and the DDS can be quickly changed to realize the nanosecond-level output signal frequency transformation and the frequency can be arbitrarily controlled, and at the same time, the baseband signal phase is controlled to realize the accurate control of the final output signal within 1°.

[0047] The present application can be used in radar, electronic warfare, communication and test system to realize the output phase controllable high-speed frequency synthesis requirement and realize the signal processing function under the in-phase / non-in-phase.

[0048] The above is only a specific embodiment of the present application, which cannot limit the range of the present application, so the replacement of equivalent components or equivalent changes and modifications made within the scope of the present application should still belong to the scope of the present application. In addition, the technical features in the present application can be freely combined with each other, and the technical features can be freely combined with each other.

Claims

1. A method of designing a frequency synthesizer with controllable phase output, characterized by, It comprises the following steps: Step one, after power on, FPGA completes local program loading from FLASH and phase compensation parameter acquisition; Step two, FPGA converts output signal frequency information from control bus into DAC control data and transmits to DAC chip, and simultaneously tracks data phase information transmitted to FPGA in real time; Step three, DAC completes baseband signal generation according to written data under clock driving; Step four, frequency multiplier performs frequency multiplication on DAC output baseband signal to improve output signal frequency to external setting value; Step five, filter completes output signal filtering to suppress front-stage link setting frequency component and improve final output signal noise ratio; Step six, when output signal frequency information on control bus changes, FPGA judges whether phase control is needed; The local program in step one is specifically frequency generation model, phase compensation model and phase compensation parameter storage function; The step two comprises: Step 2.1, host computer calculates corresponding frequency control word and phase control word and sends to FPGA through bus form; Step 2.2, FPGA interior converts DAC control data according to frequency signal generation model and phase compensation model and transmits to DAC through high-speed bus between FPGA and DAC chip; The step 2.1 host computer calculates corresponding frequency control word specifically: where fo is the desired generated baseband frequency; fs is the clock sampling frequency of the DAC.

2. The method of claim 1, wherein the output phase controllable frequency synthesizer design is a direct digital frequency synthesizer (DDFS) design. The step 2.1 host computer calculates corresponding phase control word specifically: where Po is the phase value to be adjusted.

3. The method of claim 2, wherein the output phase controllable frequency synthesizer design is characterized by, The step three is specifically real-time waveform data calculation and output to DAC as driving data based on parameterization, and DAC completes baseband signal generation.

4. The method of claim 3, wherein the output phase controllable frequency synthesizer design is characterized by, The step six comprises: When phase control is needed, FPGA rewrites data to DAC after completing phase transformation processing based on current time baseband phase; When phase control is not needed, new data is directly rewritten.

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