A Dynamic Compression Method for Lightning Waveform Data and Its Hardware Implementation Method

Abstract

The present invention discloses a dynamic compression method for lightning waveform data and a hardware implementation method, which includes performing targeted compression on data using a dynamic adaptive compression algorithm; the targeted compression includes improving the algorithm principle; using a differential module to process the differential term data stream; using a lookup module to perform data lookup; using an encoding module to form a suitable encoding; and using a control module to transmit the compressed data. By using an FPGA as a processor, the waveform data output by the sampling chip undergoes differential calculation and effective bit truncation, and is compressed and encoded by an improved LZSS algorithm, the present invention realizes lossless compression adapted to lightning waveforms, improves the compression efficiency and saves storage space compared with traditional compression algorithms.

Description

Technical Field

[0001] The present invention relates to the technical field of lightning waveform data processing, in particular to a dynamic compression method and a hardware implementation method for lightning waveform data. Background Art

[0002] Lightning signals are fast response signals. To achieve accurate acquisition and restoration of lightning waveforms, it is necessary to increase the sampling rate in the signal acquisition and storage system, which also brings a large amount of data redundancy. Therefore, for a lightning waveform data processing system, whether it is for data transmission or storage, it is necessary to first process the data through data compression technology.

[0003] Existing data compression methods can be divided into two categories: lossy compression and lossless compression. Among them, lossy compression is not suitable for processing high-value data; lossless compression is mainly divided into two categories: statistics-based and dictionary-based. Statistics-based methods are slow in hardware implementation and are not easy to process variable-length coding. Traditional dictionary-based methods have a low compression rate for lightning data for objects with a lot of repeated data, and the establishment of the dictionary requires a large amount of storage space. Summary of the Invention

[0004] The purpose of this part is to outline some aspects of the embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this part, as well as in the abstract and title of the present application, to avoid obscuring the purpose of this part, the abstract, and the title. However, such simplifications or omissions shall not be used to limit the scope of the present invention.

[0005] In view of the problems existing in the prior art, the present invention is proposed.

[0006] Therefore, the technical problem to be solved by the present invention is that traditional dictionary-based methods have a low compression rate for lightning data for objects with a lot of repeated data, and the establishment of the dictionary requires a large amount of storage space.

[0007] To solve the above technical problem, the present invention provides the following technical solution: a dynamic compression method for lightning waveform data, which includes using a dynamic adaptive compression algorithm to compress the data specifically; the specific compression includes improving the algorithm principle; using a difference module to process the differential item data stream; using a search module to search for data; using an encoding module to form a suitable encoding; and using a control module to transmit the compressed data.

[0008] As a preferred solution of the dynamic compression method for lightning waveform data of the present invention, wherein: the improvement of the algorithm principle mainly uses a window that slides with the compression process as a dictionary. If the string to be compressed appears in the dictionary, its appearance position and length are output, otherwise the string is directly output.

[0009] As a preferred solution of the dynamic compression method for lightning waveform data according to the present invention, wherein: the difference module uses a two-stage register structure to obtain the values under the previous and next clock beats, takes the difference and intercepts the lower 8 bits for output, and the output still adopts the two's complement format.

[0010] As a preferred solution of the dynamic compression method for lightning waveform data according to the present invention, wherein: the search module mainly processes the 8-bit difference item data stream output by the difference module, searches for identical items in the sliding window, and updates the window data as the progress goes; a storage dictionary and a ram storage address are established respectively, and the data in the address is the index value of the dictionary, and its own index value is given by the hash algorithm.

[0011] As a preferred solution of the dynamic compression method for lightning waveform data according to the present invention, wherein: the encoding module forms a suitable code according to the difference item read by the difference module and the record found by the corresponding search module.

[0012] As a preferred solution of the dynamic compression method for lightning waveform data according to the present invention, wherein: the control module transmits the compressed data through a microcontroller and a variable static storage controller. The microcontroller judges the format type of the data through the high byte, and the low byte is directly the true value of the encoded data.

[0013] As a preferred solution of the dynamic compression method for lightning waveform data according to the present invention, wherein: in the encoding process, the previous read difference item may be required as a basis. The previous data is stored in a register, and a FIFO memory is established to store the encoding result.

[0014] As a preferred solution of the dynamic compression method for lightning waveform data according to the present invention, wherein: an address dictionary is additionally built outside the storage dictionary. The hash algorithm is used to calculate the index value corresponding to the difference item, which is the address of the address dictionary. What is recorded in the address dictionary is the address of the storage dictionary. Therefore, the bit width of the address dictionary corresponds to the depth of the address dictionary. When searching, first calculate the hash mapping value, then find the address recorded in the address dictionary through this index, and finally take out the record in the storage dictionary from this address.

[0015] The present invention also provides a hardware implementation method for dynamic compression of lightning waveform data, including a sampling chip, an integrated circuit chip, a single-chip microcomputer and a TF card. The sampling chip is driven by the integrated circuit chip and outputs sampling data. The integrated circuit chip compresses the data and sends it to the single-chip microcomputer through the variable static storage controller interface. The single-chip microcomputer decompresses the data and transfers it to the TF card.

[0016] As a preferred solution of the hardware implementation method for dynamically compressing lightning waveform data according to the present invention, wherein: the integrated circuit chip immediately transfers the data of only one waveform after compression and storage to the single-chip microcomputer.

[0017] Advantages of the present invention: By using an FPGA as the processor, the waveform data output by the sampling chip is subjected to differential calculation and significant bit truncation, and compressed and output encoded by the improved LZSS algorithm, realizing lossless compression adapted to lightning waveforms, improving the compression efficiency and saving storage space compared with traditional compression algorithms;

[0018] Realize the compression of binary stream sampling data. Using the compression algorithm can save a large amount of storage space and prevent the loss of waveform data due to insufficient storage space; for the lightning monitoring system, it reduces the data redundancy of sampling and facilitates data transmission and storage. Description of the drawings

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to these drawings. Among them:

[0020] Figure 1 It is the flowchart of the FPGA data processing module in the embodiment of the present invention.

[0021] Figure 2 It is the state diagram of the encoding output format in the embodiment of the present invention.

[0022] Figure 3 It is the schematic diagram of the differential module in the embodiment of the present invention.

[0023] Figure 4 It is the test waveform diagram of the differential module in the embodiment of the present invention.

[0024] Figure 5 It is the schematic diagram of the LZSS search module in the embodiment of the present invention.

[0025] Figure 6 It is the test waveform diagram of the LZSS search module in the embodiment of the present invention.

[0026] Figure 7 It is the data output format diagram in the embodiment of the present invention.

[0027] Figure 8 It is the schematic diagram of the encoding module in the embodiment of the present invention.

[0028] Figure 9 It is the test waveform diagram of the encoding module in the embodiment of the present invention.

[0029] Figure 10 This is the schematic diagram of the control module in the embodiment of the present invention.

[0030] Figure 11 This is the overall RTL diagram of the compression scheme in the embodiment of the present invention.

[0031] Figure 12 This is the composition diagram of the hardware system in the embodiment of the present invention.

[0032] Figure 13 This is the program flowchart of STM32 in the embodiment of the present invention. Detailed implementation manners

[0033] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following will describe the detailed implementation manners of the present invention in conjunction with the accompanying drawings of the specification.

[0034] In the following description, many specific details are set forth to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Those skilled in the art can make similar promotions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0035] Secondly, the so-called "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that can be included in at least one implementation manner of the present invention. The appearances of "in one embodiment" in different places in this specification do not all refer to the same embodiment, nor are they separate or alternative embodiments that exclude each other with other embodiments.

[0036] Embodiment 1

[0037] Referring to Figures 1 to 11 , this is the first embodiment of the present invention. This embodiment provides a method for dynamically compressing lightning waveform data, including using a dynamic adaptive compression algorithm to compress the data specifically;

[0038] The specific compression includes

[0039] Improving the algorithm principle;

[0040] Using a difference module to process the differential data stream;

[0041] Using a search module to search for data;

[0042] Using an encoding module to form a suitable encoding;

[0043] Using a control module to transmit the compressed data.

[0044] The present invention uses an improved LZSS algorithm to dynamically compress lightning waveform data, writes the program using Verilog HDL language in the Quartus compilation environment, and writes a testbench for the main modules for testing.

[0045] The specific compression method includes:

[0046] (1) Principle of the improved LZSS algorithm;

[0047] Considering the characteristics of the lightning waveform itself, when using the traditional dictionary-based compression method, the influence of the dictionary capacity on the improvement of compression efficiency is not significant, but it will instead occupy the limited BRAM space. Therefore, the improved LZSS algorithm is used to process the waveform data. The basic idea of LZSS is to use a window that slides with the compression process as a dictionary. If the string to be compressed appears in the dictionary, its position and length are output; otherwise, the string is directly output. In the processing of binary waveform data, since the probability of multiple consecutive sampling points being the same is extremely small, and the retrieval of the length quantity requires at least two more clock cycles, only the position quantity is used as the output of the LZSS encoding in the present invention.

[0048] Modules for data processing in FPGA such as Figure 1 , the compression object of the improved algorithm is the 8-bit differential item of the lightning waveform, and the output is a 6-bit code. During the implementation process, the sliding window capacity needs to be set to 16, that is, the size of the dictionary register is 16. Another address register is created to store the index value of the dictionary. Considering the cross-clock domain transmission of data, two asynchronous FIFOs are established to cache the input and output respectively. The final 6-bit code output has three forms, such as Figure 2 .

[0049] (2) The differential module includes:

[0050] As can be seen from Figure 1 , the PLL provides a 50MHz clock signal to drive the external sampling chip to sample the lightning current wave, that is, the frequency of the input data stream is also 50MHz, and the format is 12-bit signed two's complement. The low-speed data stream after differential processing is read by the subsequent module through the FIFO.

[0051] In this module, a two-stage register structure is used to obtain the values at the previous and next clock cycles, subtract them and intercept the lower 8 bits for output, and the output still uses the two's complement format. Since the sampling frequency is high enough, the truncated differential item will not cause the loss of significant bits. The encapsulated module is as follows Figure 3 shown.

[0052] The written testbench only needs to configure a set of 12-bit random number inputs, and observe whether the outputs of the two registers and the differential item output are correct. The test waveform in modelsim is Figure 4 shown.

[0053] (3) The LZSS search module includes:

[0054] The function of this module is to process the 8-bit differential item data stream output from the differential module, find out whether there are identical items in the LZSS sliding window, and update the window data as the FIFO is read. It is necessary to establish a 16-bit deep, 8-bit wide ram storage dictionary and a 64-bit deep, 4-bit wide ram storage address. The data in the address ram is the index value of the dictionary ram, and its own index value is given by the hash algorithm to improve the search speed.

[0055] The key point of LZSS algorithm is to search for data in the sliding window. The traditional storage method of linear table needs to be convenient in sequence to get the search result. The ordered table can halve the search speed through binary search, but in hardware implementation, these two methods seriously slow down the working frequency and are not suitable for the implementation of this algorithm. The method of using hash table is to establish a mapping relationship between storage location and data. The calculation process of mapping data to location is called hash function. In this way, only two clock cycles are needed for storage and search, which greatly improves the search speed.

[0056] In hardware implementation, a two-level storage structure is adopted, the dictionary ram stores the sliding window data in the LZSS algorithm, the address ram stores the address of the data in the dictionary ram, and the address of the read address ram itself is calculated by the hash function. Considering that the selection of the hash function should not take up too many clock cycles to implement, and conflicts should be avoided as much as possible, that is, the probability of different data obtaining the same address value through the hash function calculation is reduced; taking into account the difficulty of hardware implementation, a simpler hash function construction method needs to be selected. The present invention believes that in the sliding window of width 16 storing the lightning waveform differential item data, there is a probability that the last six bits are the same but the first two bits are different, so the hash value is obtained by truncating the last six bits.

[0057] When using the dual-port ram of the IP core that comes with Quartus, the delay of reading and writing is one clock beat, so the delay required to complete a search is three clock beats, that is, one beat for hash calculation, dictionary address acquisition, and dictionary data acquisition, and one beat for completing an update. In order to improve the working frequency of the system, the present invention uses the following design:

[0058] 1) Set up a three-state state machine and define the three states as State_ra, State_rs and State_w, which are used to read the address RAM, read the dictionary RAM and update the two RAMs at the same time respectively. The rising edge of the clock triggers the state change;

[0059] 2) Set a counter with a maximum value of 15 and a frequency of 50 MHz. Its count value serves as the numbering of the data within the sliding window, i.e., the address of the dictionary ram and the data of the address ram.

[0060] 3) From the previous text, since it takes three clock cycles to process the differential items after reading them from the FIFO, two registers out_dif and out_count are established to store the previously updated differential item and the corresponding counter value respectively.

[0061] 4) When the current state is State_ra, set the read FIFO pin rdreg and the read dictionary ram pin to 1; when the current state is State_rs, clear the read FIFO pin rdreg, and at the same time raise the write ram pin to write the data in out_dif and out_count into the dictionary and the address ram respectively; when the current state is State_w, set the read address ram pin to 1.

[0062] 5) Thus, the timing of data update is as follows: update the differential item when the state is State_rs; update the index value calculated by the hash when the state is State_w; update the data in the address ram retrieved by the index value, i.e., the dictionary address hash_count, when the state is State_ra; retrieve the data hash_dif from the dictionary ram when the next state is State_rs, and store the current differential item and the calculated value in the out_dif and out_count registers; write the data in the out_dif and out_count registers into the dictionary and the address ram when the next state is State_w.

[0063] The written testbench needs to configure a group of 8-bit differential item inputs and two clocks with periods of 50 MHz and 150 MHz respectively to observe whether the output is correct. The test waveform diagram in modelsim is as Figure 6 .

[0064] (4) The encoding module includes:

[0065] The function of this module is to form a suitable encoding based on the differential items read from the FIFO and the records found by the LZSS module corresponding to them. Specifically, the rule for outputting 6-bit encoding is as Figure 7 : If the LZSS algorithm can find the same data in the window, output the high two bits as {0, 1} and the low four bits as the distance of this record. This is Format 1; if the absolute value of the difference between the current differential item and the previously read differential item is no more than 15, output the highest bit as 1 and the low five bits as the complement form of the difference. This is Format 2; if neither of the above is met, split the high and low four bits of the differential item into two groups and output, with the high two bits as {0, 0} and the low four bits as the split item. This is Format 3.

[0066] The input of the module has two groups of eight-bit differential terms out_dif and hash_dif, and two groups of four-bit counter values representing positions out_count and hash_count. The six-bit code is output and stored in the FIFO for STM32 to read.

[0067] Since the previous read differential term may be required as a basis during the encoding process, a set of registers is set to store the previous data, and a FIFO with a bit width of 6 and a depth of 2048 is also required to store the encoding result. According to the above text, when using Format 3 for output, it takes the most clock cycles, that is, splitting the differential term, outputting the high-order code, and outputting the low-order code, which requires a total of three clock cycles. Therefore, the state machine output of the LZSS search module can be directly borrowed for time resource allocation. It can be seen from the waveform diagram that stable corresponding out_dif, hash_dif, out_count, and hash_count four data can be obtained in both State_w and State_ra states. It is temporarily set to perform comparison in the State_w state. The specific encoding process is as follows.

[0068] 1) When the current state is State_w, the write enable pin of the FIFO is cleared and the register old_dif is updated. If out_dif and hash_dif are equal, calculate out_count minus hash_count as the distance value. When the difference is negative, add 15 as the distance value, and update the format signal to 0; if the difference between out_dif and old_dif falls within the range of (-16, 16), output the difference and update the format signal to 1; if neither of the above conditions is met, split the high and low four bits of old_dif into two items code_high and code_low, and update the format signal to 2.

[0069] 2) When the current state is State_ra, the write enable pin of the FIFO is set to 1. If the format signal is 0, output the high two bits of the code as {0, 1}, and the low four bits as the distance value; if the format signal is 1, output the highest bit of the code as 1, and the low five bits as the complement of the difference between the previous and next items; if the format signal is 2, output the code {0, 0, code_high}.

[0070] 3) When the current state is State_rs, if the format signal is 2, set the write enable pin of the FIFO to 1, and at the same time output the code output {0, 0, code_low}, otherwise clear the write enable pin of the FIFO.

[0071] This module requires a large number of external signals, including state machine signals, four groups of input data, two clock signals, etc., which makes it somewhat difficult to write the testbench. In the present invention, a variable condition is set and a random number between 0 and 2 is assigned every 24 clock cycles, which is used as the criterion for three encoding types. A state machine is set up by imitating the LZSS search module. When the state machine outputs 0, hash_count is updated; when the state machine outputs 1, out_dif, hash_dif, and out_count are updated. The specific update rule for the input simulation data is as follows: when condition is 0, referring to the conditions of Format 1, out_dif is equal to hash_dif and the difference between out_count and hash_count falls within the interval (-15, 15); when condition is 0, referring to the conditions of Format 2, the difference between out_count and the previous update falls within the interval (-15, 15), and the difference between hash_count and the previous out_count item is set to 30; when condition is 2, referring to the conditions of Format 3, the difference between out_count and the previous update is set to 30, and the difference between hash_count and the previous out_count item is set to 20.

[0072] The test waveform diagram in Modelsim is as Figure 9 .

[0073] (5) The control module includes:

[0074] The function of this module is to transmit the compressed data to STM32 through FSMC. Since STM32 adopts the address multiplexing method, only 16 data bus pins, read enable, write enable, address latch, and chip select signal pins are required for the input pins, and at the same time, the read FIFO signal is output.

[0075] Since the format of the FSMC data received by STM32 is u16, which can be disassembled into two bytes, the high byte and the low byte. To facilitate the subsequent decompression and processing of data by STM32, certain splitting of the encoding is set during output, and the specific description is as follows: When it is determined that the high two bits of the encoding are {0, 0}, that is, in format three, the high byte of the output is 0, the high four bits of the low byte are 0, and the low four bits are still the low four bits of the encoding; When it is determined that the high two bits of the encoding are {0, 1}, that is, in format one, the high byte of the output is 1, the high four bits of the low byte are 0, and the low four bits are the distance value in the encoding; When it is determined that the high two bits of the encoding are {1, 0}, that is, in format two and the low - order complement is positive, the high byte of the output is 2, the high four bits of the low byte are 0, and the low four bits are still the low four bits of the encoding; When it is determined that the high two bits of the encoding are {1, 1}, that is, in format two and the low - order complement is negative, the high byte of the output is 2, the high four bits of the low byte are 15, and the low four bits are still the low four bits of the encoding. Through such processing, STM32 can judge the format type of the data through the high byte, and the low byte is directly the true value of the encoded data.

[0076] The overall RTL diagram of the final data compression scheme is as Figure 11 shown

[0077] Embodiment 2

[0078] Referring to Figures 12 to 13 , this is the second embodiment of the present invention. This embodiment is based on the previous embodiment, and this embodiment proposes a hardware implementation method for dynamic compression of lightning waveform data.

[0079] The hardware implementation method includes a sampling chip, an integrated circuit chip, a single - chip microcomputer, and a TF card. Among them, the sampling chip is driven by the integrated circuit chip and outputs sampling data. The integrated circuit chip compresses the data and sends it to the single - chip microcomputer through the variable static storage controller interface. The single - chip microcomputer decompresses the data and transfers it to the TF card after decompression. The integrated circuit chip only compresses and saves the data of one waveform and then immediately transfers it to the single - chip microcomputer.

[0080] Hardware system: It is mainly composed of a sampling chip, an FPGA, an STM32 single - chip microcomputer, and a TF card. Among them, the sampling chip is driven by the FPGA and outputs sampling data to the FPGA. The FPGA compresses the data and sends it to the STM32 through the FSMC interface. The STM32 decompresses the data and transfers it to the TF card after decompression. Since the interval between two typical lightning strikes is only about 200 ms, the FPGA only compresses and saves the data of one waveform and then immediately transfers it to the STM32 to prevent waveform loss. The working process of the STM32 is shown in Figure 13 .

[0081] Compression process: The process of waveform data processing can be mainly divided into five modules, which are introduced as follows.

[0082] 1) Differential calculation: The analog-to-digital conversion chip AD9226 used has a measurement range of -5 to 5V and an output form of 12-bit two's complement. A two-stage register structure is used to obtain the values under the previous and current clock beats, take the difference, and truncate the last 8 bits for output. Since the sampling frequency is high enough, the truncated difference terms will not cause loss of significant bits.

[0083] 2) Record search: Another address dictionary RAM with a bit width of 4 and a depth of 64 is built outside the data storage dictionary. The hash function is used to calculate the index value corresponding to the difference term, which is the address of the address dictionary RAM. What is recorded in the address dictionary is the address of the storage dictionary, so the bit width of the address dictionary corresponds to the depth of the address dictionary. During the search, first calculate the hash mapping value, then find the recorded address in the address dictionary through this index, and finally retrieve the record in the storage dictionary from this address.

[0084] 3) Dictionary storage: A RAM with a bit width of 12 and a depth of 16 is created as the dictionary. The first eight bits of each record are the difference terms, and the lowest 4 bits store the timer value. The difference between it and the output of the counter under the latest clock beat is the position distance in the LZSS algorithm.

[0085] 4) Dictionary update: Two dictionary RAMs need to be updated under each clock. The specific process is as follows. A register needs to be set to store the index of the hash mapping of the difference term 16 clock beats ago, delete the address pointed to by this index in the address dictionary and the record corresponding to the address in the storage dictionary; at the same time, write a new record into the storage dictionary at this address, and write the address into the address dictionary at the address pointed to by the new hash mapping index. The whole process takes four clock beats to complete.

[0086] 5) Encoding output: If the retrieved record is X, it means the record cannot be found. Then continue to judge whether it falls within the fluctuation window of the previous term. Assuming the window center is the width 16 of the previous term, calculate whether the absolute value of the difference between the new term and the previous term is greater than 15. If it holds, the high two bits are output as {0, 0}, and the fourth bit is the high and low 4 bits of the new term. This is Format 1; otherwise, the high bit is output as 1, and the low five bits are the difference. This is Format 2; when the retrieved record is not X, then judge whether the record is the same as the new term. When they are the same, the high two bits are output as {0, 1}, and the low four bits are the difference between the current counter value and the timestamp of the record. This is Format 3; if they are not the same, output according to Format 1.

[0087] Importantly, it should be noted that the construction and arrangement of the present application shown in multiple different exemplary embodiments are merely illustrative. Although only a few embodiments are described in detail in this disclosure, those who refer to this disclosure should easily understand that many modifications are possible without substantially departing from the novel teachings and advantages of the subject matter described in this application (e.g., changes in the dimensions, scales, structures, shapes and proportions of various elements, as well as parameter values (such as temperature, pressure, etc.), installation arrangements, use of materials, colors, orientations, etc.). For example, elements shown as integrally formed may be composed of multiple parts or elements, the positions of the elements may be inverted or otherwise changed, and the nature, number or position of discrete elements may be altered or changed. Accordingly, all such modifications are intended to be included within the scope of the present invention. The order or sequence of any process or method steps may be changed or reordered according to alternative embodiments. In the claims, any "means-plus-function" clause is intended to cover the structures that perform the recited function herein, and not only structural equivalents but also equivalent structures. Other substitutions, modifications, changes and omissions may be made in the design, operating conditions and arrangement of the exemplary embodiments without departing from the scope of the present invention. Accordingly, the present invention is not limited to the specific embodiments, but extends to various modifications that still fall within the scope of the appended claims.

[0088] In addition, in order to provide a concise description of the exemplary embodiments, all features of the actual embodiments may not be described (i.e., those features that are not relevant to the currently contemplated best mode of carrying out the present invention or those that are not relevant to the implementation of the present invention).

[0089] It should be understood that in the development of any actual implementation, as in any engineering or design project, numerous specific implementation decisions may be made. Such development efforts may be complex and time-consuming, but for those of ordinary skill in the art who benefit from this disclosure, without undue experimentation, such development efforts will be a routine task of design, fabrication and production.

[0090] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention may be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A dynamic compression method for lightning waveform data, characterized in that: including using a dynamic adaptive compression algorithm to compress data specifically The specific compression includes improving the algorithm principle using a difference module to process the differential term data stream using a search module to search for data using an encoding module to form an encoding using a control module to transmit the compressed data The improved algorithm principle takes a window that slides with the compression process as a dictionary. If the string to be compressed appears in the dictionary, its occurrence position and length are output; otherwise, the string is directly output. In the processing of binary waveform data, since the probability of multiple consecutive sampling points being the same is extremely low, and the retrieval of the length quantity requires at least two more clock beats, only the position quantity is used as the output of the LZSS encoding The difference module uses a two-stage register structure to obtain the values at the previous and current clock beats, takes the difference and intercepts the lower 8 bits for output, and the output still uses the two's complement format The search module processes the 8-bit differential term data stream output by the difference module, searches for whether there are identical items in the sliding window, and updates the window data as the progress goes on A storage dictionary and a RAM storage address are established respectively. The data in the address is the index value of the dictionary, and its own index value is given by the hash algorithm Another address dictionary is built outside the storage dictionary. The hash algorithm is used to calculate the index value corresponding to the differential term, which is the address of the address dictionary. What is recorded in the address dictionary is the address of the storage dictionary. Therefore, the bit width of the address dictionary corresponds to the depth of the address dictionary. When searching, first calculate the hash mapping value, then find the address recorded in the address dictionary through this index, and finally retrieve the record in the storage dictionary from this address A three-state state machine is set up. The three states are defined as State_ra, State_rs, and State_w, which are used to read the address RAM, read the dictionary RAM, and update the two RAMs simultaneously respectively. The state change is triggered by the rising edge of the clock A counter with a maximum value of 15 and a frequency of 50 MHz is set up. Its count value is used as the number of the data in the sliding window, that is, the address of the dictionary RAM and the data of the address RAM Since it takes three clock cycles to process after reading the differential term data in the FIFO, two registers out_dif and out_count are set up to store the previously updated differential term and the corresponding counter value respectively When the current state is State_ra, the read FIFO pin rdreg and the read dictionary RAM pin are set to 1; when the current state is State_rs, the read FIFO pin rdreg is cleared, and at the same time, the write RAM pin is pulled high to write the data in out_dif and out_count into the dictionary and the address RAM respectively; when the current state is State_w, the read address RAM pin is set to 1 The timing of data update is as follows: when the state is State_rs, the differential term is updated; when the state is State_w, the index value calculated by the hash is updated; when the state is State_ra, the data in the address ram is retrieved by the index value, that is, the address hash_count of the dictionary; when the state is the next State_rs, the data hash_dif in the dictionary ram is retrieved, and the differential term and the calculated value at this time are stored in the out_dif and out_count registers; when the state is the next State_w, the data in the out_dif and out_count registers is written into the dictionary and the address ram. The written testbench needs to configure a group of 8-bit differential term inputs and two clocks with periods of 50 MHz and 150 MHz respectively to observe whether the output is correct.

2. The dynamic compression method for lightning waveform data according to claim 1, characterized in that: The encoding module forms an encoding according to the differential term read by the differential module and the record found by the corresponding search module.

3. The dynamic compression method for lightning waveform data according to claim 2, wherein: The control module transmits the compressed data through the microcontroller and the variable static storage controller. The microcontroller judges the format type of the data by the high byte, and the low byte is directly the true value of the encoded data.

4. The dynamic compression method for lightning waveform data according to claim 2, wherein: During the encoding process, the previous read differential term is required as a basis. The previous data is stored through a register, and a FIFO memory is established to store the encoding result.

5. A hardware implementation method for dynamic compression of lightning waveform data, characterized in that: Including the dynamic compression method of lightning waveform data as described in any one of claims 1 to 4, the hardware implementation method includes a sampling chip, an integrated circuit chip, a single-chip microcomputer, and a TF card. Among them, the sampling chip is driven by the integrated circuit chip and outputs sampling data. The integrated circuit chip compresses the data and sends it to the single-chip microcomputer through the variable static storage controller interface. The single-chip microcomputer decompresses the data and transfers it to the TF card.

6. The hardware implementation method for dynamically compressing lightning waveform data according to claim 5, characterized in that: The integrated circuit chip only compresses and saves the data of one waveform and then immediately transfers it to the single-chip microcomputer.

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