Clock frequency synchronization method based on data length counter

Abstract

The present invention belongs to the technical field of clock frequency synchronization, and specifically relates to a clock frequency synchronization method based on a data length counter, comprising a module A and a module B, characterized in that the method comprises the following steps: step one, calculating data length information; step two, transmitting data length information; step three, receiving data length information: a length counter is provided in module B, and after module B receives the data length transmitted by module A, the length counter adds the data length, increases the count of the length counter, and at the same time, the length counter of module B gradually decreases the count according to the output frequency of module B; step four, frequency adjustment of module B; when the count of the length counter is between a high threshold and a low threshold, module B does not adjust the current output frequency, and vice versa, makes corresponding adjustments. The synchronization method only needs to transmit the length information of the data, and does not need to perform real data transmission, so as to save bandwidth and improve network operation efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of clock frequency synchronization, and in particular relates to a clock frequency synchronization method based on a data length counter. Technical Background

[0002] Clock frequency synchronization refers to maintaining a strict and specific relationship between the frequencies or phases of signals, so that the corresponding effective moments appear at the same average rate to maintain all devices in the communication network running at the same rate.

[0003] The existing clock frequency synchronization method requires that each module has the function of mutual frequency synchronization, and the device also needs to be able to lock its own frequency with the input signal frequency. If these functions are not available, synchronization is impossible. There are certain requirements for the system, especially for asynchronous systems, and the applicability is low. Summary of the invention

[0004] The present invention aims to provide a clock frequency synchronization method based on a data length counter, which is suitable for clock frequency synchronization between any two modules in a system to achieve clock frequency transmission.

[0005] The technical solution for achieving the above-mentioned purpose includes the following contents.

[0006] A clock frequency synchronization method based on a data length counter includes a module A and a module B, and includes the following steps:

[0007] Step 1: Calculate the data length information: Set the fixed period of module A to N. Module A will calculate the continuous data received every N clocks to obtain the data length within the period, and then assemble the data length within the period into clock information;

[0008] Step 2: Data length information transmission: The sending component of module A encapsulates the clock information and transmits it to module B. Module B extracts the data length information from the received encapsulated information.

[0009] Step 3, receiving data length information: Module B is provided with a length counter. After module B receives the data length transmitted by module A, the length counter adds the data length and increases the count of the length counter. Meanwhile, the length counter of module B gradually decreases the count according to the output frequency of module B.

[0010] Step 4, frequency adjustment of module B: when the count of the length counter will gradually decrease and reach the pre-configured low threshold, it means that the output frequency of module B is greater than the input frequency of module A. Module B adjusts the output frequency so that the count of the length counter is no longer lower than the low threshold. At this time, the output frequency of module B will not be greater than the input frequency of module A; when the count of the length counter will gradually increase and reach the pre-configured high threshold, it means that the output frequency of module B is less than the input frequency of module A. Module B adjusts the output frequency so that the count of the length counter is no longer higher than the high threshold. At this time, the output frequency of module B will not be less than the input frequency of module A; when the count of the length counter is between the high threshold and the low threshold, module B does not adjust the current output frequency.

[0011] Furthermore, it also includes a clock information recovery step: the clock information output by module A includes a serial number, a data length of the cycle and a data length of each of the previous M cycles, wherein the serial number is a position sequence number identifying the current clock information, and increases by 1 after each transmission of the clock information, and the data length of the cycle is represented by the length of the received data in the current cycle, and M can be determined by a technician in this field according to the quality of the communication channel. The worse the channel quality, the larger the value of M, and vice versa; module B first detects whether the serial number in the extracted clock information differs by 1 from the serial number received last time. If not, it indicates that the clock information is lost, and then the corresponding count is backfilled to complete the clock information recovery.

[0012] Furthermore, M takes a value of 1-6.

[0013] Furthermore, it also includes a clock information compression step: according to the input frequency jitter, the maximum data length received in one cycle is calculated to be Lmax, and the minimum length is Lmin; between Lmax and Lmin, k fixed values ​​are divided, wherein the maximum value is equal to Lmax, and the minimum value is Lmin, and the k is not greater than the bit reserved by the sending component, and the k fixed values ​​are respectively marked with bits, and the system establishes a mapping table according to the corresponding relationship between the bit mark and the data length, and synchronizes the mapping table to modules A and B. In the step 1, if the cycle is connected The received data length is Lt. A fixed value Ln that is closest to Lt is selected from the k fixed values, and the bit identifier corresponding to Ln is filled in the corresponding data length field of the clock information. If Lt is greater than Ln, the data length of the next cycle is added with the difference between Lt and Ln; if Lt is less than Ln, the data length of the next cycle is subtracted from the difference between Ln and Lt; if Lt is equal to Ln, the data length of the next cycle does not need to be calculated additionally; in step three, after the clock information is extracted, the data length information can be obtained according to the correspondence between the bit position and the data length in the mapping table.

[0014] Furthermore, the value of K is 3.

[0015] The present invention uses a data length counter-based method to perform clock frequency synchronization, and only needs to transmit data length information without the need for real data transmission, thereby facilitating bandwidth saving; further optimized is that, due to the poor quality of the information transmission pipeline and other reasons, there is a possibility of clock information loss, the clock frequency will be offset and jittered, and the system will lose packets, the present invention can also detect the loss of clock information and restore the clock frequency information in time, and provide clock frequency synchronization anti-interference performance; if the information transmission bandwidth between modules is limited, and the data length is relatively large and occupies a large position in the clock information, the present invention provides a clock information compression method, replaces the data length with a bit identifier, establishes a mapping table corresponding to several fixed data lengths and different bit identifiers, transmits the closest bit identifier between modules instead of transmitting the actual data length value, and corrects the deviation between the fixed data length and the actual data length in the next cycle, the receiving module can obtain the data length information according to the corresponding relationship between the bit and the data length in the mapping table, thereby realizing the compression of the clock frequency information, having stronger adaptability, and further optimizing the technical solution.

[0016] Compared with the prior art, the present invention has the following characteristics:

[0017] In a synchronous or asynchronous system, clock frequency synchronization can be performed between any two modules through information transmission;

[0018] In the case of partial information loss, the lost information can be restored to avoid frequency oscillation during synchronization;

[0019] The additional overhead of passing synchronization information is small and can be further compressed. DETAILED DESCRIPTION

[0020] The present invention is specifically described below with reference to the embodiments.

[0021] A clock frequency synchronization method based on a data length counter comprises a module A and a module B.

[0022] Step 1: Calculate the data length information: configure the fixed period of module A to be N. Module A calculates the continuous data received every N clocks to obtain the data length within the period, and then assembles the data length within the period into clock information and transmits it to the information sending component in module A;

[0023] Step 2: Data length information transmission: The information sending component in module A packages the clock information into the required format and transmits it to module B, which then extracts the data length information contained in the clock information;

[0024] Step 3, receiving data length information: Module B is provided with a length counter. After module B receives the data length transmitted by module A, the length counter adds the data length and increases the count of the length counter. Meanwhile, the length counter of module B gradually decreases the count according to the output frequency of module B.

[0025] Step 4, frequency adjustment of module B: when the count of the length counter will gradually decrease and reach the pre-configured low threshold, it means that the output frequency of module B is greater than the input frequency of module A. Module B adjusts the output frequency so that the count of the length counter is no longer lower than the low threshold. At this time, the output frequency of module B will not be greater than the input frequency of module A; when the count of the length counter will gradually increase and reach the pre-configured high threshold, it means that the output frequency of module B is less than the input frequency of module A. Module B adjusts the output frequency so that the count of the length counter is no longer higher than the high threshold. At this time, the output frequency of module B will not be less than the input frequency of module A; when the count of the length counter is between the high threshold and the low threshold, module B does not adjust the current output frequency to ensure that the adjusted clock frequency of module B and the clock frequency of module A remain synchronized.

[0026] In view of the poor quality of the information transmission pipeline in the system, if there is packet loss in the system, in order to ensure that the clock information is not lost, a further optimization scheme for the clock frequency synchronization method of the above embodiment is to add a clock information loss detection and recovery step, the specific content is: the clock information assembled by module A also includes a sequence number and the data length of each cycle of the first M cycles. The sequence number is the position sequence number identifying the current clock information. The sequence number increases by 1 after each transmission of the clock information. According to the communication channel quality of this embodiment, the value of M is 4; the content of the clock information is shown in the following table,

[0027]

[0028] Module B first detects whether the sequence number in the extracted clock information differs by 1 from the sequence number received last time. If so, it indicates that the information is transmitted correctly. If not, it indicates that the clock information is lost. Then, the corresponding count is backfilled to complete the clock information recovery.

[0029] For example, when the sequence number differs by 2, it means that the clock information of the previous sequence number is lost, and the data length L1 of the previous cycle in the clock information needs to be backfilled; the length counter increases by the sum of the data length of the previous cycle and the data length of the current cycle, that is, L1 + L0;

[0030] If the sequence number differs by 3, it means that the clock information of the previous two sequence numbers is lost, and the data length L1+L2 of the previous two cycles in the clock information needs to be backfilled; the length counter increases by the sum of the data length of the previous 1st and 2nd cycles and the data length of the current cycle, that is, L1+L2+L0;

[0031] If the serial number differs by 4 or 5, the counting can be performed according to the above method.

[0032] If the data length within the cycle is large, it will occupy a longer bit position. When there is insufficient bandwidth resources, or the data bit width provided by the encapsulation format of the information sending component in the module is insufficient, and the information needs to be fully transmitted, this embodiment also provides an optimization solution for clock information compression, the specific contents are as follows:

[0033] Before starting clock frequency synchronization, a mapping table between data length and bit position identifier needs to be established. This pre-step can be completed by a third party or any module. Before clock synchronization, the mapping table needs to be synchronized to modules A and B. The pre-step is as follows:

[0034] According to the input frequency jitter, the maximum data length received in one cycle is calculated to be Lmax, and the minimum length is Lmin; the data length bit reserved by the sending component in module A of this embodiment is 2, which can identify the maximum value of 4, and divide Lmax and Lmin into 3 fixed values, namely L3, L2, and L1, where L3>L2>L1, then L3 is equal to Lmax, L1 is equal to Lmin,

[0035] L3, L2, and L1 are marked with bits 00, 01, and 10 respectively. The system establishes a mapping table based on the corresponding relationship and synchronizes the mapping table to modules A and B.

[0036] When modules A and B perform clock frequency synchronization, the data length received by module A in this cycle is Lt. Compared with L3, L2, and L1, if L2 is closest to Lt, module A fills the bit mark 01 corresponding to L2 into the data length field of the clock information according to the mapping table. If Lt is greater than L2, the data length of the next cycle is added with the difference between Lt and L2 (Lt-L2); if Lt is less than L2, the data length of the next cycle is subtracted from the difference between L2 and Lt (L2-Lt); if Lt is equal to L2, the data length of the next cycle does not need to be calculated additionally; after module B extracts the clock information, it can obtain the data length information from the bit mark according to the correspondence between the bit and the data length in the mapping table.

[0037] The clock frequency synchronization method of the above embodiment solves the problem of clock synchronization between any two modules in the system, and provides a further optimization method for clock information recovery and clock information compression for data packet loss caused by poor transmission channel quality and limited transmission bandwidth. This method can perform clock synchronization between any modules in a synchronous or asynchronous system through clock information transmission. In the case of partial clock information loss, the lost information can be restored to avoid frequency oscillation during synchronization. The additional overhead of transmitting synchronization information is small, the bandwidth requirement is low, and the adaptability is strong.

Claims

1. A clock frequency synchronization method based on a data length counter, comprising module A and module B, characterized in that: The steps include: Step 1: Calculate the data length information: Set the fixed period of module A to N. Module A will calculate the continuous data received every N clocks to obtain the data length within the period, and then assemble the data length within the period into clock information; Step 2: Data length information transmission: The sending component of module A encapsulates the clock information and transmits it to module B. Module B extracts the data length information from the received encapsulated information. Step 3, receiving data length information: Module B is provided with a length counter. After module B receives the data length transmitted by module A, the length counter adds the data length and increases the count of the length counter. Meanwhile, the length counter of module B gradually decreases the count according to the output frequency of module B. Step 4, frequency adjustment of module B: when the count of the length counter will gradually decrease and reach the pre-configured low threshold, it means that the output frequency of module B is greater than the input frequency of module A. Module B adjusts the output frequency so that the count of the length counter is no longer lower than the low threshold. At this time, the output frequency of module B will not be greater than the input frequency of module A; when the count of the length counter will gradually increase and reach the pre-configured high threshold, it means that the output frequency of module B is less than the input frequency of module A. Module B adjusts the output frequency so that the count of the length counter is no longer higher than the high threshold. At this time, the output frequency of module B will not be less than the input frequency of module A; when the count of the length counter is between the high threshold and the low threshold, module B does not adjust the current output frequency.

2. The clock frequency synchronization method based on data length counter according to claim 1, characterized in that: The method further includes a clock information recovery step: the clock information output by module A includes a sequence number, a data length of the cycle, and a data length of each of the first M cycles, wherein the sequence number is a position sequence number identifying the current clock information, and is incremented by 1 after each transmission of the clock information, and the data length of the cycle is represented by the length of the received data in the cycle, and M is determined according to the quality of the communication channel; Module B first detects whether the sequence number in the extracted clock information differs by 1 from the sequence number received last time. If not, it indicates that the clock information is lost, and then the corresponding count is backfilled to complete the clock information recovery.

3. The clock frequency synchronization method based on data length counter according to claim 2, characterized in that: The value of M is 1-6.

4. The clock frequency synchronization method based on data length counter according to claim 1, characterized in that: It also includes the clock information compression step: According to the input frequency jitter, the maximum data length received in one cycle is calculated to be Lmax, and the minimum length is Lmin; k fixed values ​​are separated between Lmax and Lmin, wherein the maximum value is equal to Lmax, and the minimum value is Lmin, and the k is not greater than the data value that can be identified by the bits reserved by the sending component, and the k fixed values ​​are respectively identified by bits, and the system establishes a mapping table according to the corresponding relationship between the bit identifier and the data length, and synchronizes the mapping table to modules A and B, In the step 1, if the length of the data received in the cycle is Lt, a fixed value Ln closest to Lt is selected from the k fixed values, and the bit identifier corresponding to Ln is filled into the corresponding data length field of the clock information. If Lt is greater than Ln, the data length of the next cycle is added with the difference between Lt and Ln; if Lt is less than Ln, the data length of the next cycle is subtracted from the difference between Ln and Lt; if Lt is equal to Ln, the data length of the next cycle does not need to be additionally calculated. In step three, after the clock information is extracted, the data length information can be obtained according to the correspondence between the bit and the data length.

5. The clock frequency synchronization method based on data length counter according to claim 4, characterized in that: The value of K is 3.

Images