Video processing circuit and related video processing method

Abstract

The present application discloses a video processing circuit and a related video processing method, which is coupled to a memory chip and includes an image processing circuit. The image processing circuit includes a first channel, a second channel and a compression circuit, wherein the two channels process a first image data and a second image data respectively to generate a first processed image data and a second processed image data, and the compression circuit compresses the first processed image data and the second processed image data to generate a first compressed image data and a second compressed image data. A storage block in the memory chip is configured as a ring buffer, which is shared by the first channel and the second channel to store the first compressed image data and the second compressed image data. The memory space of the image processing circuit can be saved.

Description

Technical Field

[0001] The present application relates to the field of video, and in particular to a video processing circuit and a related video processing method. Background Art

[0002] In current video signal processing circuits, since the amount of data in each frame is large and has a high frame rate, a large memory space is required to temporarily store the data. In order to solve the problem of memory requirements, the prior art uses a ring buffer to continuously temporarily store the frame data output from the front-end circuit. When the ring buffer is used, the required memory space can be reduced to the amount of data in one frame or even less than the amount of data in one frame. However, in some applications, if the video signal processing circuit needs to generate frame data for multiple channels, and each channel has a different resolution or frame rate, the circuit design will require each channel to have a corresponding ring buffer for easy management. Therefore, the required memory space cannot be effectively reduced. Summary of the invention

[0003] One of the purposes of the present application is to provide an image processing circuit that can save memory space, which can effectively reduce the required memory space when supporting multiple channels, so as to solve the problems described in the prior art.

[0004] In one embodiment of the present application, a video processing circuit is disclosed, which is coupled to a memory chip and includes an image processing circuit. The image processing circuit includes a first channel, a second channel and a compression circuit, wherein the first channel and the second channel share an input port, wherein the two channels process a first image data and a second image data respectively to generate a first processed image data and a second processed image data, and the compression circuit compresses the first processed image data and the second processed image data to generate a first compressed image data and a second compressed image data. A storage block in the memory chip is configured as a ring buffer, which is shared by the first channel and the second channel to store the first compressed image data and the second compressed image data.

[0005] In one embodiment of the present application, a video processing method is disclosed, which is applied to a video processing circuit, and the video processing circuit is coupled to a memory chip, and includes the following steps: processing a first image data through a first channel of an image processing circuit to generate a first processed image data, and processing a second image data through a second channel of the image processing circuit to generate a second processed image data, wherein the first channel and the second channel share an input port; compressing the first processed image data and the second processed image data to generate a first compressed image data and a second compressed image data respectively; and storing the first compressed image data and the second compressed image data in a ring buffer. Wherein, a storage block in the memory chip is configured as a ring buffer, which is shared by the first channel and the second channel to store the first compressed image data and the second compressed image data.

[0006] The technical solution provided by the embodiment of the present application compresses the processed image data of multiple channels and allows the multiple channels to share the same circular buffer, so that the circular buffer can store more image data or the circular buffer only needs a smaller capacity to meet the needs. By using time-sharing multi-tasking technology to compress the processed image data, only one set of compression circuits is needed to achieve its function, thereby reducing the hardware manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0008] Figure 1 A schematic diagram of a video processing circuit provided in an embodiment of the present application.

[0009] Figure 2 A schematic diagram of an image processing circuit provided in an embodiment of the present application.

[0010] Figure 3 A schematic diagram of a video encoder provided in an embodiment of the present application.

[0011] Figure 4 A schematic diagram of a data table written in accordance with an embodiment of the present application.

[0012] Figure 5 A schematic diagram of using a multiplexer to sequentially transmit items written into a data table to a video encoder according to an embodiment of the present application. DETAILED DESCRIPTION

[0013] Figure 1 FIG. 1 is a schematic diagram of a video processing circuit 100 provided in an embodiment of the present application. Figure 1 As shown, the video processing circuit 100 includes an image processing circuit 110, a ring buffer 120 and a video encoder 130. In this embodiment, the video processing circuit 100 can be applied to an image capture device, which is used to receive image data Din sensed by an image sensor, and process and encode the image data to generate an encoded image data Denc to the back-end circuit for storage or transmission. In one embodiment, the image processing circuit 110 and the video encoder are arranged on the same chip, and the ring buffer 120 can be composed of a dynamic random access memory (DRAM) and arranged on another chip. The ring buffer 120 can be a specific block in a dynamic random access memory chip, which is used to store the image data processed by the video processing circuit 100.

[0014] Figure 2 FIG. 1 is a schematic diagram of an image processing circuit 110 provided in an embodiment of the present application. Figure 2 As shown, the image processing circuit 110 includes a splitter 210, a first channel 220, a second channel 230, selection circuits 241, 242, an arbiter 250, a compression circuit 260, a splitter 270, selection circuits 281, 282, and write direct memory access (WDMA) circuits 280, 290, wherein the first channel 220 includes a crop circuit 222 and a scaling circuit 224; the second channel 230 includes a crop circuit 232 and a scaling circuit 234.

[0015] In the operation of the image processing circuit 110, first, the separation circuit 210 receives the image data Din and divides the image data into the first channel 220 and the second channel 230. In one embodiment, the separation circuit 210 receives the image data Din through a single port, and each of the first channel 220 and the second channel 230 receives the complete image data Din. Next, regarding the operation of the first channel 220, the cutting circuit 222 cuts each frame in the image data Din to leave the required area, and transmits the data of the required area to the scaling circuit 224. The scaling circuit 224 is used to perform an image scaling operation on the data of the required area to generate a processed image data D1, and transmits it to the selection circuit 241. For example, the scaling circuit 224 may include a plurality of scaling units, and the scaling circuit 224 may first perform a vertical image scaling up operation on the received data to generate vertically scaled image data to a line buffer, and then perform a horizontal image scaling up operation on the vertically scaled image data to generate processed image data D1. The operation of the second channel 230 is similar to that of the first channel, and will not be described in detail herein. In practice, the cropping and / or scaling processing performed on the image data Din by the first channel 220 is different from that performed on the image data Din by the second channel 230. For example, the scaling ratio performed on the image data Din by the first channel 220 is different from that performed on the image data Din by the second channel 230. It should be noted that the operation contents and operation sequence of the first channel 220 and the second channel 230 described above are merely exemplary and are not limitations of the present application.

[0016] Next, the selection circuit 241 can transmit the processed image data D1 to the arbiter 250 at an appropriate time point according to the control signal Vc1, and the selection circuit 242 can transmit the processed image data D2 to the arbiter 250 at an appropriate time point according to the control signal Vc2. In one embodiment, the selection circuit 241 and the selection circuit 242 can be implemented as a whole using a multiplexer. The arbiter 250 can be a 2-to-1 arbiter, which is used to select one of the outputs of the selection circuits 241 and 242 to input to the compression circuit 260. The compression circuit 260 can be any type of compression circuit, such as a circuit using the Arm Frame Buffer Compression (AFBC) compression mechanism to alternately compress the processed image data D1 and D2 to generate compressed image data Dcom1 and Dcom2 respectively. Next, the separation circuit 270 transmits the compressed image data Dcom1 to the WDMA circuit 280 through the selection circuit 281 controlled by the control signal Vc3, so as to be written into the ring buffer 120. Similarly, the separation circuit 270 transmits the compressed image data Dcom2 to the WDMA circuit 290 through the selection circuit 282 controlled by the control signal Vc4, so as to be written into the ring buffer 120. That is, the compressed image data Dcom1 generated after processing by the first channel 220 and the compressed image data Dcom2 generated after processing by the second channel 230 share the ring buffer 120.

[0017] The operations of the selection circuits 241, 242, the arbitrator 250, the compression circuit 260, the separation circuit 270, and the selection circuits 281, 282 can be regarded as time-sharing multi-tasking processing of the processed image data D1, D2, that is, the compression circuit 260 is used alternately to process the processed image data D1, D2 to generate corresponding compressed image data Dcom1, Dcom2, respectively, for storage in the ring buffer 120.

[0018] In the image processing circuit 110, by compressing the processed image data D1 and D2 to generate compressed image data Dcom1 and Dcom2 of smaller size, the ring buffer 120 can store more pens of image data, or the ring buffer 120 only needs to be designed with a smaller capacity to meet the needs. In addition, by using time-sharing multitasking technology to process the processed image data D1 and D2, only one set of compression circuits is needed to achieve its function, so the hardware manufacturing cost can be reduced.

[0019] Figure 3 FIG. 1 is a schematic diagram of a video encoder 130 provided in an embodiment of the present application. Figure 3As shown, the video encoder 130 includes a read direct memory access (RDMA) circuit 310, a pre-load circuit 320, a memory 330, a decompression circuit 340, and an encoding circuit 350. In the operation of the video encoder 130, the RDMA circuit 310 reads the compressed image data Dcom1 and Dcom2 previously written by the image processing circuit 110 from the ring buffer 120, and temporarily stores them in the memory 330 through the pre-load circuit 320. The decompression circuit 340 can be a decompression circuit corresponding to the compression circuit 260, such as a decompression circuit using the AFBC mechanism, and performs a decompression operation on the compressed image data Dcom1 and Dcom2 through the pre-load circuit 320 to generate decompressed image data. Then, the encoding circuit performs an encoding operation on the decompressed image data, such as an encoding operation that complies with the H.264 and H.265 specifications of High Efficiency Video Coding, to generate encoded image data Denc.

[0020] In order to effectively reduce the size of the ring buffer 120 without affecting the operations of the image processing circuit 110 and the video encoder 130, and to enable the compressed image data Dcom1 and Dcom2 to share the ring buffer 120, it is necessary to efficiently control the data processing and transmission of the image processing circuit 110 and the video encoder 130, that is, the data of the previous level circuit can be quickly sent to the next level circuit for processing after being processed. The specific contents are described as follows.

[0021] In one embodiment, the video processing circuit 100 configures a storage space / block in a memory chip as a ring buffer 120 through some global buffers. The content stored in the global buffer includes the starting address of the ring buffer 120, the size of the ring buffer 120, the number of items in the ring buffer 120, the current write pointer of the ring buffer 120, the current read pointer of the ring buffer 120, etc. When the WDMA circuits 280 and 290 write the compressed image data Dcom1 and Dcom2 to the ring buffer 120 respectively, the WDMA circuits 280 and 290 will also establish a write data table according to the content of the global buffer to record the information of the data written to the ring buffer 120. Figure 4For example, assuming that the WDMA circuits 280 and 290 create an entry in a write data table 400 when writing compressed image data corresponding to a frame into the ring buffer 120, when the WDMA circuits 280 and 290 write compressed image data corresponding to a first frame into the ring buffer 120, the WDMA circuits 280 and 290 create the starting address of the compressed image data of the first frame in the ring buffer 120, the size of the compressed image data of the first frame, and related information of the compressed image data of the first frame in entry 0 of the write data table 400, wherein the related information includes the state of the compressed image data of the first frame (e.g., preset state, writing in progress, or completed writing), the frame index of the first frame, the channel index (corresponding to the first channel 220 or the second channel 230), etc. The frame index is used to identify the corresponding frame (e.g., frame serial number), and the channel index is used to identify the corresponding channel. Since the ring buffer 120 is shared by the first channel and the second channel, by recording the frame index of each frame and the channel index in each entry, the video encoder 130 can identify and read the data stored in the ring buffer 120 accordingly.

[0022] Similarly, when the WDMA circuits 280 and 290 write compressed image data corresponding to a second frame, a third frame, and a fourth frame into the ring buffer 120, the WDMA circuits 280 and 290 will respectively record the starting address of the compressed image data of the second frame, the third frame, and the fourth frame in the ring buffer 120, the size of the compressed image data, and the related information of the compressed image data in items 1, 2, and 3 of the write data table 400. Next, when the WDMA circuits 280 and 290 write compressed image data corresponding to a fifth frame into the ring buffer 120, the WDMA circuits 280 and 290 will respectively record the information of the fifth frame in item 0 of the write data table 400 to overwrite the information of the first frame stored previously.

[0023] In one embodiment, the write data table 400 may be stored in a first buffer corresponding to the WDMA circuits 280 and 290. The first buffer may be composed of a plurality of buffer units for storing a plurality of items in the write data table. The RDMA circuit 310 in the video encoder 130 may establish a read data table to record information of data read from the ring buffer 120. The read data table may be stored in a second buffer. The second buffer is also composed of buffer units. In practice, the read data table may include only one item. Therefore, the buffer units in the second buffer are less than the buffer units in the first buffer, thereby reducing the hardware cost of the second buffer.

[0024] In one embodiment, a mechanism can be used to transfer the data of each item in the write data table 400 in the first buffer to the read data table in the second buffer, so that the video encoder 130 can read the image data in the ring buffer 120. In one embodiment, the first buffer and the second buffer are connected by a dedicated hardware line, that is, the process of obtaining the write data table 400 for the video encoder 130 does not need to be controlled by the central processor or software. Figure 5 For example, the image processing circuit 110 may include a multiplexer 510, which selects item 0, item 1, item 2, and item 3 in sequence according to a selection signal Vs, and then reselects item 0, item 1, item 2, item 3, and so on, so as to transmit the start address, size, and information of the corresponding frame to the video encoder 130. In addition, in one embodiment, the selection signal Vs is generated by the video encoder 130 and is a frequency signal with a specific frequency. The video encoder 130 can select an item in the write data table 400 through the selection signal Vs, and the multiplexer 510 can be triggered by the rising edge of the selection signal Vs to transmit the content of an item to the second register, that is, in each cycle of the frequency signal, the video encoder 130 can obtain the information of an item from the write data table 400 to the read data table.

[0025] After receiving the starting address, size, and information of a certain item, for example, the starting address, size, and frame-related information of the compressed data of the first frame in the ring buffer 120 of item 0, the video encoder 130 can know the address of the compressed data of the first frame in the ring buffer 120, the corresponding frame number, and the channel information according to the content of item 0, and read the compressed data of the first frame from the ring buffer 120 for subsequent operations. In another embodiment, after reading and writing multiple items in the data table 400, the video encoder 130 can determine the subsequent process of encoding the compressed data in the ring buffer 120 according to the contents of the multiple items.

[0026] exist Figure 4 , Figure 5 In the embodiment of the present invention, by transmitting the data written in the data table 400 to the second buffer corresponding to the video encoder 130, the video encoder 130 can quickly read the required data from the ring buffer 120. In addition, by using the multiplexer 510, data of different items can be transmitted to the video encoder 130 in sequence under the condition that only one hardware circuit is required, so as to reduce the hardware cost.

[0027] In one embodiment, since the image data Din includes brightness (Y) and chrominance (UV) data, the ring buffer 120 may include a first ring buffer and a second ring buffer, wherein the first ring buffer is used to store the compressed brightness data, and the second ring buffer is used to store the compressed chrominance data. Figure 4 , Figure 5 In an embodiment of the write data table 400, the starting address, size, and information carried by each item in the write data table 400 may include the starting address of the compressed luminance data in the first ring buffer, the size of the compressed luminance data, and the information of the compressed luminance data, the starting address of the compressed chrominance data in the second ring buffer, the size of the compressed chrominance data, and the information of the compressed chrominance data, wherein the information of the compressed luminance data includes the state of the compressed luminance data (for example, the preset state, being written, or having been written), and the related frame index and channel index, and the information of the compressed chrominance data includes the state of the compressed chrominance data (for example, the preset state, being written, or having been written), and the related frame index and channel index. In another embodiment, since the image data Din may further include luminance header and chrominance header data, in addition to the above-mentioned first ring buffer and second ring buffer, the ring buffer 120 may further include a third ring buffer and a fourth ring buffer, the third ring buffer is used to store the compressed luminance header data, and the fourth ring buffer is used to store the compressed chrominance header data. At this time, in Figure 4 , Figure 5 In the embodiment of the present invention, the starting address, size, and information of each item in the write data table 400 may further include the starting address of the compressed luminance header data in the third ring buffer, the size of the compressed luminance data, and the information of the compressed luminance header data, the starting address of the compressed chrominance header data in the second ring buffer, the size of the compressed chrominance header data, and the information of the compressed chrominance header data. As described above, by writing the content of each item in the above-mentioned write data table 400, the video encoder 130 can obtain the relevant information of the luminance and chrominance data at one time, so as to improve the reading efficiency of the video encoder 130.

[0028] It should be noted that in Figure 1 In the embodiment of the present invention, the image processing circuit 110 writes the compressed image data into the ring buffer 120 for use by the video encoder 130, but the present application is not limited thereto. In other embodiments of the present application, the video encoder 130 can be replaced by other post-stage circuits, such as a post-stage image processing circuit. These design changes should belong to the scope of the present application.

[0029] To briefly summarize the present application, in the video processing circuit of the present application, by compressing the processed image data of multiple channels and allowing multiple channels to share the same ring buffer, the ring buffer can store more pens of image data or the ring buffer only needs a smaller capacity to meet the needs, and by using time-sharing multi-tasking technology to compress the processed image data, only one set of compression circuits can be used to achieve its function, so the hardware manufacturing cost can be reduced. In addition, an embodiment of the present application also establishes a write data table, which includes the starting address, size, status, frame index and channel index of the compressed data of each frame in the ring buffer, and each item can be transmitted to the subsequent circuit through the multiplexer to efficiently read the required data from the ring buffer.

[0030] The above description is only a preferred embodiment of the present application. All equivalent changes and modifications made according to the scope of the patent application of the present application shall fall within the scope of the present application.

[0031] 100: video processing circuit;

[0032] 110: image processing circuit;

[0033] 120: Ring buffer;

[0034] 130: video encoder;

[0035] Din: image data;

[0036] Denc: encoded image data;

[0037] 210: separation circuit;

[0038] 220: first channel;

[0039] 222: Cutting circuit;

[0040] 224: scaling circuit;

[0041] 230: Second channel;

[0042] 232: Cutting circuit;

[0043] 234: Scaling circuit;

[0044] 241, 242: Select circuit;

[0045] 250: arbitrator;

[0046] 260: compression circuit;

[0047] 270: Separation circuit;

[0048] 281,282: Select circuit;

[0049] 280,290: WDMA circuit;

[0050] D1, D2: processed image data;

[0051] Dcom1, Dcom2: compressed image data;

[0052] Vc1, Vc2, Vc3, Vc4: control signals;

[0053] 310: RDMA circuit;

[0054] 320: preloading circuit;

[0055] 330: Memory;

[0056] 340: decompression circuit;

[0057] 350: encoding circuit;

[0058] 400: write to data table;

[0059] 510: Multitasker;

[0060] Vs: Select signal.

Claims

1. A video processing circuit coupled to a memory chip, characterized in that: include: Image processing circuit, comprising: a first channel and a second channel, the first channel and the second channel sharing an input port, wherein the first channel processes first image data to generate first processed image data, and the second channel processes second image data to generate second processed image data; and A compression circuit, used for compressing the first processed image data and the second processed image data to generate first compressed image data and second compressed image data; Wherein, a storage block in the memory chip is configured as a ring buffer, shared by the first channel and the second channel, to store the first compressed image data and the second compressed image data; The image processing circuit further includes: A write direct memory access circuit, coupled between the compression circuit and the ring buffer, for writing the first compressed image data and the second compressed image data into the ring buffer; Wherein, the write direct memory access circuit is used to establish a write data table, the write data table includes a plurality of items, and each item is used to record information of a data written into the ring buffer; The video processing circuit also includes: A subsequent circuit, configured to read the first compressed image data or the second compressed image data from the ring buffer for processing; The write data table is stored in a first buffer, and the subsequent circuit uses a second buffer to receive data of the plurality of items in the write data table to access the ring buffer; Wherein, a dedicated line is provided between the second buffer and the first buffer to connect the second buffer and the first buffer; The number of storage units in the second buffer is less than the number of storage units in the first buffer.

2. The video processing circuit according to claim 1, characterized in that: The data is compressed image data corresponding to a frame in the first compressed image data or the second compressed image data, and each of the items includes a starting address of the data in the ring buffer, a size of the data, a frame index corresponding to the frame, and a channel index for indicating the first channel or the second channel.

3. The video processing circuit according to claim 2, characterized in that: Each of the items further includes a state of the data, where the state of the data indicates that the write direct memory access circuit is writing the data into the circular buffer, or the data has been successfully written into the circular buffer.

4. The video processing circuit according to claim 1, characterized in that: The image processing circuit further includes a multiplexer, and the multiplexer transmits data of a corresponding item in the plurality of items in the write data table to the second buffer according to a selection signal.

5. The video processing circuit according to claim 1, characterized in that: The latter circuit is a video encoder.

6. A video processing method, applied to a video processing circuit, wherein the video processing circuit is coupled to a memory chip, the method comprising: Processing the first image data through a first channel of an image processing circuit to generate first processed image data, and processing the second image data through a second channel of the image processing circuit to generate second processed image data, wherein the first channel and the second channel share an input port; compressing the first processed image data and the second processed image data to generate first compressed image data and second compressed image data respectively; and storing the first compressed image data and the second compressed image data in a ring buffer; Wherein, a storage block in the memory chip is configured as the ring buffer, shared by the first channel and the second channel, to store the first compressed image data and the second compressed image data; The method further comprises: Establishing a write data table, wherein the write data table includes a plurality of items, and each item is used to record information of a data written into the ring buffer; The method further comprises: Reading the first compressed image data or the second compressed image data from the ring buffer through a subsequent circuit for processing; The write data table is stored in a first buffer, and the subsequent circuit uses a second buffer to receive data of the plurality of items in the write data table to access the ring buffer; Wherein, a dedicated line is provided between the second buffer and the first buffer to connect the second buffer and the first buffer; The number of storage units in the second buffer is less than the number of storage units in the first buffer.

7. The video processing method according to claim 6, characterized in that: The data is compressed image data corresponding to a frame in the first compressed image data or the second compressed image data, and each of the items includes a starting address of the data in the ring buffer, a size of the data, a frame index corresponding to the frame, and a channel index for indicating the first channel or the second channel.

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