SG SOI Semiconductor Device Modeling Method

Abstract

This invention relates to a modeling method for SGSOI semiconductor devices, comprising the following steps: constructing a mathematical model of the SGSOI semiconductor device using a script; importing the script into a circuit simulator; and obtaining the semiconductor device model of the SGSOI semiconductor device by acquiring the semiconductor device parameter information within the mathematical model in the script, thereby realizing the modeling of the semiconductor device. The SGSOI semiconductor device modeling method of this invention utilizes parabolic approximation and perturbation methods to calculate the relationship between the channel surface potential, carrier subband energy levels, and various parameters, solving the difficulty in describing ballistic transport and quantum confinement effects in existing technologies. This helps improve the simulation verification of circuit design, providing support for chip design; simultaneously, it meets the needs of efficient circuit design and development, providing direction for semiconductor process development.

Description

Technical Field

[0001] This invention relates to the field of modeling, and in particular to a method for modeling SG SOI semiconductor devices. Background Technology

[0002] With the rapid development of the semiconductor industry and the continuous updating of semiconductor device processes and structures, various high-performance and high-reliability semiconductor devices have emerged. As device dimensions become increasingly smaller, the degradation of device characteristics caused by discrete impurity fluctuations, short-channel effects, and reduced threshold voltages becomes increasingly significant. In traditional bulk silicon MOSFETs, increasing the substrate impurity concentration can reduce the depletion layer width near the source / drain-bulk junction, thereby suppressing short-channel effects. In bulk silicon MOSFETs, electric field lines from the source and drain propagate through the depletion layer region of the source-drain junction to the channel region, affecting the electrostatic potential distribution within the channel. As device channel lengths enter the range of less than 20nm, the gate's ability to control the electrostatics within the device channel continuously decreases, making short-channel effects such as threshold voltage reduction and the DIBL effect crucial considerations. Therefore, with further advancements in device miniaturization, it is necessary to propose new MOSFET structures to suppress short-channel effects. Computational models of SGSOI (Surrounding Gate Silicon on Insulator) semiconductor devices are widely used in semiconductor manufacturing and design. Their ability to flexibly adjust various physical process parameters can meet the needs of upstream chip design and also provide feedback and guidance for downstream process line improvements. SGSOI technology can be extensively applied in low-voltage, low-power radio frequency integrated circuit design. SGSOI semiconductor devices are highly anticipated for their superior electrostatic control. With appropriate modeling and numerical simulation, the behavior and characteristics of devices can be predicted. However, various numerical simulators have been developed to date, but such numerical calculations require enormous amounts of time and are not suitable for large-scale circuit simulators. Therefore, there is an urgent need to develop analytical physical models that simultaneously meet the requirements of computational accuracy and efficiency.

[0003] In the current semiconductor chip design process, intensive modeling using analytical numerical calculations has become indispensable. In short-channel devices, ballistic transport effects are increasingly prominent and play a dominant role. The intensive physical modeling of short-channel nanoscale CMOS devices includes: (1) the introduction of ballistic transport effects; (2) the introduction of quantum confinement effects; and (3) the introduction of AC characteristics. In order to obtain the electrical characteristics of SGSOI semiconductor devices accurately and efficiently, analytical intensive modeling calculations are required for the characteristics of SGSOI semiconductor devices. The analytical intensive model of the SGSOI semiconductor device should meet the requirements of high accuracy and high efficiency in calculating relevant electrical parameters under a wide range of geometric structures and bias voltages.

[0004] Therefore, how to establish a method that can describe ballistic transport effects based on quantum transport characteristics within the effective conditions of device characteristic effects and within the short-channel device structure range, has a wide range of physical parameter scaling functions to help improve the simulation verification of circuit design, and is suitable for large-scale integrated circuit simulation to meet the needs of efficient circuit design and development has become one of the problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned need for short-channel device technology, the purpose of this invention is to provide an SG SOI semiconductor device modeling method to solve the problems in the prior art, such as the inability of the model to describe ballistic transport effects based on quantum transport characteristics, the lack of wide-range physical parameter scaling function, the inability to help improve the simulation verification of circuit design, and the difficulty in meeting the needs of efficient and high-precision computational modeling for large-scale integrated circuit simulation and efficient circuit design and development.

[0006] The technical solution adopted by this invention to achieve the above objectives is: an SG SOI semiconductor device modeling method, comprising the following steps:

[0007] A mathematical model of an SG SOI semiconductor device is constructed using a script;

[0008] Import the script into the circuit simulator;

[0009] By obtaining the semiconductor device parameter information from the mathematical model within the script, the semiconductor device model of the SG SOI semiconductor device is obtained, thus realizing the modeling of the semiconductor device.

[0010] The mathematical model of the SGSOI semiconductor device is the same as that of a long-channel N-type SGSOI metal-oxide-semiconductor field-effect transistor:

[0011]

[0012] Where, k BT Let represent Boltzmann's constant, absolute temperature, and Planck's constant, respectively; r represents the radius component of the circular cross-section perpendicular to the carrier conduction direction within the channel; and Q... eline Let Q be the charge density of the electromagnetic field based on Gauss's law. qline Here, m is the charge density calculated based on quantum statistical theory, m0 is the electron mass in vacuum, and m C * n is the effective mass of charge carriers in the transmission direction. v The valley index of the band structure. This indicates the valley degeneracy of a specific band structure. This represents the subband energy level of charge carriers in the conduction band, with the superscript q0 indicating the non-perturbation term charge carrier energy level. Indicates the first The nth order of the first type of Bessel function r A zero-point value, This represents the effective mass of the charge carriers in the radial direction (r-direction) within the confined cross section of the SGSOI channel. and n r V represents the quantum number of the angular component and the quantum number of the radius component, respectively. DS The source-drain voltage is given by E. F，S and E F，D The difference between them determines, E F，S and E F，D R represents the Fermi level at the source and drain ends, respectively. ref V is the backscattering constant of charge carriers at the potential energy barrier. t Let w be the thermal voltage, and w be the electrostatic potential distribution function within the channel; R be the radius of the circular cross-section of the SG SOI channel; q represent the unit charge; and ΔU G The parameters are assumed to correlate the channel surface potential with the potential difference between the channel surface and the center. w represents the perturbation constant of each subband energy level of the charge carrier. S This represents the channel surface potential of the SG SOI semiconductor device.

[0013] The mathematical model of the SGSOI semiconductor device is the same as that of a long-channel N-type SGSOI metal-oxide-semiconductor field-effect transistor:

[0014] In the subthreshold range, i.e., when the gate-source voltage is less than the threshold voltage at which the semiconductor device turns on:

[0015]

[0016] In the deep inversion layer region, i.e., when the gate-source voltage is greater than the threshold voltage for the semiconductor device to turn on:

[0017]

[0018] w S This represents the channel surface potential of the SG SOI semiconductor device.

[0019] The long channel refers to the true semiconductor channel of an SGSOI semiconductor device with a true semiconductor channel length greater than 20 nm.

[0020] The mathematical model of the SG SOI semiconductor device is the mathematical model of a short-channel N-type SG SOI metal-oxide-semiconductor field-effect transistor:

[0021] The carrier subband energy levels distributed along the channel direction are as follows:

[0022]

[0023] Among them, all charge carriers contributing to the ballistic / quasi-ballistic current can only exist at the maximum value E at the top of the barrier within the channel. MAX Within the above energy range, z MAX The location of the potential barrier vertex in the channel direction:

[0024]

[0025]

[0026] in, The effective mass of the charge carrier in the radius r direction within the confined cross section of the SGSOI channel. Indicates the first The nth order of the first type of Bessel function r There are zero-point values, m r *P =2(m t -1 +m l -1 ) -1 m r *P m represents the effective mass of the P-type charge carrier in the radial direction (r) within the SGSOI confinement section. t -1 m l -1 Let U represent the effective mass of the charge carrier along the minor and major axes of the ellipsoidal isoenergetic surface near the bottom of the conduction band, respectively, where z is the conduction direction axis of the charge carrier, and ΔU G The parameter w is the hypothetical relationship between the channel surface potential and the center potential difference. SLet γ be the channel surface potential of the SG SOI semiconductor device, r be the radius component of the circular cross section perpendicular to the carrier conduction direction in the channel, A and B be the correlation calculation coefficients for the gate-source voltage and drain-source voltage, respectively, and γ be a scaling factor dependent on the device structure.

[0027] The short channel is a true semiconductor channel of an SGSOI semiconductor device with a channel length of less than 20 nm and greater than 10 nm.

[0028] The mathematical model of the SG SOI semiconductor device is a mathematical model for the transient capacitance applied to the AC analysis of the device:

[0029] The capacitance model between the gate and source / drain is as follows:

[0030]

[0031]

[0032] C GS，G For the gate-source equivalent circuit capacitance based on device AC analysis, C GD，G Q is the equivalent gate-source capacitance based on the AC analytical solution of the device. eline V represents the one-dimensional carrier charge density distribution within the channel of an SG SOI semiconductor device along the source-drain direction, which is time-correlated. G L is the voltage applied to the gate. G denoted as , where z is the channel length of the SGSOI semiconductor device, and z is the conduction direction axis of the charge carriers.

[0033] The mathematical model of the SG SOI semiconductor device is the same as that of the P-type SG SOI metal-oxide-semiconductor field-effect transistor:

[0034] The effective carrier mass m is obtained using general-purpose device simulation software. z Substituting the effective mass m of the channel carriers into the mathematical model of the N-type SGSOI metal-oxide-semiconductor field-effect transistor... C * P-type SG SOI metal-oxide-semiconductor field-effect transistors were obtained.

[0035]

[0036]

[0037]

[0038] in, This represents the unperturbed conjugate carrier wavefunction within the confined potential well. This represents the unperturbed carrier wavefunction within the confined potential well. Let m be the perturbation constant of each subband energy level of the charge carrier. r *P =2(m t -1 +m l -1 ) -1 m is the effective mass of the charge carrier in the radial direction within the confined cross section of the SG SOI channel. t -1 m l -1 These represent the effective mass of the charge carrier along the minor and major axes of the ellipsoidal isoenergetic surface near the bottom of the conduction band, respectively. This represents the energy level of the valence charge carrier subband. The q0 represents the carrier subband energy level with quantum confinement effect of the valence band, and the superscript q0 represents the carrier energy level without perturbation.

[0039] The script is a Verilog-A file.

[0040] The semiconductor device model of the SG SOI semiconductor device is obtained by acquiring the semiconductor device parameter information from the mathematical model within the script, including the following steps:

[0041] By querying the parameter information and mathematical model contained in the semiconductor device model within the script, the voltage and current values ​​of the ballistic / quasi-ballistic current corresponding to the channel surface potential and the carrier subband energy level are extracted. The voltage and current values ​​are then imported into the device behavior description module in the circuit simulator. The circuit netlist using the SGSOI semiconductor device model is generated and saved according to the circuit design software.

[0042] Based on the derivation of the various input and output nodes of the device in the netlist and the mapping relationship between the nodes, a semiconductor device model containing a description of the relationship between the bias voltage of each endpoint and the ballistic / quasi-ballistic current in the device channel is generated.

[0043] The semiconductor device model contains the following parameter information:

[0044] Channel surface potential w of SG SOI semiconductor device S Subband energy levels of charge carriers in the conduction band Ballistic / quasi-ballistic current I DS Channel radius R, channel length L G Gate-source voltage V GS Drain-source voltage V DS Effective oxide film thickness T OX The built-in source-channel junction voltage V associated with the channel radius R bi Valley degeneracy of band structure

[0045] The present invention has the following beneficial effects and advantages:

[0046] 1. The SG SOI semiconductor device modeling method of the present invention uses parabolic approximation and perturbation method to calculate the relationship between the channel surface potential, carrier subband energy level and various parameters, which solves the difficulty of existing models in describing ballistic transport and quantum confinement effects, thereby helping to improve the simulation verification of circuit design and providing support for chip design; at the same time, it meets the needs of efficient circuit design and development and provides direction for semiconductor process development.

[0047] 2. This invention enables the creation of scripts and rapid reading and querying via SPICE software for high-precision circuit characteristic simulation, thereby achieving batch development of SGSOI semiconductor device models to meet the requirements of high accuracy and high efficiency in simulation calculations. Attached Figure Description

[0048] Figure 1 The diagram shown illustrates one embodiment of the SG SOI semiconductor device modeling method of the present invention.

[0049] Figure 2 The diagram shown is a schematic of the structure of an SG SOI metal-oxide-semiconductor field-effect transistor in the prior art.

[0050] Figure 3 The diagram shows the band structure along the inner radius of the SG SOI carrier quantum confinement cross section of this invention.

[0051] Figure 4 The diagram shows the band structure in the channel direction of the SG SOI carrier conduction section of the present invention.

[0052] Figure 5 The diagram shows the carrier scattering mechanism within the SG SOI semiconductor device of the present invention.

[0053] Figure 6 The diagram shown is an AC equivalent circuit diagram of the present invention.

[0054] Figure 7 The diagram shown illustrates one embodiment of the SG SOI semiconductor device modeling method of the present invention.

[0055] Wherein: 1, long-channel N-type SG SOI metal oxide semiconductor field-effect transistor, 11, true silicon semiconductor channel, 12, silicon dioxide insulating oxide layer, 13, N-type heavily doped silicon channel, S11-S13 represent steps. Detailed Implementation

[0056] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0057] Semiconductor device modeling methods include at least:

[0058] Provide an SG SOI semiconductor device, list the nonlinear equation of the channel surface potential of the SG SOI semiconductor device, scan several parameters in the nonlinear equation of the channel surface potential, and establish the relationship between the channel surface potential and each parameter.

[0059] The relationship between the channel surface potential, carrier subband energy levels and various parameters is calculated using parabolic approximation and perturbation methods.

[0060] Based on the channel surface potential, carrier subband energy levels, and the ballistic transport mode of the carriers in the SG SOI semiconductor device characterized by the approximation method already adopted, the channel current expression and charge expression are derived to obtain the model of the semiconductor device.

[0061] Preferably, the parameters include one or more of the following: process parameters, device bias voltage, operating temperature, ambient electric field, magnetic field, radiation environment, light exposure, or pressure information on the device.

[0062] Preferably, the analytical equation of the channel surface potential is solved by approximation using a parabola to establish the relationship between the channel surface potential and each parameter; the analytical equation of the carrier subband energy level is solved by approximation using a perturbation method to establish the relationship between the carrier subband energy level and each parameter.

[0063] More preferably, the methods for solving the analytical equations of the channel surface potential and the carrier subband energy level include the parabolic approximation method, the perturbation approximation method, the numerical integration approximation method, and the combined equation optimization method.

[0064] Preferably, simulation software is used to simulate the relationship between the channel surface potential and various parameters, thereby establishing the relationship between the channel surface potential and various parameters.

[0065] Preferably, the method for solving the analytical equation of the channel surface potential includes an analysis method of the barrier formation mechanism at the semiconductor-silicon interface and an approximate method of parabolic distribution of electrostatic potential within the SGSOI; the method for solving the analytical equation of the carrier subband energy level includes a combined equation optimization method based on quantum statistics for carrier density calculation and based on the classical Gaussian law for carrier density calculation, an analytical approximation method of the Fermi integral function, a perturbation approximation method of carrier quantum confinement energy levels, and a Laplace approximation method for calculating the potential energy barrier distribution within the SGSOI in the carrier conduction direction. This is used to calculate the relationship between the channel surface potential, carrier subband energy levels, and various parameters.

[0066] More preferably, the analytical relationship between the channel surface potential and various parameters is described by combining the analysis and calculation of the barrier formation mechanism at the semiconductor-silicon interface with the parabolic approximation of the electrostatic potential distribution in the cross section of the SG SOI.

[0067] More preferably, by solving the combined equations of charge density in classical theory and one-dimensional electron density in majority carrier bands in quantum statistical theory, and simultaneously using the interval approximate analytical calculation of the Fermi integral function, and substituting it into the perturbation approximation equation of the carrier quantum confinement energy level, an analytical expression describing the relationship between the carrier subband energy level and each parameter is obtained.

[0068] Preferably, after obtaining the channel current expression and the charge expression, the channel current expression and the charge expression are optimized for carrier saturation effect or drain-induced barrier effect.

[0069] More preferably, the correlation parameter of a channel surface potential is defined by utilizing the axial symmetry of the circular cross-section of the SG SOI semiconductor device. The correlation parameter of the channel surface potential is used to replace the expression equation of the channel surface potential of the SG SOI semiconductor device. The relationship between the carrier subband energy level and each parameter is calculated by using the perturbation approximation. The expression of the channel current is derived based on the carrier ballistic transport equation. Then, the expression of the charge is calculated based on the classical electrostatic Gauss theorem or based on quantum statistical theory to obtain the model of the semiconductor device.

[0070] Preferably, the parameters include gate capacitance, intermediate external bias voltage, and gate voltage after flat-band voltage correction. The channel surface potential and intermediate external bias voltage satisfy the following relationship:

[0071]

[0072]

[0073] Among them, w S ε represents the channel surface potential of the SG SOI semiconductor device. CH With ε OX The dielectric constants of the SG SOI true semiconductor channel and the gate oxide insulator, respectively, are V. GS =V G -V S Here, q represents the gate-source bias voltage, and q represents the unit charge. The difference between the work functions of the gate and the channel, i.e., the work function of the metal gate. Work function of true silicon semiconductor The difference, The electrostatic potential difference, w, represents the work function between the gate and the channel. FBCorresponding to the conduction band bottom potential under flat band conditions, the electron affinity electrostatic potential χ of the true silicon semiconductor channel is... CH / q Its work function Decision, χ CH For electron affinity, T OX R is the effective thickness of the gate oxide, defined as the radius of the circular cross-section of the SG SOI, and ΔU G The associated hypothesis parameter is defined as the channel surface potential, which is the potential difference between the channel surface and the center.

[0074] Preferably, the parameters include operating temperature, SG SOI semiconductor device structural dimensions, and the carrier subband energy levels and external bias intermediate values ​​satisfy the following relationship:

[0075]

[0076]

[0077]

[0078]

[0079] Among them, E z E represents the kinetic energy of the charge carriers in the conduction direction. total The total energy of a charge carrier. Represented as a subband energy level of charge carriers in the conduction band, with the upper right corner q indicating the subband energy level of charge carriers due to quantum confinement effect. and n r These represent the quantum numbers of the angular component and the quantum number of the radius component, respectively. This represents the unperturbed carrier wavefunction within the confined potential well. This represents the perturbation constant of each sub-band energy level of the charge carrier. Perturbation theory can describe the relationship between the electronic energy level distribution within the channel cross-section and the bias voltage. t -1 m l -1 Let m represent the effective mass of the charge carrier along the minor and major axes of the ellipsoidal isoenergetic surface near the bottom of the conduction band, respectively. r * =2(m t -1 +m l -1 ) is the effective mass of the charge carrier in the radial direction within the SG SOI confinement section, and is the th The nth order of the first type of Bessel function r There are zero-point values. Due to the symmetry of the SG SOI cross section about its central axis, the angular components can be ignored when calculating the carrier wavefunction, and only the distribution in the radial direction needs to be considered.

[0080] Please see Figures 1-6 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0081] Example 1

[0082] like Figures 1-3 As shown, this embodiment provides an SG SOI semiconductor device modeling method, which includes:

[0083] Step S11: Provide a long-channel N-type SGSOI metal-oxide-semiconductor field-effect transistor (MOSFET) device. List the channel surface potential and carrier subband energy level equations for the semiconductor device. Scan several parameters in the channel surface potential and carrier subband energy level equations to establish the relationship between the channel surface potential, carrier subband energy levels, and each parameter. Assume that the electrostatic potential distribution within the channel cross-section of the semiconductor device can be approximately calculated by a quadratic function of an associated assumed parameter. This unknown parameter is obtained by calculating the potential difference between the channel and the gate oxide insulation interface and the channel center. Establish this associated assumed parameter ΔU. G The relationship with each parameter.

[0084] Specifically, step S111: In this embodiment, a long-channel N-type SGSOI metal-oxide-semiconductor field-effect transistor 1 is provided, such as... Figure 2 As shown, the long-channel SG SOI metal-oxide-semiconductor field-effect transistor 1 includes a true silicon semiconductor channel 11, a silicon dioxide insulating oxide layer 12 forming on the upper and lower layers of the true silicon semiconductor channel 11, a gate structure G formed on the silicon dioxide insulating oxide layer 12, and N-type heavily doped silicon channels 13 formed on the left and right sides of the true silicon semiconductor channel 11. A source structure S and a drain structure D are formed on both sides of the N-type heavily doped silicon channels 13 at both ends. Based on the physical parameters of the long-channel N-type SG SOI metal-oxide-semiconductor field-effect transistor 1, the corresponding associated assumption parameter ΔU is obtained. G Numerical calculation of the system of equations.

[0085] Specifically, in this embodiment, the carrier transport mode of the long-channel SG SOI metal-oxide-semiconductor field-effect transistor 1 is ballistic / quasi-ballistic transport. The carrier conduction behavior within the channel is as follows: Figure 5There are three different conduction mechanisms: (a) carrier components injected from the source / drain; (b) carrier components reflected back to the source / drain after scattering; and (c) carrier components injected from the drain / source. Simultaneously, by combining the equations for the cylindrical SG SOI line charge density based on Gauss's law and the majority carrier band line charge density based on quantum statistics, we can construct an equation regarding ΔU. G The nonlinear equations satisfy the following relationship:

[0086]

[0087] Where q represents the unit charge, k B T These represent Boltzmann's constant, absolute temperature, and Planck's constant, respectively; r represents the radial component of the cross-section; and Q... eline Q is the line charge density of a classical electromagnetic field. qline Let m be the one-dimensional charge density in quantum statistical theory, m0 be the electron mass in vacuum, and m C * n is the effective mass of charge carriers in the transmission direction. v The valley index of the band structure, g nv E represents the degeneracy of a specific valley. F，S and E F，D E represents the Fermi level at the source and drain terminals, respectively. total The total energy of a charge carrier. Represented as the subband energy level of charge carriers in the conduction band. Represented as carrier subband energy levels with conduction band quantum confinement effect, with the superscript q0 indicating the carrier energy level without perturbation. and n r V represents the quantum number of the angular component and the quantum number of the radius component, respectively. DS The source-drain voltage is given by E. F，S and E F，D The difference between them determines R ref V is the backscattering constant of charge carriers at the potential energy barrier. t Let w be the thermal voltage, and w be defined as the electrostatic potential distribution function within the channel. The electrostatic potential energy distribution along the radial cross-section can be approximated by a quadratic function, satisfying the following relationship:

[0088]

[0089] Correspondingly, numerical methods can be used to calculate the nonlinear equation of the channel surface potential, establish the relationship between the channel surface potential and various parameters, and verify the accuracy of the model of the long-channel SG SOI metal-oxide-semiconductor field-effect transistor. -1 / 2(a) is a Fermi integral function of order -1 / 2, satisfying the following relation:

[0090]

[0091] y represents the integrand of the Fermi integral function, and a represents the constant variable of the Fermi integral function.

[0092] Specifically, step 112: In this embodiment, the approximate calculation equations for the Fermi integral function in the multi-carrier band line charge density based on quantum statistics are selected in different intervals to correspond to the characteristic performance of the long-channel SG SOI metal-oxide-semiconductor field-effect transistor 1 under different operating conditions, satisfying the following relationship:

[0093]

[0094] Specifically, step 113: In this embodiment, by assuming that the linear charge density based on Gauss's law is equal to the one-dimensional charge density of the majority carrier band based on quantum statistics, and by using the analytical approximation calculations in the above different intervals, the following relationship can be obtained in the subthreshold interval:

[0095]

[0096] The following relationship can be obtained in the deep inversion layer region:

[0097]

[0098] It should be noted that, according to the approximate calculation equations for each working interval in S112 above, ΔU is within the subthreshold interval. G ≈0, and the highest-order term within the deep inversion layer interval can yield a term related to ΔU. G The unique solution to a quartic equation in one variable.

[0099] Step 12: Based on the parameters characterized by the above method, combined with Landauer theory and the ballistic transport-based carrier conduction mode of the semiconductor device, derive the channel current expression and charge expression of the long-channel N-type SG SOI metal-oxide-semiconductor field-effect transistor 1, and obtain the model of the semiconductor device.

[0100] Specifically, in this embodiment, the carrier transport mode of the long-channel N-type SGSOI metal-oxide-semiconductor field-effect transistor 1 is ballistic / quasi-ballistic transport, that is, the carriers in the channel have a certain probability of backscattering caused by phonons, and the effect is reflected in the calculation of the carrier conduction coefficient in each subband. Therefore, the equation for the ballistic / quasi-ballistic transport current in the channel can be derived, satisfying the following relationship:

[0101]

[0102] Among them, the ballistic / quasi-ballistic current I between the source and drain. DS It is believed that charge carriers are transported from the source to the drain with a probability of 1-Rref.

[0103] It should be noted that during the modeling and calculation process, the influence of discrete dopants that may exist inside the channel is not considered. It is necessary to consider that the heavily doped source and drain electrodes can provide sufficient mobile charge carriers to inject into the channel to form a current. Since the above parameter definitions take into account that the SG SOI has a circular cross-section and are modeled in cylindrical coordinates, the mathematical expressions for the electric field distribution, potential energy distribution, and particle wave function along the interface direction will exhibit axisymmetry centered on the z-axis. Furthermore, the quantum tunneling current between the source and drain electrodes needs to be neglected.

[0104] At this point, the core compact model of the long-channel N-type SG SOI metal-oxide-semiconductor field-effect transistor 1 device has been completed.

[0105] Example 2

[0106] like Figures 1-4 As shown, this embodiment provides an SG SOI modeling method, which includes:

[0107] Step S11: Provide a short-channel N-type SGSOI metal-oxide-semiconductor field-effect transistor (MOSFET) device, list the channel surface potential and carrier subband energy level equations for the semiconductor device, scan several parameters in the channel surface potential and carrier subband energy level equations, and establish the relationship between the channel surface potential, carrier subband energy levels, and each parameter. The drain-induced barrier lowing (DIBL) effect mainly manifests as its influence on the potential energy distribution along the device channel in the subthreshold range.

[0108] Specifically, a short-channel N-type SGSOI metal-oxide-semiconductor field-effect transistor (MOSFET) is provided. Its device structure is essentially the same as the long-channel N-type SGSOI MOSFET of Embodiment 1, differing only in the channel length. The channel surface potential of the N-type SGSOI semiconductor device described in Embodiment 1 can be approximately calculated using an associated assumed parameter. Similarly, by introducing the channel direction component z to describe the aforementioned associated assumed parameter, the electrostatic potential distribution along the carrier conduction direction within the channel cross-section of the N-type SGSOI semiconductor device is calculated, and this associated assumed parameter ΔU is established. G The relationship between (z) and each parameter.

[0109] Step S12: Use the two-dimensional Laplace equation to scan the correlation hypothesis parameter ΔU that considers the DIBL effect.G The relationship with each parameter.

[0110] Specifically, in this embodiment, the DIBL effect is considered in the short-channel N-type SGSOI metal-oxide-semiconductor field-effect transistor (MOSFET) device model. The potential distribution along the carrier conduction direction changes due to the electric field from the drain. Therefore, the position of the barrier apex and the energy level at the barrier apex also change, resulting in a significant change in the ballistic / quasi-ballistic transport current. Thus, reproducing this potential distribution is essential to accurately represent the ballistic / quasi-ballistic transport current. To calculate the electrostatic potential distribution w(r, z) in the channel of the short-channel N-type SGSOI MOSFET device, it is necessary to solve its Poisson equation. Under subthreshold operating conditions, due to V GS Since the channel is sufficiently small and short, it can be assumed that the carrier charge density in the channel is zero. Therefore, the three-dimensional Poisson equation transforms into a two-dimensional Laplace equation, yielding the following relationship for the electrostatic potential distribution within the channel of a short-channel N-type SGSOI metal-oxide-semiconductor field-effect transistor:

[0111]

[0112]

[0113]

[0114]

[0115] Where A and B represent the calculation coefficients related to the gate-source voltage and drain-source voltage, respectively, and V bi ε is the built-in potential between the source / drain and the channel, γ is a scaling factor dependent on the device structure, and ε is the voltage between the source and the drain channel. CH C is the dielectric constant of the channel. OX L represents the gate oxide capacitance per unit length. G Defined as the channel length of the SGSOI semiconductor device. As mentioned above, z defines the conduction direction axis of the charge carriers. Simulation software can obtain the corresponding equations and parameters to simulate the corresponding relationships. The simulation software includes, but is not limited to, Silvaco TCAD and Sentaurus, which will not be elaborated here.

[0116] Step S13: Utilize the above-mentioned correlation hypothesis parameter ΔU G (z) Describe the electrostatic potential distribution along the z-direction in the channel of a short-channel N-type SG SOI metal-oxide-semiconductor field-effect transistor 1 device, and establish the relationship between the channel surface potential, carrier subband energy level and various parameters at this time.

[0117] Specifically, the surface potential of the channel distributed along the channel direction is calculated according to the following relationship:

[0118]

[0119]

[0120] AU G (z)=A exp(γ·z)+B exp(-γ·z).

[0121] Specifically, the energy levels of the carrier subbands distributed along the channel direction satisfy the following relationship:

[0122]

[0123] Among them, all charge carriers contributing to the ballistic / quasi-ballistic current can only exist at the maximum value E at the top of the barrier within the channel. MAX The above energy range, z MAX Let be the location of the potential barrier vertex along the channel direction. Using analytical calculations of the electrostatic potential distribution, the location of the potential barrier vertex along the channel direction can be calculated by taking its first derivative, satisfying the following relationship:

[0124]

[0125]

[0126] At this point, the core compact model of the short-channel N-type SG SOI metal-oxide-semiconductor field-effect transistor 1 device has been completed.

[0127] Example 3

[0128] like Figure 6 As shown, this embodiment provides an SG SOI semiconductor modeling method, which includes:

[0129] Step S11: Provide an SG SOI semiconductor device, list the analytical equation for the dynamic charge density of carriers in the channel of the SG SOI semiconductor device, scan several parameters in the analytical equation for the dynamic charge density of carriers in the channel, and establish the relationship between the dynamic charge density of carriers in the channel and each parameter.

[0130] Specifically, step S111: In this embodiment, the SG SOI semiconductor device is a short-channel SG SOI metal-oxide-semiconductor field-effect transistor 1, whose structure is the same as that of the long-channel SG SOI metal-oxide-semiconductor field-effect transistor in Embodiment 1. Constructing a capacitance model is essential for calculating the transient and AC characteristics of the SG SOI semiconductor device. When considering the MOSFET capacitance, an equivalent capacitance circuit for the MOSFET needs to be established, and the current can be composed of charge carriers flowing through the source and drain. The transient current flowing through the MOSFET can be obtained by calculating the change in charge accumulated in each capacitor over time. The transient current flowing between the gate and source can be determined by the time derivative of the accumulated charge between the gate and source. Since the current flowing through the source can be obtained as a function of the static current between the source and drain and the transient current between the gate and source, the current I flowing through the source is... S The following relationship must be satisfied:

[0131]

[0132]

[0133] Among them, I SUP The source-drain current under static conditions can be simplified to a steady-state source between the source and drain, Q. GS Q is the time-dependent amount of carrier charge accumulated between the gate and source. eline The one-dimensional carrier charge density distribution in the channel of the SG SOI semiconductor device with time correlation in the source-drain direction is described in detail in Example 1.

[0134] Specifically, in step S112: Based on the above description of the source transient current, it can be deduced that the current flowing through the drain terminal can be represented by a function of the static current between the source and drain and the transient current between the gate and drain. The current I flowing through the drain terminal... D The following relationship must be satisfied:

[0135]

[0136]

[0137] Among them, Q GD The current-dependent amount of charge stored between the gate and source terminals is represented by the time-dependent nature of the current, which can be expressed by the time-dependent change in the voltage applied to each terminal.

[0138] Specifically, in step S113: by solving for the time derivative of the bias voltage component applied to each terminal, the following can be derived: Figure 6 The source / drain capacitance components of an intermediate-priced circuit, and the currents flowing through the source and drain, satisfy the following set of relationships:

[0139]

[0140] V G V S V D These represent the voltages applied to the gate, source, and drain, respectively.

[0141] Step S12: Calculate the relationship between the capacitance and various parameters using the source and drain current equations.

[0142] Specifically, using the transient current equations flowing through the source and drain in the SG SOI semiconductor device described in S111-S113 above, and combining the relationship between charge and voltage (C = Q / V), the gate-source and gate-drain capacitances can be derived. Therefore, using the one-dimensional carrier charge density model in the channel of the SG SOI metal-oxide-semiconductor field-effect transistor in Example 1, a capacitance calculation model between the gate and source / drain can be derived and constructed, satisfying the following relationship:

[0143]

[0144]

[0145] It should be noted that, as described in Example 1, Q eline It can be expressed as about V G The equation. From this equation, Q... eline The change relative to the time component can be equivalent to Q. eline Compared to V G With V G The product of changes relative to time. C GS，G C represents the equivalent gate-source capacitance based on the AC analytical representation of the device. GD，G L represents the equivalent gate-drain capacitance based on the AC analytical representation of the device. G This indicates the channel length of the SGSOI semiconductor device.

[0146] Step S13: Calculate the relationship between the quantum capacitance in the channel and various parameters using the gate-source / drain capacitance calculation model.

[0147] Specifically, as described in S12, the gate-source / drain capacitance can be defined as the effective gate capacitance within the channel. Therefore, the SG SOI metal-oxide-semiconductor field-effect transistor 1 has a barrier vertex z in the channel direction. MAX The effective capacitance per unit length at a given point can be calculated and expressed in terms of the gate oxide capacitance and quantum capacitance, satisfying the following relationship:

[0148]

[0149]

[0150] Among them, C OX The capacitance per unit length of the gate oxide film of the short-channel SG SOI metal-oxide-semiconductor field-effect transistor 1 is the same as that described in Example 1, C q The quantum capacitance within the channel of a short-channel SGSOI metal-oxide-semiconductor field-effect transistor (MOSFET) is represented by C. eff，G Represents the potential barrier vertex z MAX The effective capacitance at that location.

[0151] At this point, the core compact model of the long-channel SG SOI metal-oxide-semiconductor field-effect transistor 1 device has been completed.

[0152] Example 4

[0153] like Figure 2 As shown, this embodiment provides an SG SOI semiconductor device modeling method, which includes:

[0154] Step S11: Provide a long-channel P-type SGSOI metal-oxide-semiconductor field-effect transistor (MOSFET) device. List the channel surface potential and carrier subband energy level equations for the semiconductor device. Scan several parameters in the channel surface potential and carrier subband energy level equations to establish the relationship between the channel surface potential, carrier subband energy levels, and each parameter. Assume that the electrostatic potential distribution within the channel cross-section of the semiconductor device can be approximately calculated by a quadratic function of an associated assumed parameter. This unknown parameter is obtained by calculating the potential difference between the channel and the gate oxide insulation interface and the channel center. Establish this associated assumed parameter ΔU. G The relationship with each parameter.

[0155] Specifically, step S111: In this embodiment, a long-channel SG SOI metal-oxide-semiconductor field-effect transistor is provided, such as... Figure 2 The diagram shows a schematic of a short-channel SG SOI metal-oxide-semiconductor field-effect transistor (P-type structure) in the prior art. The long-channel P-type SG SOI metal-oxide-semiconductor field-effect transistor 1 includes a true silicon semiconductor channel 11, a silicon dioxide insulating oxide layer 12 forming on the upper and lower layers of the true silicon semiconductor channel 11, a gate structure G formed on the silicon dioxide insulating oxide layer 12, P-type heavily doped silicon channels 23 formed on the left and right sides of the true silicon semiconductor channel 11, and a source structure S and a drain structure D formed on both sides of the two P-type heavily doped silicon channels 13. The corresponding associated assumption parameter ΔU is obtained based on the physical parameters of the long-channel N-type SG SOI metal-oxide-semiconductor field-effect transistor 1. G Numerical calculation of the system of equations.

[0156] Specifically, step 112: using the band structure of the long-channel P-type SG SOI metal-oxide-semiconductor field-effect transistor 1, the effective mass of carriers in the channel is approximated.

[0157] Based on the mapping relationship between the valence band structure and the effective mass extraction of holes, the various dispersion relationships can be approximated using the parabolic equation.

[0158] It should be noted that the valence band structure of the P-type SG SOI metal-oxide-semiconductor field-effect transistor 1 is very complex, and the effective carrier mass approximation based on the analytical model of the N-type SG SOI metal-oxide-semiconductor field-effect transistor 1 in Example 1 cannot be applied. Related reports demonstrate that, from the perspective of current characteristic calculation, leakage current can be reproduced by adjusting the effective carrier mass.

[0159] Specifically, step S113: Use simulation software to simulate and extract the effective mass of the charge carriers, and compare it with the approximately calculated effective mass to verify the applicability of the effective mass approximation. The simulation software obtains the corresponding equations and parameters, and can simulate the accurate effective mass of the charge carriers. The simulation software includes, but is not limited to, Silvaco TCAD and Sentaurus, which will not be described in detail here. As shown in Table 1, m x m y m z These represent the effective mass of the charge carrier along the minor and major axes of the ellipsoidal isoenergetic surface near the bottom of the valence band.

[0160] Table 1 Effective hole mass extracted from band dispersion relation

[0161] <![CDATA[m x / m0]]> <![CDATA[m y / m0]]> <![CDATA[m z / m0]]> Effective mass ratio 0.93 0.37 1.14

[0162] Step S12: Using Example 1 for ΔU G The analytical solution method of (z) is used to calculate the channel surface potential and carrier subband energy levels of the long-channel SG SOI metal oxide semiconductor field-effect transistor 1 within the applicable range of effective mass approximation, and to establish the relationship between the channel surface potential, carrier subband energy levels and various parameters.

[0163] In this embodiment, the analytical model of the long-channel N-type SGSOI metal-oxide-semiconductor field-effect transistor 1 is applied verbatim to the long-channel P-type SGSOI metal-oxide-semiconductor field-effect transistor 1 to calculate its static electrical characteristics. During the calculation of the voltage and current characteristics of the long-channel P-type SGSOI metal-oxide-semiconductor field-effect transistor 1, the quantum confinement energy level of the charge carriers in the valence band and the parameter relationship satisfy the following equation:

[0164]

[0165]

[0166]

[0167] in, This represents the unperturbed conjugate carrier wavefunction within the confined potential well. This represents the unperturbed carrier wavefunction within the confined potential well. Let m be the perturbation constant of each subband energy level of the charge carrier. r *P =2(m t -1 +m l -1 ) represents the effective mass of the charge carrier in the radial direction within the confinement section of the SG SOI, m t -1 m l -1 These represent the effective mass of the charge carrier along the minor and major axes of the ellipsoidal isoenergetic surface near the bottom of the conduction band, respectively. This represents the energy level of the valence charge carrier subband. The q0 represents the carrier subband energy level with quantum confinement effect of the valence band, and the superscript q0 represents the carrier energy level without perturbation.

[0168] Step S13: Based on the carrier conduction method of ballistic transport, derive the channel current expression and charge expression of the long-channel P-type SG SOI metal-oxide-semiconductor field-effect transistor 1, and obtain the model of the semiconductor device.

[0169] At this point, the core compact model of the long-channel SG SOI metal-oxide-semiconductor field-effect transistor 1 device has been completed.

[0170] Example 5

[0171] like Figure 7 As shown, this embodiment provides an implementation method for applying the SG SOI semiconductor model described above to large-scale integrated circuit design based on CMOS technology. The implementation method includes:

[0172] Step S11: Calculate the equations using the SG SOI peninsula device model constructed in Examples 1 to 4, and write a design script based on the Verilog-A specification, thereby allowing device-level modeling of systems that process continuous-time signals.

[0173] This approach describes the complex physical behavior within a device using a series of analytically computable equations with high precision. It develops a syntax that conforms to Verilog-A, describing the potential energy distribution, conduction carrier energy level states, and even the AC ballistic transport current characteristics within the device. Verilog-A's source code is shorter and simpler than C, saving approximately 90% of the source code.

[0174] Step S12: Use Verilog-A to express the devices in the continuous-time signal processing system in a script that conforms to the HSPICE programming language, and realize the netlist script for embedded circuit simulation design based on HSPICE.

[0175] Step S13: HSPICE can be applied to almost all simulation software used in the semiconductor chip circuit design process. It can meet the simulation application of the SG SOI peninsula device model constructed in Examples 1 to 4 in the above circuit design, and is also compatible with different circuit simulators.

[0176] It is important to note that to meet the design requirements of the VLSI manufacturing industry, the functionality and performance of circuits must be verified through computational simulation. Generally, semiconductor foundries provide analytical compact models of devices to the circuit design team to facilitate the design process. Therefore, the industrial standardization of device compact models is a crucial resource that semiconductor companies within the integrated circuit industry vigorously develop and maintain. Furthermore, the complex behavior of source / drain charges, capacitance, and leakage current within devices can be approximated with high precision using analytical equations from compact models. Optimizing the computational efficiency and accuracy of these models is critical for computational circuit simulation; therefore, adjustable model parameters are inevitably included in the model equations.

[0177] This concludes the introduction to the implementation method of applying the SG SOI semiconductor model to large-scale integrated circuit design based on CMOS technology.

[0178] In summary, this invention provides a modeling method for SG SOI semiconductor devices, comprising: providing an SG SOI semiconductor device; listing analytical expressions for unknown parameters expressed by the difference between the center potential and the surface potential within the channel of the SG SOI semiconductor device; scanning the analytical descriptions of the unknown parameters under different channel positions, different bias voltages, and different device operating ranges, and establishing analytical solutions for the channel surface potential, carrier subband energy levels, and ; deriving channel current expressions and charge expressions based on the channel center and surface potentials or carrier subband energy levels characterized by the Landauer current formula and the carrier transport mode of the semiconductor device, thereby obtaining a model of the SG SOI semiconductor device. This semiconductor device modeling method uses assumed unknown parameters, fundamentally solving the difficulties in developing intensive physical models of semiconductor devices. Compared to traditional physical models, it has advantages such as faster computation speed and higher accuracy, while also possessing a certain physical process scaling capability, providing support for chip design and direction for semiconductor process development. Therefore, this invention effectively overcomes various shortcomings of existing technologies and has high industrial applicability. Meanwhile, using SPICE (Simulation Program with Integrated Circuit Emphasis) tools to achieve high-precision circuit simulation is a standard practice widely adopted in the semiconductor industry. For this purpose, foundries need to provide certified MOS device models with excellent simulation and analysis algorithms to perform circuit simulations and evaluate output characteristics. Verilog-A provides an analog signal hardware description language (HDL) that can be used in conjunction with SPICE, facilitating circuit designers and model developers to use their integrated design environments and easily designing and verifying complex analog / mixed-signal circuits and models. To embed the analysis model into the circuit simulator, Verilog-A, as the standard notation language for modeling analog circuits, is used to describe the analytical expressions, which are then read into the circuit simulator. The circuit simulator script can be written using traditional syntax, and the MOSFET-related parts can be replaced with analytical expressions for SG SOI MOSFETs written in Verilog-A.

[0179] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An SG SOI semiconductor device modeling method, characterized in that, Includes the following steps: A mathematical model of an SG SOI semiconductor device is constructed using a script; Import the script into the circuit simulator; By obtaining the semiconductor device parameter information from the mathematical model within the script, the semiconductor device model of the SG SOI semiconductor device is obtained, thus realizing the modeling of the semiconductor device. The script is a Verilog-A file; The semiconductor device model of the SG SOI semiconductor device is obtained by acquiring the semiconductor device parameter information from the mathematical model within the script, including the following steps: By querying the parameter information and mathematical model contained in the semiconductor device model within the script, the voltage and current values ​​of the ballistic / quasi-ballistic current corresponding to the channel surface potential and the carrier subband energy level are extracted. The voltage and current values ​​are then imported into the device behavior description module in the circuit simulator. The circuit netlist using the SG SOI semiconductor device model is generated and saved according to the circuit design software. Based on the derivation of the various input and output nodes of the device in the netlist and the mapping relationship between the nodes, a semiconductor device model containing a description of the relationship between the bias voltage of each endpoint and the ballistic / quasi-ballistic current in the device channel is generated. The semiconductor device model contains the following parameter information: Channel surface potential w of SG SOI semiconductor device S Subband energy levels of charge carriers in the conduction band Ballistic / quasi-ballistic current I DS Channel radius R, channel length L G Gate-source voltage V GS Drain-source voltage V DS Effective oxide film thickness T OX The built-in source-channel junction voltage V associated with the channel radius R bi Valley degeneracy of band structure 2. The SG SOI semiconductor device modeling method according to claim 1, characterized in that, The mathematical model of the SGSOI semiconductor device is the same as that of a long-channel N-type SGSOI metal-oxide-semiconductor field-effect transistor: Where, k B T Let represent Boltzmann's constant, absolute temperature, and Planck's constant, respectively; r represents the radius component of the circular cross-section perpendicular to the carrier conduction direction within the channel; and Q... eline Let Q be the charge density of the electromagnetic field based on Gauss's law. qline Here, m is the charge density calculated based on quantum statistical theory, m0 is the electron mass in vacuum, and m C * n is the effective mass of charge carriers in the transmission direction. v The valley index of the band structure. This indicates the valley degeneracy of a specific band structure. This represents the subband energy level of charge carriers in the conduction band, with the superscript q0 indicating the non-perturbation term charge carrier energy level. Indicates the first The nth order of the first type of Bessel function r A zero-point value, This represents the effective mass of the charge carriers in the radial direction (r direction) within the confinement section of the SG SOI channel. and n r V represents the quantum number of the angular component and the quantum number of the radius component, respectively. DS The source-drain voltage is given by E. F,S and E F,D The difference between them determines, E F,S and E F,D R represents the Fermi level at the source and drain ends, respectively. ref V is the backscattering constant of charge carriers at the potential energy barrier. t Let w be the thermal voltage, w be the electrostatic potential distribution function within the channel, R be the radius of the circular cross-section of the SG SOI channel, q be the unit charge, and ΔU be the voltage. G The parameters are assumed to correlate the channel surface potential with the potential difference between the channel surface and the center. w represents the perturbation constant of each subband energy level of the charge carrier. S This represents the channel surface potential of the SG SOI semiconductor device.

3. The SG SOI semiconductor device modeling method according to claim 1, characterized in that, The mathematical model of the SGSOI semiconductor device is the same as that of a long-channel N-type SGSOI metal-oxide-semiconductor field-effect transistor: In the subthreshold range, i.e., when the gate-source voltage is less than the threshold voltage at which the semiconductor device turns on: In the deep inversion layer region, i.e., when the gate-source voltage is greater than the threshold voltage for the semiconductor device to turn on: Where, k B T Here, represents Boltzmann's constant, absolute temperature, and Planck's constant, respectively; r represents the radius component of the circular cross-section perpendicular to the carrier conduction direction within the channel; m0 is the electron mass in vacuum; and m... C * n is the effective mass of charge carriers in the transmission direction. v The valley index of the band structure. This indicates the valley degeneracy of a specific band structure. This represents the subband energy level of charge carriers in the conduction band, with the superscript q0 indicating the non-perturbation term charge carrier energy level. and n r V represents the quantum number of the angular component and the quantum number of the radius component, respectively. DS R is the source-drain voltage. ref V is the backscattering constant of charge carriers at the potential energy barrier. t Let w be the thermal voltage, w be the electrostatic potential distribution function within the channel, R be the radius of the circular cross-section of the SG SOI channel, q be the unit charge, and ΔU be the voltage. G The parameters are assumed to correlate the channel surface potential with the potential difference between the channel surface and the center. w represents the perturbation constant of each subband energy level of the charge carrier. S This represents the channel surface potential of the SG SOI semiconductor device.

4. The SG SOI semiconductor device modeling method according to claim 2 or 3, characterized in that, The long channel refers to a true semiconductor channel of an SG SOI semiconductor device with a true semiconductor channel length greater than 20 nm.

5. The SG SOI semiconductor device modeling method according to claim 1, characterized in that, The mathematical model of the SG SOI semiconductor device is the mathematical model of a short-channel N-type SG SOI metal-oxide-semiconductor field-effect transistor: The carrier subband energy levels distributed along the channel direction are as follows: Among them, all charge carriers contributing to the ballistic / quasi-ballistic current can only exist at the maximum value E at the top of the barrier within the channel. MAX Within the above energy range, z MAX The location of the potential barrier vertex in the channel direction: in, The effective mass of the charge carrier in the radius r direction within the confined cross section of the SG SOI channel. Indicates the first The nth order of the first type of Bessel function r A zero-point value, m r *P m represents the effective mass of the P-type charge carrier in the radial direction (r) within the SGSOI confinement section. t -1 m l -1 Let U represent the effective mass of the charge carrier along the minor and major axes of the ellipsoidal isoenergetic surface near the bottom of the conduction band, respectively, where z is the conduction direction axis of the charge carrier, and ΔU G The parameter w is the hypothetical relationship between the channel surface potential and the center potential difference. S Let γ be the channel surface potential of the SG SOI semiconductor device, r be the radius component of the circular cross section perpendicular to the carrier conduction direction in the channel, A and B be the correlation calculation coefficients for the gate-source voltage and drain-source voltage, respectively, and γ be a scaling factor dependent on the device structure.

6. The SG SOI semiconductor device modeling method according to claim 5, characterized in that, The short channel is a true semiconductor channel of an SG SOI semiconductor device with a channel length of less than 20 nm and greater than 10 nm.

7. The SG SOI semiconductor device modeling method according to claim 4, characterized in that: The mathematical model of the SG SOI semiconductor device is a mathematical model for the transient capacitance applied to the AC analysis of the device: The capacitance model between the gate and source / drain is as follows: C GS,G For the gate-source equivalent circuit capacitance based on device AC analysis, C GD,G Q is the equivalent circuit capacitance between the gate and drain based on the AC analytical solution of the device. eline V represents the one-dimensional carrier charge density distribution within the channel of an SG SOI semiconductor device along the source-drain direction, which is time-correlated. G L is the voltage applied to the gate. G denoted as , where z is the channel length of the SG SOI semiconductor device, and z is the conduction direction axis of the charge carriers.

8. The SG SOI semiconductor device modeling method according to claim 1, characterized in that: The mathematical model of the SG SOI semiconductor device is the same as that of the P-type SG SOI metal-oxide-semiconductor field-effect transistor: The effective carrier mass m is obtained using general-purpose device simulation software. z Substituting the effective mass m of the channel carriers into the mathematical model of the N-type SGSOI metal-oxide-semiconductor field-effect transistor... C * P-type SG SOI metal-oxide-semiconductor field-effect transistors were obtained. in, This represents the unperturbed conjugate carrier wavefunction within the confined potential well. This represents the unperturbed carrier wavefunction within the confined potential well. Let m be the perturbation constant of each subband energy level of the charge carrier. r *P =2(m t -1 +m l -1 ) -1 m is the effective mass of the charge carrier in the radial direction within the confined cross section of the SG SOI channel. t -1 m l -1 These represent the effective mass of the charge carrier along the minor and major axes of the ellipsoidal isoenergetic surface near the bottom of the conduction band, respectively. This represents the energy level of the valence charge carrier subband. The carrier subband energy level represents the quantum confinement effect of the valence band.

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