Port position determination method and apparatus, electronic device, and readable storage medium

Abstract

The application provides a port position determination method and device, electronic equipment and a readable storage medium. The method comprises: obtaining module information of at least two adjacent target modules; wherein the module information comprises an execution device in the module and a port of the module; obtaining layout limitation conditions of the at least two target modules; wherein the layout limitation conditions are used to limit the execution device of each target module in a first limitation area of the corresponding module and to limit the ports of each two adjacent target modules in a second limitation area of module connection; and determining the port position of each two adjacent target modules according to the module information and the layout limitation conditions of the at least two target modules, so that the port position obtained by planning is the best port position, thereby greatly improving the port position determination efficiency, reducing the manpower investment and workload, and improving the determination accuracy of the port position.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and more specifically, to a method, apparatus, electronic device, and computer-readable storage medium for determining port locations. Background Technology

[0002] In high-performance chip design, because the chips are too large, electronic design automation (EDA) tools cannot perform overall placement and routing of the chips. The usual solution is to divide the chips into multiple small hard modules according to their functions.

[0003] Based on the chip being divided into multiple small hard modules, the position of the input and output ports of each module on the module boundary directly affects the signal path of that port and the placement of components inside the module, thereby affecting the chip's efficiency and circuit resources.

[0004] Current chip design typically involves determining the location of module input and output ports based on a general assumption of experience. Then, after placement and routing are completed, the port positions are adjusted based on the timing check results of the entire chip. This approach makes port position determination inefficient, and adjusting the ports after the entire chip design is completed results in a huge workload. Summary of the Invention

[0005] The purpose of this application is to provide a port location determination method, apparatus, electronic device, and readable storage medium to solve the problems of low efficiency and large workload caused by the current chip design method of assuming port locations based on the designer's experience and adjusting the port locations based on the timing check results of the whole chip after the layout and routing are completed.

[0006] In a first aspect, the present invention provides a port location determination method, the method comprising: acquiring module information of at least two adjacent target modules; wherein the module information includes execution devices in the module and ports of the module; acquiring layout constraints of at least two target modules; wherein the layout constraints are used to restrict the execution devices of each target module to be within a first restricted area of ​​the corresponding module and to restrict the ports of each pair of adjacent target modules to be within a second restricted area of ​​the module connection; and determining the port location of each pair of adjacent target modules based on the module information of the at least two target modules and the layout constraints.

[0007] The port location determination method described above first obtains the module information of at least two adjacent target modules, then obtains the layout constraints of at least two target modules, and finally determines the port location of each pair of adjacent modules based on the module information and layout constraints. Since the ports of each pair of adjacent modules are restricted to the second constraint area of ​​the module connection by the layout constraints, when the positions of the actuators within the two target modules change, although the port locations of the target modules also change with the positions of the actuators, the ports of the target modules are always restricted to the second constraint area. Thus, based on the automated determination of port locations, the planned port locations are the optimal port locations, thereby greatly improving the efficiency of port location determination, reducing manpower input and workload, and also improving the accuracy of port location determination.

[0008] In an optional implementation of the first aspect, determining the port position of each pair of adjacent target modules based on the module information and layout constraints of the at least two target modules includes: restricting the execution device of each target module to a first restricted area of ​​the corresponding module according to the layout constraints; restricting the ports of each pair of adjacent target modules to a second restricted area of ​​module connection according to the layout constraints; and performing layout planning on the at least two target modules to obtain the port position of each pair of adjacent target modules after the layout planning is completed.

[0009] In an optional implementation of the first aspect, restricting the ports of every two adjacent target modules within a second restricted area of ​​the module connection according to layout constraints includes: obtaining at least one pre-configured set of anchoring buffers; wherein each set of anchoring buffers includes multiple anchoring buffers, different adjacent target modules correspond to different sets of anchoring buffers, and each anchoring buffer in the same set corresponds to one port of the corresponding two adjacent target modules; and restricting each set of anchoring buffers within the second restricted area of ​​the connection between the corresponding two adjacent target modules according to layout constraints.

[0010] In an alternative implementation of the first aspect, each set of anchoring buffers corresponds to all input and output ports of one of the two adjacent target modules.

[0011] In an alternative implementation of the first aspect, each set of anchoring buffers corresponds to all input ports of one of the two adjacent target modules and all input ports of the other of the two adjacent target modules.

[0012] In an optional implementation of the first aspect, layout planning is performed on at least two target modules to obtain the port positions of each pair of adjacent target modules after layout planning is completed. This includes: layout planning the positions of each group of anchor buffers to obtain the position information of each anchor buffer in each group of anchor buffers after planning is completed; and determining the port positions of the corresponding two adjacent target modules based on the position information of each anchor buffer in each group of anchor buffers. This implementation pre-embeds a corresponding anchor buffer for each port and restricts the anchor buffers to a second restricted area. After optimization, the position of the corresponding port can be determined by the position information of the anchor buffers, thereby automatically determining the port position, improving the efficiency of port position determination in chip design, and greatly reducing the workload of designers.

[0013] In an alternative embodiment of the first aspect, each anchoring buffer is provided with an anti-optimization attribute to prevent optimization. This embodiment prevents optimization of the configured anchoring buffer by setting an anti-optimization attribute when configuring the anchoring buffer, thereby avoiding port position loss due to optimization.

[0014] In an optional implementation of the first aspect, restricting the ports of every two adjacent target modules within a second restricted area of ​​module connection according to layout constraints includes: obtaining the port identifier of each port of every two adjacent target modules; wherein different ports have different identifiers; and restricting all ports of every two adjacent target modules within the second restricted area of ​​corresponding module connection according to the port identifier of each port.

[0015] In an optional implementation of the first aspect, layout planning is performed on at least two target modules to obtain the port positions of each pair of adjacent target modules after layout planning. This includes: performing layout planning on the position of each port identifier in each pair of adjacent target modules to obtain the position information of each port identifier after planning; and determining the position of the corresponding port based on the position information of each port identifier. This implementation automatically determines the port position by setting a corresponding port identifier for each port and restricting the port identifier to a second restricted area. After optimization, the position information of the port identifier is the position of the corresponding port, thereby improving the efficiency of port position determination in chip design and greatly reducing the workload of designers.

[0016] In an optional implementation of the first aspect, obtaining module information of at least two adjacent target modules includes: obtaining multiple logical modules obtained from the top-level layout planning; wherein each logical module includes the logical module location, size, and execution devices and ports in the logical module; and obtaining at least two adjacent logical modules as target modules based on the module locations of the multiple logical modules.

[0017] In an optional embodiment of the first aspect, after determining the port positions of each pair of adjacent target modules based on module information and layout constraints of at least two target modules, the method further includes: calculating the port delay at each port position; and determining the timing constraints of the corresponding port based on the delay at each port position. This embodiment calculates the port delay at each port position based on the determined port positions of each pair of adjacent target modules; and determines the timing constraints of the corresponding port based on the delay at each port position. Because the determined port positions are relatively accurate, relatively accurate port timing convergence constraints are generated.

[0018] In a second aspect, the present invention provides a port location determination device, the device comprising an acquisition module and a determination module; the acquisition module is configured to acquire module information of at least two adjacent target modules; wherein the module information includes actuators in the module and ports of the module; and to acquire layout constraints of the at least two target modules; wherein the layout constraints are configured to restrict the actuators of each target module to a first restricted area of ​​the corresponding module and restrict the ports of each pair of adjacent target modules to a second restricted area of ​​module connection; the determination module is configured to determine the port location of each pair of adjacent target modules based on the module information and layout constraints of the at least two target modules.

[0019] The port position determination device designed above first obtains the module information of at least two adjacent target modules, then obtains the layout constraints of at least two target modules, and finally determines the port position of each pair of adjacent modules based on the module information and layout constraints. Since the ports of each pair of adjacent modules are restricted to the second restriction area of ​​the module connection by the layout constraints, when the position planning of the actuators in the two target modules changes, although the port position of the target module also changes with the position of the actuators, the port of the target module is always restricted to the second restriction area. Thus, based on the automated determination of port position, the planned port position is the optimal port position, thereby greatly improving the efficiency of port position determination, reducing manpower input and workload, and also improving the accuracy of port position determination.

[0020] In an optional embodiment of the second aspect, the determining module is specifically configured to, according to layout constraints, restrict the actuator of each target module to a first restricted area of ​​the corresponding module; and, according to layout constraints, restrict the ports of every two adjacent target modules to a second restricted area of ​​module connection.

[0021] Within the domain; perform layout planning for at least two target modules to obtain the port positions of every two adjacent target modules after the layout planning is completed.

[0022] In an optional implementation of the second aspect, the determining module is further specifically configured to acquire at least one pre-configured set of anchoring buffers; wherein each set of anchoring buffers includes multiple anchoring buffers, different adjacent target modules correspond to different sets of anchoring buffers, and each anchoring buffer in the same set is associated with...

[0023] One port corresponds to each of two adjacent target modules; according to the layout constraints, each set of anchor buffers is restricted to the second restricted area where the two adjacent target modules are connected.

[0024] In an optional implementation of the second aspect, the determining module is further specifically used to plan the layout of the positions of each group of anchoring buffers, obtain the position information of each anchoring buffer in each group of anchoring buffers after the planning is completed, and determine the port positions of two adjacent target modules based on the position information of each anchoring buffer in each group of anchoring buffers.

[0025] 5 In an optional embodiment of the second aspect, the determining module is further specifically configured to obtain the port identifier of each port of each of two adjacent target modules; wherein different ports have different identifiers; and based on the port identifier of each port, restrict all ports of each of two adjacent target modules to a second restriction area connected to the corresponding modules.

[0026] In an optional implementation of the second aspect, the determining module is further specifically configured to perform layout planning on the position of each port identifier in every two adjacent zero target modules, thereby obtaining the planned position of each port.

[0027] The location information of the port identifier; the location of the corresponding port is determined based on the location information of each port identifier.

[0028] In an optional implementation of the second aspect, the acquisition module is specifically used to acquire multiple logical modules obtained from the top-level layout planning; wherein each logical module includes the logical module location, size, and execution devices and ports in the logical module; and at least two adjacent logical modules are acquired as target modules based on the module locations of the multiple logical modules.

[0029] In an alternative embodiment of the second aspect, the device further includes a calculation module for calculating the port delay at each 5-port location; the determination module is further configured to determine the timing constraints of the corresponding port based on the delay at each port location.

[0030] Thirdly, this application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the method described in the first aspect or any optional implementation thereof.

[0031] Fourthly, this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the method described in the first aspect or any optional implementation thereof.

[0032] Fifthly, this application provides a computer program product that, when run on a computer, causes the computer to perform the method described in the first aspect or any optional implementation of the first aspect.

[0033] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0034] 0 To more clearly illustrate the technical solutions of the embodiments of this application, the embodiments of this application will be described below.

[0035] The accompanying drawings used in this application are briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 A first flowchart of the port location determination method provided in the embodiments of this application;

[0037] Figure 2 This is a structural example diagram of multiple logic modules of a chip provided in an embodiment of this application;

[0038] Figure 3 This is a structural example diagram of an adjacent target module provided in an embodiment of this application;

[0039] Figure 4 This is a structural example diagram of another adjacent target module provided in an embodiment of this application;

[0040] Figure 5 A second flowchart of the port location determination method provided in the embodiments of this application;

[0041] Figure 6 This is a schematic diagram illustrating the position determination of the anchoring buffer provided in an embodiment of this application;

[0042] Figure 7 This is a schematic diagram of the port location determination device provided in the embodiments of this application;

[0043] Figure 8This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0044] Icons: 700 - Acquisition module; 710 - Determining module; 720 - Calculation module; 8 - Electronic device; 801 - Processor; 802 - Memory; 803 - Communication bus. Detailed Implementation

[0045] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0047] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0048] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0049] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0050] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0051] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0052] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0053] In high-performance chip design, due to the large size of the chip, Electronic Design Automation (EDA) tools cannot perform overall placement and routing. A common solution is to divide the chip into multiple small hardware modules based on its function. These EDA tools refer to three categories: chip design aids, programmable chip design aids, and system design aids. They can automatically place and route chips, perform circuit design simulations, etc. These multiple small hardware modules can be understood as multiple small functional modules, each performing a corresponding function.

[0054] Based on the chip being divided into multiple small hard modules, the position of the input and output ports of each module on the module boundary directly affects the signal path of that port and the placement of components inside the module, thereby affecting the chip's efficiency and circuit resources.

[0055] The inventors have discovered that current chip design typically determines the positions of module input and output ports based on an assumed general order from experience. Then, after placement and routing are completed, the port positions are adjusted based on the timing check results of the entire chip. This approach makes port position determination inefficient, and adjusting the ports after the entire chip design is completed results in a huge workload.

[0056] To address the aforementioned problems, the inventors have designed a port location determination method, apparatus, electronic device, and readable storage medium. By merging two adjacent target modules into one module, and then confining the execution devices of each target module within their respective module regions (first restricted regions), and confining the ports of the two adjacent target modules within a second restricted region connecting the modules, the EDA tools automatically perform layout planning for the ports of the two adjacent target modules based on the aforementioned constraints, thereby determining the port locations of the two adjacent target modules. This effectively improves the efficiency of determining module port locations and greatly reduces the workload of port location planning for chip modules.

[0057] Based on the above ideas, this application provides a method for determining port location. This method can be applied to computing devices, including but not limited to computers, servers, etc. Figure 1 As shown, this method can be implemented in the following ways, including:

[0058] Step S100: Obtain module information of at least two adjacent target modules.

[0059] Step S110: Obtain the layout constraints for at least two target modules.

[0060] Step S120: Determine the port positions of every two adjacent modules based on the module information and layout constraints of at least two target modules.

[0061] In the above embodiments, "at least two adjacent target modules" refers to at least two logic modules that are in an adjacent state among the multiple logic modules divided into the chip. The multiple logic modules of the chip can be obtained through top-level layout planning, which can plan the multiple logic modules of the chip, the position and size of each logic module, and the execution devices and ports in each logic module. As a possible example, such as... Figure 2 As shown, top-level layout planning can yield the following results: Figure 2 The multiple logic modules shown are Block A, Block B, Block C, Block D, Block E, Block F, Block H, and Block G.

[0062] Based on the above, this solution can select at least two adjacent logic modules as the target module. That is, this solution can determine the port positions of two adjacent logic modules. For example, following the previous example, this solution determines the port positions of adjacent Block H and Block G. Furthermore, this solution can also determine the port positions of two or more adjacent logic modules. For example, this solution can determine the port positions of adjacent Block E, Block H, and Block G, thereby determining the port positions between Block E and Block H, and between Block H and Block G. The selection of this target module can be achieved through manual selection.

[0063] In the above embodiments, the module information of the target module may include the execution device and ports in the target module. Specifically, the execution device may be a device required to perform the corresponding function of the target module, such as a circuit device, digital logic gate, etc.; the ports refer to the input ports and output ports of the target module. The output port is used to output signals to adjacent target modules, and the input port is used to receive signals output by the adjacent target module. For example, based on Block H and Block G as target modules, the input port of Block G is the port that receives signals transmitted by Block H, and the output port of Block G is the port that points to the output signal of Block H; similarly, the input port of Block H is the port that receives signals transmitted by Block G, and the output port of Block H is the port that points to the output signal of Block G.

[0064] In the above embodiments, the present solution can also obtain layout constraints of at least two target modules, wherein the layout constraints are used to restrict the execution device of each target module to be within a first restricted area of ​​the corresponding module, and to restrict the ports of each two adjacent target modules to be within a second restricted area of ​​the module connection, wherein the first restricted area can represent the module area of ​​each target module, and the second restricted area can represent the connection area of ​​adjacent target modules.

[0065] like Figure 3 As shown, for example, following the aforementioned example, based on Block H and Block G as target modules, this layout constraint can restrict the actuator in Block H to the Block H module area, restrict the actuator in Block G to the Block G module area, and then restrict the ports of Block H and Block G modules to the range of the AB dashed line area (second restriction area).

[0066] like Figure 4As shown, for example, based on Block E, Block H, and Block G as target modules, this layout constraint can restrict the actuators in Block E to the Block E module area, restrict the actuators in Block H to the Block H module area, restrict the actuators in Block G to the Block G module area, and then restrict the ports of Block H and Block G modules to the AB dashed line area (second restriction area), and the ports of Block E and Block H modules to the CD dashed line area (second restriction area).

[0067] Based on the above, this solution determines the port positions of every two adjacent modules according to the module information and layout constraints of at least two target modules.

[0068] The port location determination method described above first obtains the module information of at least two adjacent target modules, then obtains the layout constraints of at least two target modules, and finally determines the port location of each pair of adjacent modules based on the module information and layout constraints. Since the ports of each pair of adjacent modules are restricted to the second constraint area of ​​the module connection by the layout constraints, when the positions of the actuators within the two target modules change, although the port locations of the target modules also change with the positions of the actuators, the ports of the target modules are always restricted to the second constraint area. Thus, based on the automated determination of port locations, the planned port locations are the optimal port locations, thereby greatly improving the efficiency of port location determination, reducing manpower input and workload, and also improving the accuracy of port location determination.

[0069] In an optional implementation of this embodiment, as one possible implementation, for step S120, this solution may restrict the execution device of each target module to the first restricted area of ​​the corresponding module according to the layout constraint conditions; and restrict the ports of every two adjacent target modules to the second restricted area of ​​the module connection according to the layout constraint conditions, and then perform layout planning on at least two target modules to obtain the port positions of every two adjacent modules after the layout planning is completed.

[0070] As one possible implementation, this solution can determine the port positions of two adjacent target modules by pre-embedding anchor buffers at the ports. Specifically, for example... Figure 5 As shown, the steps may include the following:

[0071] Step S500: Obtain at least one pre-configured set of anchoring buffers.

[0072] Step S510: According to the layout constraints, restrict each set of anchoring buffers to the second constraint area where the two adjacent target modules are connected.

[0073] Step S520: Layout planning is performed for the position of each group of anchoring buffers to obtain the position information of each anchoring buffer in each group of anchoring buffers after the planning is completed.

[0074] Step S530: Determine the port positions of the two adjacent target modules based on the position information of each anchor buffer in each group of anchor buffers.

[0075] In the above implementation, the anchor buffer has no logical function itself, but it has the function of applying force to the signal and transmitting it downward. In this solution, a set of anchor buffers can be configured in advance for each pair of adjacent target modules. Each set of anchor buffers includes multiple anchor buffers, and each anchor buffer corresponds to a port of the two adjacent target modules.

[0076] Specifically, as one possible implementation, each set of anchor buffers corresponds to all input and output ports of one of the two adjacent target modules. Following the aforementioned example, based on Block H and Block G as target modules, a set of anchor buffers can be designed. This set of anchor buffers can correspond to all input and output ports of Block H, or it can correspond to all input and output ports of Block G. Each anchor buffer in this set can correspond to one of the ports. For example, as a specific example, Block H's input ports include 201, 202, and 203, and Block H's output ports include 204, 205, and 206. Based on this, the set of anchor buffers can include anchor buffer 201, anchor buffer 202, anchor buffer 203, anchor buffer 204, anchor buffer 205, and anchor buffer 206, thus corresponding to input ports 201, 202, and 203, and output ports 204, 205, and 206, respectively.

[0077] As another example, based on Block E, Block H, and Block G as target modules, this scheme can design two sets of anchor buffers. The first set of anchor buffers corresponds to all input and output ports of Block E, and the second set corresponds to all input and output ports of Block G. Different sets of anchor buffers correspond to different adjacent target modules. For example, as a specific example, the input and output ports of Block E include 101, 102, and 103, and the input and output ports of Block G include 301, 302, and 303. Based on this, the first set of anchor buffers may include anchor buffer 101, anchor buffer 102, and anchor buffer 103, and the second set of anchor buffers may include anchor buffer 201, anchor buffer 202, and anchor buffer 203. Furthermore, it should be noted that when port names are similar, this scheme can name the anchor buffers by module or port, thereby distinguishing anchor buffers corresponding to ports with similar names.

[0078] As another possible implementation, each set of anchor buffers corresponds to all input ports of one of the two adjacent target modules and all input ports of the other of the two adjacent target modules. For example, as a specific example, based on Block H and Block G as target modules, the input ports of Block H include 201, 202, and 203, and the input ports of Block G include 301, 302, and 303. Based on this, the set of anchor buffers may include anchor buffer 201, anchor buffer 202, anchor buffer 203, anchor buffer 301, anchor buffer 302, and anchor buffer 303. The case of three adjacent target modules is similar and will not be described in detail here.

[0079] In this approach, the scheme uses a set of anchor buffers to represent the ports of two adjacent target modules. This set of anchor buffers is then confined within a second restricted area connecting the two adjacent target modules. For example, following the previous example, this scheme confines anchor buffer 201, anchor buffer 202, anchor buffer 203, anchor buffer 204, anchor buffer 205, and anchor buffer 206 within the AB region. It should be noted that the AB region can be defined around the connection line between the two target modules, for example, as shown below. Figure 6 As shown, the rectangular area around the connecting line.

[0080] Based on the above, this solution plans the layout of each group of anchor buffers, specifically using EDA tools. EDA tools can automatically plan the placement of actuators in two adjacent target modules, thereby finding the optimal placement of actuators in two adjacent target modules. The different positions of the actuators will cause the corresponding anchor buffers at their respective ports to be in different positions within the second restricted area. This yields the position information of the anchor buffers in the second restricted area under the optimal placement of the actuators determined by the EDA tool, i.e., the position information of each anchor buffer in each group of anchor buffers after the layout is completed. It should be noted that this solution can use any current chip design tool for layout planning besides EDA tools, and can be adaptively adjusted according to the actual application scenario.

[0081] Based on the position information of each anchoring buffer, and since each anchoring buffer corresponds to a port, the position of the corresponding port can be determined according to the position information of each anchoring buffer. Furthermore, since in two adjacent target modules, the input port of one target module is always opposite the output port of the other target module, the corresponding port positions of adjacent target modules can be determined based on the port positions determined by the anchoring buffers. For example, ... Figure 6 As shown, this scheme determines anchor buffer 201 as follows: Figure 6As shown, the anchor buffer 201 corresponds to the input port 201 of the Block H module. Therefore, the M position relative to the anchor buffer 201 of the Block H module can be determined as the position of the input port 201 of the Block H module, and the boundary position of the Block G module opposite to the M position is the output port position of the Block G module relative to the input port 201. It should be noted that when there are three or more adjacent target modules, the port position determination method for each pair of adjacent target modules is the same, therefore, it will not be elaborated further here.

[0082] Specifically, as one possible implementation method, this solution can be as follows: Figure 6 The lower left corner of the two adjacent modules shown is the origin, so the coordinate position of the anchor buffer 201 can be obtained. Then, the coordinate position of the input port 201 of the Block H module and the position coordinate of the output port of the Block G module opposite to the input port 201 can be determined by the coordinate position of the anchor buffer 201.

[0083] In an optional implementation of this embodiment, since EDA tools may optimize anchor buffers in some cases—for example, if multiple anchor buffers exist simultaneously in a signal transmission line—the EDA tool may determine that so many anchor buffers are unnecessary and thus delete some anchor buffers for optimization. Therefore, to prevent the anchor buffers configured in this solution from being optimized by the EDA tool, this solution can also set an anti-optimization attribute for the configured anchor buffers when configuring them. This prevents the EDA tool from optimizing the configured anchor buffers, thereby avoiding the situation of missing port positions caused by optimization.

[0084] In the implementation of the above design, this solution pre-embeds a corresponding anchoring buffer for each port and restricts the anchoring buffer to a second restricted area. After optimization by EDA tools, the position of the corresponding port can be determined by the position information of the anchoring buffer, thereby automatically determining the port position, improving the efficiency of port position determination in chip design, and greatly reducing the workload of designers.

[0085] In an optional implementation of this embodiment, in addition to determining the port positions of two adjacent target modules by pre-embedding anchor buffers for the ports, this solution can also set a corresponding port identifier for each port, thereby restricting the port identifier to a second restricted area to determine the port position.

[0086] Specifically, this solution pre-assigns corresponding port identifiers to all input and output ports of one of the target modules in each pair of adjacent target modules. Different ports have different port identifiers. Based on this, this solution also uses EDA tools to plan the layout of the actuators of the two adjacent target modules, thereby obtaining the position of the port identifiers under the optimal placement of the actuators. The obtained position of the port identifier is the position of the corresponding port. As a specific example, the input ports of Block H include 201, 202, and 203, and the output ports of Block H include 204, 205, and 206. Based on this, port identifiers Block H 201, Block H 202, Block H 203, Block H 204, Block H 205, and Block H 206 can be set, corresponding to input ports 201, 202, and 203, and output ports 204, 205, and 206, respectively. The subsequent planning scheme is similar to the aforementioned anchored buffer method, and will not be repeated here. Finally, the position information of the port identifiers obtained by this solution is the position of the corresponding port. It should be noted that when there are three or more target modules, the port positions of every two adjacent target modules are determined in the same way as described above, so it will not be repeated here.

[0087] In the implementation of the above design, this solution sets a corresponding port identifier for each port and restricts the port identifier to a second restricted area. After optimization by EDA tools, the position information of the port identifier is the position of the corresponding port, thereby automatically determining the port position, improving the efficiency of determining the port position in chip design, and greatly reducing the workload of designers.

[0088] In an optional implementation of this embodiment, after obtaining the port positions of every two adjacent modules, this solution can calculate the port delay at each port position, and then determine the timing constraints of the corresponding port based on the port delay at each port position. Specifically, in the aforementioned case of using a pre-embedded descriptor buffer, this solution can calculate the delay from the signal source of each port to the input of the pre-embedded anchor buffer, and the delay from the output of the anchor buffer to the signal endpoint. Then, based on this delay, it can calculate the delay ratio of each signal in each of the two adjacent target modules, thereby determining the port timing constraints of each target module based on the delay ratio of each target module, thus generating relatively accurate port timing convergence constraints.

[0089] Figure 7 A schematic structural block diagram of a port position determination device provided in this application is presented. It should be understood that this device is related to... Figure 1 and Figure 6The method embodiment executed in this document corresponds to the method described above, and the specific functions of the device can be found in the description above. To avoid repetition, detailed descriptions are omitted here. The device includes at least one software function module that can be stored in memory or embedded in the device's operating system (OS) in the form of software or firmware. Specifically, the device includes: an acquisition module 700 and a determination module 710; the acquisition module 700 is used to acquire module information of at least two adjacent target modules; wherein the module information includes the execution devices in the module and the ports of the module; and to acquire layout constraints of at least two target modules; wherein the layout constraints are used to restrict the execution devices of each target module to a first restricted area of ​​the corresponding module and to restrict the ports of each pair of adjacent target modules to a second restricted area of ​​the module connection; the determination module 710 is used to determine the port positions of each pair of adjacent target modules based on the module information and layout constraints of the at least two target modules.

[0090] The port position determination device designed above first obtains the module information of at least two adjacent target modules, then obtains the layout constraints of at least two target modules, and finally determines the port position of each pair of adjacent modules based on the module information and layout constraints. Since the ports of each pair of adjacent modules are restricted to the second restriction area of ​​the module connection by the layout constraints, when the position planning of the actuators in the two target modules changes, although the port position of the target module also changes with the position of the actuators, the port of the target module is always restricted to the second restriction area. Thus, based on the automated determination of port position, the planned port position is the optimal port position, thereby greatly improving the efficiency of port position determination, reducing manpower input and workload, and also improving the accuracy of port position determination.

[0091] In an optional embodiment of this example, the determining module 710 is specifically used to restrict the execution device of each target module to a first restricted area of ​​the corresponding module according to the layout constraints; restrict the ports of every two adjacent target modules to a second restricted area of ​​module connection according to the layout constraints; and perform layout planning on at least two target modules to obtain the port positions of every two adjacent target modules after the layout planning is completed.

[0092] In an optional embodiment of this example, the determining module 710 is further specifically used to obtain at least one pre-configured set of anchoring buffers; wherein each set of anchoring buffers includes multiple anchoring buffers, different adjacent target modules correspond to different sets of anchoring buffers, and each anchoring buffer in the same set corresponds to a port of the corresponding two adjacent target modules; according to the layout constraints, each set of anchoring buffers is restricted to a second restricted area connected to the corresponding two adjacent target modules.

[0093] In an optional embodiment of this example, the determining module 710 is further specifically used to plan the layout of the position of each group of anchoring buffers, obtain the position information of each anchoring buffer in each group of anchoring buffers after the planning is completed, and determine the port position of the corresponding two adjacent target modules according to the position information of each anchoring buffer in each group of anchoring buffers.

[0094] In an optional embodiment of this example, the determining module 710 is further specifically used to obtain the port identifier of each port of each of two adjacent target modules; wherein, different ports have different identifiers; and based on the port identifier of each port, all ports of each of two adjacent target modules are restricted to the second restriction area connected by the corresponding modules.

[0095] In an optional embodiment of this example, the determining module 710 is further specifically used to perform layout planning on the position of each port identifier in every two adjacent target modules, obtain the position information of each port identifier after planning, and determine the position of the corresponding port based on the position information of each port identifier.

[0096] In an optional embodiment of this example, the acquisition module 700 is specifically used to acquire multiple logical modules obtained from the top-level layout planning; wherein, each logical module includes the logical module location, size, and execution devices and ports in the logical module; and at least two adjacent logical modules are acquired as target modules based on the module locations of the multiple logical modules.

[0097] In an optional embodiment of this example, the device further includes a calculation module 720 for calculating the port delay at each port location; the determination module 710 is further used to determine the timing constraints of the corresponding port based on the delay at each port location.

[0098] According to some embodiments of this application, such as Figure 8As shown, this application provides an electronic device 8, including: a processor 801 and a memory 802. The processor 801 and the memory 802 are interconnected and communicate with each other through a communication bus 803 and / or other forms of connection mechanism (not shown). The memory 802 stores a computer program executable by the processor 801. When the computing device is running, the processor 801 executes the computer program to perform the method executed in the aforementioned implementation, such as steps S100 to S120: obtaining module information of at least two adjacent target modules; obtaining layout constraints of at least two target modules; and determining the port position of each pair of adjacent modules based on the module information and layout constraints of at least two target modules.

[0099] This application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the aforementioned method.

[0100] The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0101] This application provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned method.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A method for determining port location, characterized in that, The method includes: Obtain module information for at least two adjacent target modules; wherein the module information includes the execution devices in the module and the ports of the module; Obtain the layout constraints of the at least two target modules; wherein the layout constraints are used to restrict the execution device of each target module within a first restricted area of ​​the corresponding module and to restrict the ports of every two adjacent target modules within a second restricted area of ​​the module connection, the first restricted area representing the module area of ​​each target module and the second restricted area representing the connection area of ​​adjacent target modules; The port positions of each pair of adjacent target modules are determined based on the module information and layout constraints of the at least two target modules. Determining the port positions of each pair of adjacent target modules based on the module information and layout constraints of the at least two target modules includes: Based on the layout constraints, the actuators of each target module are restricted to the first restricted area of ​​the corresponding module; Based on the layout constraints, the ports of every two adjacent target modules are restricted to the second restricted area of ​​module connection; Layout planning is performed on the at least two target modules to obtain the port positions of each pair of adjacent target modules after the layout planning is completed.

2. The method according to claim 1, characterized in that, The step of restricting the ports of every two adjacent target modules to the second restricted area of ​​module connection according to the layout constraints includes: Obtain at least one pre-configured set of anchoring buffers; wherein each set of anchoring buffers includes multiple anchoring buffers, different adjacent target modules correspond to different sets of anchoring buffers, and each anchoring buffer in the same set corresponds to a port of the corresponding two adjacent target modules; According to the layout constraints, each set of anchoring buffers is restricted to a second restricted area where two adjacent target modules are connected.

3. The method according to claim 2, characterized in that, in, Each set of anchoring buffers corresponds to all input and output ports of one of the two adjacent target modules.

4. The method according to claim 2, characterized in that, in, Each set of anchoring buffers corresponds to all input ports of one of the two adjacent target modules and all input ports of the other of the two adjacent target modules.

5. The method according to claim 2, characterized in that, The step of performing layout planning on the at least two target modules to obtain the port positions of each pair of adjacent target modules after layout planning includes: The layout of each group of anchoring buffers is planned to obtain the position information of each anchoring buffer in each group of anchoring buffers after the planning is completed; The port positions of the two adjacent target modules are determined based on the position information of each anchor buffer in each group of anchor buffers.

6. The method according to claim 5, characterized in that, in, Each anchoring buffer is equipped with anti-optimization properties to prevent optimization.

7. The method according to claim 1, characterized in that, The step of restricting the ports of every two adjacent target modules to the second restricted area of ​​module connection according to the layout constraints includes: Obtain the port identifier of each port of every two adjacent target modules; different ports have different identifiers. Restrict all port identifiers of every two adjacent target modules to the second restricted area of ​​the corresponding module connection.

8. The method according to claim 7, characterized in that, The step of performing layout planning on the at least two target modules to obtain the port positions of each pair of adjacent target modules after layout planning includes: Layout planning is performed on the position of each port identifier in every two adjacent target modules to obtain the position information of each port identifier after the planning is completed; The location of the corresponding port is determined based on the location information of each port identifier.

9. The method according to any one of claims 1-8, characterized in that, The step of obtaining module information of at least two adjacent target modules includes: Obtain multiple logical modules from the top-level layout plan; each logical module includes its location, size, execution devices, and ports. Based on the module positions of multiple logic modules, at least two adjacent logic modules are obtained as the target module.

10. The method according to any one of claims 1-8, characterized in that, After determining the port positions of each pair of adjacent target modules based on the module information and layout constraints of the at least two target modules, the method further includes: Calculate the port delay at each port location; The timing constraints for each port are determined based on the delay at each port location.

11. A port position determination device, characterized in that, The device includes an acquisition module and a determination module; The acquisition module is configured to acquire module information of at least two adjacent target modules; wherein the module information includes the execution devices in the module and the ports of the module; and to acquire layout constraints of the at least two target modules; wherein the layout constraints are configured to restrict the execution devices of each target module within a first restricted area of ​​the corresponding module and restrict the ports of each pair of adjacent target modules within a second restricted area of ​​the module connection, wherein the first restricted area represents the module area of ​​each target module and the second restricted area represents the connection area of ​​adjacent target modules; The determining module is used to determine the port positions of each pair of adjacent target modules based on the module information and layout constraints of the at least two target modules. The determining module is specifically used to restrict the execution device of each target module to a first restricted area of ​​the corresponding module according to the layout constraints; restrict the ports of every two adjacent target modules to a second restricted area of ​​module connection according to the layout constraints; and perform layout planning on the at least two target modules to obtain the port positions of every two adjacent target modules after the layout planning is completed.

12. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 10.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 10.

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