Storage system and control method of storage system

Abstract

One embodiment provides a storage system and a control method of the storage system, for example, a storage system including a PLP function can be realized even when a performance of a PLP capacitor is degraded. According to one embodiment, a storage system includes a controller which controls writing of data to a nonvolatile memory and a volatile memory, a power supply circuit which generates a plurality of voltages using a first voltage supplied from outside and supplies the plurality of voltages to the nonvolatile memory, the volatile memory, the controller, and a backup power supply circuit. When the first voltage is not reduced due to a power-off command, the power supply circuit generates the plurality of voltages using an output voltage of the backup power supply circuit. The controller changes a size of data which can be stored in the volatile memory in accordance with a power supply capability fed from the backup power supply circuit.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2021-149340, filed on September 14, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] In summary, the implementation methods described herein relate to storage systems and methods for controlling storage systems. Background Technology

[0004] Solid-state drives (SSDs) are known to be examples of storage systems that include non-volatile memory. In an SSD, data transferred from an external device called the host is temporarily written to volatile memory, which acts as a buffer. Data stored in this buffer is then written to non-volatile memory. When the SSD receives a power-off command from the host (hereinafter referred to as a power-off command), it writes all the data stored in the buffer to the non-volatile memory and then turns off the power. For example, DRAM is used as volatile memory, and NAND flash memory is used as non-volatile memory.

[0005] Some SSDs include Power Loss Protection (PLP) functionality, which prevents data loss in cache memory in the event of a power outage not based on a shutdown command, but rather on an unexpected power outage such as a power failure (i.e., an incorrect power outage). PLP requires a backup power supply. An example of a backup power supply is a capacitor (or PLP capacitor for short). By storing charge in the capacitor, the PLP capacitor can be charged to a specified voltage. If the power supply is unexpectedly cut off for any reason, the charge stored in the PLP capacitor is released, and the charging voltage is discharged. The SSD can then use the discharge voltage from the PLP capacitor to operate for a specified period. For example, if the power supply is unexpectedly cut off while data from the host is being stored in the cache memory, the data being stored in the cache memory can be written to non-volatile memory using the discharge voltage of the PLP capacitor. This functionality is called PLP.

[0006] In PLP capacitors, the capacitance (static capacitance) of the capacitor that stores charge can sometimes decrease due to aging, deterioration, and other factors. For example, if the capacitance of a capacitor decreases due to aging, it may not be possible to charge the capacitor to the voltage level required to write data from the buffer memory to the non-volatile memory, and the PLP capacitor may not function properly. Summary of the Invention

[0007] One implementation provides a storage system and a control method for the storage system, for example, enabling the storage system including PLP functionality even when the performance of the PLP capacitor deteriorates.

[0008] Typically, according to one embodiment, a storage system includes: a non-volatile memory; a volatile memory; a controller for controlling the writing of data to and from the non-volatile memory and the volatile memory; a power supply circuit connected to the non-volatile memory, the volatile memory, and the controller, and generating a plurality of voltages using a first voltage supplied externally, and supplying the plurality of voltages to the non-volatile memory, the volatile memory, and the controller; and a backup power supply circuit. When the first voltage is not reduced due to a power-off command, the power supply circuit generates the plurality of voltages using an output voltage from the backup power supply circuit. The controller adjusts the size of data that can be stored in the volatile memory according to the power supply capacity fed from the backup power supply circuit. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating an example of an information processing system according to a first embodiment.

[0010] Figure 2 This is a plan view showing an example of the appearance of an SSD according to the first embodiment.

[0011] Figure 3A and Figure 3B This is a plan view showing an example arrangement of the constituent components of an SSD according to a first embodiment.

[0012] Figure 4 This is a block diagram illustrating a configuration example of a power supply system according to the first embodiment.

[0013] Figure 5 This is a view of the PLP function showing a comparative example where the health value of the PLP capacitor is equal to or greater than the fault threshold.

[0014] Figure 6 This is a view of the PLP function showing a comparative example where the health value is less than the fault threshold.

[0015] Figure 7 This is a view showing the PLP function of a first embodiment when the health value is greater than or equal to a first threshold.

[0016] Figure 8 This is a diagram illustrating the PLP function of a first embodiment when the health value is less than a first threshold and greater than or equal to a second threshold.

[0017] Figure 9This is a diagram illustrating the PLP function of a first embodiment when the health value is less than a first threshold and greater than or equal to a second threshold.

[0018] Figure 10 This is a view showing the PLP function according to the first embodiment when the health value is less than the second threshold and greater than or equal to the fault threshold.

[0019] Figure 11 This is a view showing the PLP function according to the first embodiment when the health value is less than the second threshold and greater than or equal to the fault threshold.

[0020] Figure 12 This is a diagram illustrating the PLP function according to the first embodiment when the health value is less than the fault threshold.

[0021] Figure 13 This is a flowchart illustrating a processing example of a controller performing a PLP function according to a first embodiment.

[0022] Figure 14 This is a flowchart illustrating another example of the processing of a controller performing a PLP function according to the first embodiment.

[0023] Figure 15 This is a flowchart illustrating a processing example of a controller performing a PLP function according to a second embodiment.

[0024] Figure 16 This is a flowchart illustrating a processing example of a controller performing a PLP function according to a third embodiment.

[0025] Figure 17 This is a flowchart illustrating a processing example of the controller 14 performing the PLP function according to the fourth embodiment. Detailed Implementation

[0026] Various embodiments will be described below with reference to the accompanying drawings.

[0027] This disclosure is merely illustrative and is not limited to the embodiments described below. Modifications readily conceived by those skilled in the art naturally fall within the scope of this invention. For clarity of description, the size, shape, etc., of the parts may be altered and schematically shown in the drawings compared to precise representations. Corresponding constituent elements in the various drawings are indicated by the same reference numerals, and their detailed descriptions may be omitted unless necessary.

[0028] Figure 1This is a block diagram illustrating an example of an information processing system 1 according to a first embodiment. The information processing system 1 includes a storage system 4 and a host device (hereinafter referred to as a host) 2 that can be connected to the storage system 4. The storage system 4 is a storage device configured to write data to and read data from a non-volatile memory 16. In this specification, the storage system 4 is, for example, an SSD. Examples of non-volatile memory are NAND flash memory, NOR flash memory, magnetoresistive random access memory (MRAM), phase-change random access memory (PRAM), resistive random access memory (ReRAM), ferroelectric random access memory (FeRAM), etc. In this specification, the non-volatile memory 16 is, for example, NAND flash memory (hereinafter referred to as NAND memory). As described above, the information processing system 1 includes a host 2 and an SSD 4 connected to the host 2.

[0029] Host 2 is an information processing device used to access external devices connected to SSD 4. Host 2 can be a server (storage server) that stores large amounts and various types of data in SSD 4. Host 2 can be a personal computer. SSD 4 can be an SSD for commercial use assembled into a server such as in a data center. SSD 4 can also be a personal-use SSD assembled into a personal computer.

[0030] SSD 4 includes connector 12, controller 14, NAND memory 16, dynamic random access memory (DRAM) 20, power supply circuitry 24, and backup power supply circuitry 30 including multiple capacitors. SSD 4 can be used as the primary storage device of host 2. SSD 4 can be built into host 2, located externally to host 2, or connected to host 2 via cable or network.

[0031] Controller 14 writes data to NAND memory 16 and reads data from NAND memory 16 according to commands (requests) sent from host 2. Furthermore, controller 14 generates control signals to control the voltage values ​​generated by power supply circuit 24 based on commands sent from host 2 and various information sent from power supply circuit 24. Controller 14 sends the generated control signals to power supply circuit 24. Upon receiving the control signal, controller 14 controls the voltage supplied to each device of SSD 4 (e.g., NAND memory 16, controller 14, and DRAM 20). In addition, controller 14 also controls the execution of PLP functions. Controller 14 can be constructed from circuitry such as a system-on-a-chip (SoC).

[0032] The power supply circuit 24 receives one or more externally supplied voltages to generate the voltages required by each device in the SSD 4. The externally supplied voltage can be an internal power supply or an external power supply. The external power supply can be the power supply of the host 2. Figure 1 In this diagram, the power supply is the power supply for host 2, but the power cord is not shown. Power supply circuit 24 can also draw voltage from backup power supply circuit 30 to generate the voltages required by each device in SSD 4. Power supply circuit 24 can be a single integrated circuit (IC) or multiple ICs. Information indicating various states of power supply circuit 24 is sent to controller 14 according to a specified communication standard. The specified communication standard can be a serial communication standard. One example of a serial communication standard is the I2C format. In this specification, it is assumed that the communication standard between power supply circuit 24 and controller 14 is based on the I2C format.

[0033] DRAM 20 is an example of volatile memory. For example, DRAM 20 is DRAM of the Double Data Rate 3 Low Voltage (DDR3L) standard. DRAM 20 includes buffer memory 22. Buffer memory 22 includes write buffer 22a, read buffer 22b, and management information buffer 22c. Data supplied from host 2 to SSD 4 that is being written to NAND memory 16 or has not yet been written to NAND memory 16 is stored in write buffer 22a. Data read from NAND memory 16 that is being transferred to host 2 or has not yet been transferred to host 2 is stored in read buffer 22b. Lookup tables, various tables used during the operation of SSD 4, and various values ​​are stored in management information buffer 22c. One example of various values ​​is the address of the block whose data has been written to NAND memory 16 via the PLP function, i.e., the address of the non-volatile block. The lookup table represents the correspondence between logical addresses specified by host 2 and physical addresses of NAND memory 16.

[0034] The DRAM 20, as volatile memory, can be located either outside or inside the controller 14. Static random access memory (SRAM), which allows for faster access, can be used instead of DRAM 20 as volatile memory.

[0035] The NAND memory 16 may include a plurality of (e.g., sixteen) NAND chips 18. Each of the NAND chips 18 may include a memory cell array comprising a plurality of memory cells arranged in a matrix. The NAND chips 18 may be formed from memory cell arrays having a two-dimensional structure or from memory cell arrays having a three-dimensional structure.

[0036] The storage cell array comprises multiple blocks. Each of these blocks comprises multiple pages. These blocks serve as the unit for data erase operations. Each of the multiple pages comprises multiple storage cells connected to the same word line. A page is the unit for data write and data read operations.

[0037] Data is stored in write buffer 22a as a write unit, or in read buffer 22b as a read unit. During writing, a page of data read from write buffer 22a is written to NAND memory 16. If a power outage occurs unexpectedly, not due to a shutdown command, and power circuit 24 does not generate voltage during the write process, the data being written to or not being written to NAND memory 16 in write buffer 22a will be lost. Similarly, data in read buffer 22b and management information buffer 22c will also be lost. If SSD 4 receives a shutdown command, controller 14 writes data from buffer memory 22 to NAND memory 16 and then stops the operation of power circuit 24.

[0038] In the first embodiment, a backup power circuit 30 is provided. In the event of an unexpected power outage, the controller 14 can use the backup power circuit 30 to write data from the buffer memory 22 into the NAND memory 16.

[0039] The controller 14 generates control signals to control the voltage values ​​generated by the power supply circuit 24 based on commands (requests) sent from the host 2 and various information sent from the power supply circuit 24. The controller 14 sends the generated control signals to the power supply circuit 24. Therefore, the multiple voltages supplied to the various devices of the SSD 4 are controlled by the controller 14.

[0040] Backup power circuit 30 is connected to power circuit 24. When a power outage occurs unexpectedly, not due to a shutdown command, backup power circuit 30 supplies voltage to power circuit 24 to protect data being written to or not yet written to NAND memory 16. Backup power circuit 30 consists of multiple PLP capacitors connected in parallel. PLP capacitors will be described later with reference to Figure 3. Examples of PLP capacitors include double-layer capacitors, conductive polymer aluminum electrolytic capacitors, conductive polymer tantalum solid electrolytic capacitors, and so on.

[0041] The power supply circuit 24 includes a PLP function, which allows it to continue supplying voltage to the NAND memory 16, controller 14, and DRAM 20 for a certain period of time in the event of an unexpected power outage, not caused by a shutdown command, by using the power supply capacity fed from the backup power supply circuit 30. When an unexpected power outage occurs, the controller 14 sends a command to the power supply circuit 24 to execute the PLP function.

[0042] The power supply capacity corresponds to the combined electrostatic capacitance (total capacitance) accumulated by the multiple PLP capacitors included in the backup power circuit 30. The combined electrostatic capacitance is set according to the time (backup time) during which the power circuit 24 supplies voltage to the NAND memory 16, controller 14, and DRAM 20 to perform the PLP function after power is cut off. This combined electrostatic capacitance (hereinafter sometimes simply referred to as the electrostatic capacitance of the PLP capacitor) is set slightly larger than the following electrostatic capacitance: such that during the voltage supply time, the data being written from the buffer memory 22 to the NAND memory 16 is completed, i.e., the electrostatic capacitance becomes non-volatile. This is because by setting a margin in the electrostatic capacitance of the PLP capacitor, the non-volatile nature of the data stored in the buffer memory 22 can be achieved during the voltage supply time; that is, even if the electrostatic capacitance of the PLP capacitor decreases slightly due to aging or degradation, the PLP function can still be realized.

[0043] The controller 14 includes a CPU 32, a host interface (host I / F) circuit 34, a NAND interface (NAND I / F) circuit 36, and a DRAM interface (DRAM I / F) circuit 38. The CPU 32, host I / F circuit 34, NAND I / F circuit 36, and DRAM I / F circuit 38 are connected to a bus 40. Although not directly shown, a power supply circuit 24 is also connected to the bus 40.

[0044] CPU 32 executes firmware stored in NAND memory 16 to implement various functions. Examples of these functions include charging control of backup power circuit 30 and control using the PLP function of power circuit 24.

[0045] The host I / F circuit 34 is electrically connected to the host 2 via connector 12. The NAND I / F circuit 36 ​​is electrically connected to the NAND memory 16. The DRAM I / F circuit 38 is electrically connected to the DRAM 20.

[0046] The host 2 is electrically connected to the host I / F circuit 34 of the SSD 4, conforming to standards such as Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), AT Accessory (ATA), Serial ATA (SATA), and PCI Express (PCIe). TM Standards such as Ethernet™, Fibre Channel™, NVM Express (NVMe)™, Universal Serial Bus (USB)™, and Universal Asynchronous Receiver / Transmitter (UART)™.

[0047] The NAND I / F circuitry 36, which electrically interconnects the controller 14 and the NAND memory 16, conforms to standards such as Toggle DDR and Open NAND Flash Interface (ONFI). The NAND I / F circuitry 36 is connected to the NAND memory 16 via multiple (e.g., 18) channels.

[0048] Figure 2 This is a plan view showing an example appearance of the SSD 4 according to the first embodiment. The SSD 4 is disposed in a housing 44. A notch 46 is provided at one end of the housing 44. A connector 12 is provided in the notch 46. The connector 12 includes a plurality of pins 12a, including signal pins and power pins. The housing 44 includes an upper housing 44a and a lower housing (not shown). The upper housing 44a and the lower housing are integrated by screws.

[0049] Figure 3A and 3B This is a plan view showing an example of the arrangement of the constituent components of the SSD 4 according to the first embodiment. Figure 3A The surface of the substrate 52 of the SSD 4 (i.e., the surface opposite to the upper housing 44a) is shown. The substrate 52 is rectangular in shape with four sides 52a, 52b, 52c, and 52d. A connector 12 is disposed on one of the shorter sides 52a. The pins 12a of the connector 12 are disposed on the surface of the substrate 52. A controller 14, a DRAM 20, a power supply circuit 24, and a backup power supply circuit 30 are disposed on the surface of the substrate 52. Figure 3B The back side of substrate 52 (i.e., the surface opposite to the lower housing) is shown. NAND chip 18 is disposed on the back side of substrate 52.

[0050] Because controller 14 processes high-speed signals input or output via connector 12, controller 14 is positioned near connector 12. Specifically, controller 14 is positioned between the line connecting the midpoints of the respective long sides 52c and 52d and the short side 52a on the connector 12 side. DRAM 20 is positioned near controller 14.

[0051] The PLP capacitors 28 constituting the backup power circuit 30 are concentrated between the lines connecting the midpoints of the long sides 52c and 52d of the substrate 52 and the short side 52b opposite to the connector 12. The controller 14 is the largest heat source for the components on the substrate 52. The PLP capacitors 28 deteriorate due to heat; however, because the PLP capacitors 28 are arranged as far away from the controller 14 as possible, the heat-induced deterioration is minimized.

[0052] Similar to the PLP capacitor 28, the NAND chip 18 has low heat resistance. The NAND chip 18 is disposed on the side opposite to the side where the controller 14 and the PLP capacitor 28 are located. For example, the NAND chip 18 is concentrated between the line connecting the midpoints of the long sides 52c and 52d of the substrate 52 and the short side 52b opposite to the connector 12. Therefore, by arranging the NAND chip 18 as far away from the controller 14 as possible, the NAND chip 18 is protected from thermal effects.

[0053] Compared to the controller 14, the NAND chip 18 has a smaller impact on the PLP capacitor 28, but it does generate some heat. As shown in the accompanying drawings, the PLP capacitor 28 is preferably located separately from the NAND chip 18. Even so, considering the thermal effects between the components in the SSD 4 when performing layout design, the PLP capacitor 28 may deteriorate due to other external factors, and the PLP function may fail to operate properly. Therefore, this embodiment includes a power supply system as described in detail below.

[0054] Figure 4 This is a block diagram illustrating an example configuration of a power system including a power supply circuit 24 according to the first embodiment, a backup power supply circuit 30 including a PLP capacitor 28, and a health value measurement circuit 74.

[0055] The power supply circuit 24 includes a fuse 62, a load switch 64, a low-dropout (LDO) regulator 66, a DC / DC converter 68, control logic 70, an I2C I / F circuit 72, and an A / D converter 76. The power supply (not shown) generates a voltage, for example, a DC 12V voltage. A current corresponding to the voltage is supplied in series to the LDO regulator 66 and the DC / DC converter 68 through the fuse 62 and the load switch 64. The host device 2 may include a power supply that can supply a current corresponding to the voltage to the power supply circuit 24. The single or multiple ICs constituting the power supply circuit 24 may be referred to as a power management integrated circuit (PMIC).

[0056] Fuse 62 is a metal fuse that blows when an overcurrent exceeding a certain current flows through it. When fuse 62 blows, no voltage is supplied to load switch 64 unless the fuse is replaced. Fuse 62 is not limited to a metal fuse; it can also be an electronic fuse that becomes non-conductive when an overcurrent is detected.

[0057] Load switch 64 is an on / off switch that is normally in the ON state. In the ON state, load switch 64 outputs a voltage obtained by subtracting the dropout voltage from the supply voltage. Similar to fuse 62, load switch 64 turns OFF when an overcurrent exceeding a certain threshold flows. In the OFF state, load switch 64 outputs 0V. The overcurrent value at which fuse 62 blows can be higher, lower, or equal to the overcurrent value at which load switch 64 changes from the ON state to the OFF state. Both fuse 62 and load switch 64 provide a dual protection against overcurrent supply to LDO regulator 66 and DC / DC converter 68.

[0058] The LDO regulator 66 is a circuit used to generate one or more voltages for one or more SSDs 4 that require low current. The DC / DC converter 68 is a circuit used to generate one or more voltages for one or more SSDs 4 that require high current. The LDO regulator 66 can be formed by an independent IC or a single IC. The DC / DC converter 68 can also be formed by an independent IC or a single IC.

[0059] LDO regulator 66 reduces the voltage output of load switch 64. The voltage output of LDO regulator 66 is then supplied to controller 14.

[0060] DC / DC converter 68 boosts or bucks the output voltage of load switch 64 to generate one (or more) voltages required by the various devices in SSD 4 (controller 14, NAND memory 16, DRAM 20, etc.). DC / DC converter 68 consists of multiple DC / DC converter units that boost or buck multiple voltages respectively.

[0061] The boost DC / DC converter unit boosts the output voltage of the load switch 64 and provides the boosted voltage as a charging voltage to multiple PLP capacitors 28 connected in parallel. The multiple PLP capacitors 28 constitute the backup power supply circuit 30.

[0062] The buck DC / DC converter unit generates multiple voltages by stepping down the output voltage of the load switch 64. The voltages generated by the buck DC / DC converter unit are supplied to the NAND memory 16, the DRAM 20, and the controller 14.

[0063] Control logic 70 monitors the output voltage of load switch 64. When it detects that the output voltage has dropped to a specified voltage (e.g., 0V), control logic 70 sends the detection result to controller 14. Even if controller 14 does not receive a shutdown command, when it is notified that the output voltage of load switch 64 has become 0V, controller 14 determines that an unexpected power outage has occurred that is not caused by shutdown and sends a PLP command to control logic 70.

[0064] Upon receiving a PLP command, control logic 70 inputs the voltage (output voltage) from charging PLP capacitor 28 to the buck DC / DC converter unit in DC / DC converter 68. As a result, for a period of time after an unexpected power outage, the buck DC / DC converter unit steps down the output voltage of PLP capacitor 28 and provides the stepped-down voltage to NAND memory 16, DRAM 20, and controller 14, as well as to LDO regulator 66. Consequently, for a period of time after an unexpected power outage, DC / DC converter 68 and LDO regulator 66 can provide the voltage (or multiple voltages) generated by stepping down the output voltage of PLP capacitor 28 to NAND memory 16, DRAM 20, and controller 14. The PLP function is implemented by using the output voltage of PLP capacitor 28; that is, data in buffer memory 22 is written to NAND memory 16, i.e., non-volatile.

[0065] The I2C I / F circuit 72 is connected to the bus 40 of the control logic 70 and the controller 14 to communicate with the controller 14 in response to control signals sent from the control logic 70. The I2C I / F circuit 72 provides control signals from the controller 14 to the control logic 70.

[0066] A health value measurement circuit 74 is connected in parallel with multiple PLP capacitors 28. The health value measurement circuit 74 measures the combined electrostatic capacitance (total capacitance) accumulated by the parallel-connected PLP capacitors 28 and outputs the measurement result as the health value of the PLP capacitors 28. The health value represents the power supply capability fed from the backup power circuit 30. The health value corresponds to the time during which the PLP capacitors 28 can output voltage to achieve the PLP function. In other words, the health value corresponds to the amount of data that the output voltage of the PLP capacitors 28 can write to the NAND memory 16. If the health value is higher than or equal to a threshold, it is determined that the PLP function can be achieved. If the health value is lower than the threshold, it is determined that the PLP function cannot be achieved and the SSD 4 fails. The health value measurement circuit 74 measures and outputs the health value at fixed intervals. The health value output from the health value measurement circuit 74 is provided to the control logic 70 via an A / D converter 76.

[0067] The PLP function will be described below.

[0068] First, the PLP function of the comparative example will be described. The hardware configuration of the comparative example is... Figures 1 to 4 The hardware configuration is the same as in the first embodiment shown. However, the control operation of the controller 14, which is related to the PLP function, differs from that in the first embodiment.

[0069] In the comparative example, a single fault threshold is set as a threshold used to determine the health value or power supply capability of the PLP capacitor 28 in case of degradation. The fault threshold is set based on the size of the PLP object data that can be stored in buffer memory 22 and written to NAND memory 16 via the PLP function. This size can be referred to as the data storage capacity of buffer memory 16. When the PLP capacitor 28 degrades, in some cases, it is typically not possible to charge the PLP capacitor 28 to the specified voltage required to write all the PLP object data stored in buffer memory 22 to NAND memory 16. To predict that the PLP capacitor 28 cannot be used as a PLP capacitor, the controller 14 compares the health value of the PLP capacitor 28 measured by the health value measurement circuit 74 with the fault threshold.

[0070] Figure 5 This is a view illustrating a comparative example of the PLP function when the health value of PLP capacitor 28 is equal to or greater than the fault threshold. In this case, the size of the data that the output voltage of PLP capacitor 28 can be written into NAND memory 16 is greater than the size of the PLP object data 102 stored in buffer memory 22. All PLP object data 102 can be written into NAND memory 16 via the PLP function.

[0071] Figure 6 This is a view showing a comparative example of the PLP function when the health value is less than the fault threshold. In this case, the amount of data that can be written to the NAND memory 16 via the output voltage of the PLP capacitor 28 is less than the size of the PLP object data 106 stored in the buffer memory 22. A portion 106a (the portion 106a corresponding to the health value) of the PLP object data 106 can be written to the NAND memory 16 via the PLP function, but the remaining portion 106b of the PLP object data 106 cannot be written to the NAND memory 16 via the PLP function (non-volatile failure), therefore, the SSD 4 is considered to have failed.

[0072] Therefore, in the comparative example, SSD 4 is considered to have failed when the health value is less than the failure threshold.

[0073] Next, the PLP function provided by the SSD 4 in the first embodiment will be described. In the first embodiment, a fault threshold and at least one value greater than the fault threshold are set as health values ​​or power supply capability thresholds to determine the degradation of the PLP capacitor 28. Two values ​​are set: a second threshold greater than the fault threshold and a first threshold greater than the second threshold. However, only the first threshold may be set to a value other than the fault threshold, or three or more thresholds may be set to values ​​that are not fault thresholds. In the comparative example, the health value threshold is only one fault threshold, and the size of the PLP object data that can be stored in the buffer memory 22 is fixed. However, in the first embodiment, multiple thresholds are set, and the size of the PLP object data (or the effective size of the buffer memory 22) is variable. The effective size of the buffer memory 22 is the maximum storable size of the buffer memory 22 that can store data. The data stored in the buffer memory 16 includes data sent from the host 2 to the SSD 4, log data for user data, data for ECC, data related to lookup tables, etc. The buffer memory 22 is not limited to physical memory and may also be implemented using logical (virtual) buffers.

[0074] The controller 14 controls the writing to the buffer memory 22 so that the size of the data stored in the buffer memory 22 is not greater than or equal to the effective size. For example, when the size of the data stored in the buffer memory 22 may become larger than the effective size, the controller 14 writes a portion of the data stored in the buffer memory 22 to the NAND memory 16, and then reduces the size of the data stored in the buffer memory 22 by deleting that portion of data.

[0075] Initially, controller 14 sets the effective size of buffer memory 22 to a size corresponding to a health value greater than or equal to a first threshold. Controller 14 compares the health value of PLP capacitor 28, measured by health value measurement circuit 74, with the first threshold.

[0076] Figure 7 This is a view illustrating the PLP function of the SSD 4 according to the first embodiment when the health value is greater than or equal to a first threshold. In this case, the output voltage of the PLP capacitor 28 can write a data size greater than the size of the PLP object data 112 stored in the buffer memory 22 into the NAND memory 16. All PLP object data 112 can be written into the NAND memory 16 via the PLP function, and the PLP function operates normally.

[0077] Figure 8This is a view illustrating the PLP function of the SSD 4 according to the first embodiment when the health value is less than a first threshold and greater than or equal to a second threshold. In this case, the size of the data that can be written to the NAND memory 16 by the output voltage of the PLP capacitor 28 is smaller than the size of the PLP object data 114 stored in the buffer memory 22. Therefore, all PLP object data 114 cannot be written to the NAND memory 16 by the PLP function. The controller 14 changes the effective size of the buffer memory 22 from a size corresponding to the first threshold to a size corresponding to the second threshold. That is, the controller 14 reduces the effective size of the buffer memory 22. This reduction also reduces the PLP object data 114 to PLP object data 114a, which is a part of it. As a result, the size of the data that can be written to the NAND memory 16 by the output voltage of the PLP capacitor 28 becomes larger than the reduced size of the PLP object data 114a. Therefore, all PLP object data 114a can be written to the NAND memory 16.

[0078] Before the effective size of buffer memory 22 is reduced, controller 14 writes the difference between data 114b (i.e., PLP object data 114) and the reduced PLP object data 114a into NAND memory 16. An example of the difference data to be written to NAND memory 16 is data stored in write buffer 22a that is being written to NAND memory 16 or not yet written to NAND memory 16. Alternatively, an example of the difference data is a specific size of data written to buffer memory 22, including the most recent data written to buffer memory 22.

[0079] Figure 9 This is a view illustrating the PLP function of the SSD 4 according to the first embodiment when the health value is less than a first threshold and greater than or equal to a second threshold. In this case, the output voltage of the PLP capacitor 28 can write a data size greater than the size of the PLP object data 118 stored in the buffer memory 22 into the NAND memory 16. All PLP object data 118 can be written into the NAND memory 16 via the PLP function, and the PLP function operates normally.

[0080] Figure 10This is a view showing the PLP function of the SSD 4 according to the first embodiment when the health value is less than the second threshold and greater than or equal to the fault threshold. In this case, the size of the data that can be written to the NAND memory 16 by the output voltage of the PLP capacitor 28 is smaller than the size of the PLP object data 122 stored in the buffer memory 22. Therefore, not all PLP object data 122 can be written to the NAND memory 16 by the PLP function. The controller 14 changes the effective size of the buffer memory 22 from the size corresponding to the second threshold to the size corresponding to the fault threshold. That is, the controller 14 reduces the effective size of the buffer memory 22. This reduction also reduces the PLP object data 122 to PLP object data 122a, which is a part of it. As a result, the size of the data that can be written to the NAND memory 16 by the output voltage of the PLP capacitor 28 becomes larger than the reduced size of the PLP object data 122a. Therefore, all PLP object data 122a can be written to the NAND memory 16.

[0081] Before the effective size of buffer memory 22 is reduced, controller 14 writes the difference between data 122b (i.e., PLP object data 122) and the reduced PLP object data 122a to NAND memory 16. An example of the difference data to be written to NAND memory 16 is data stored in write buffer 22a that is being written to NAND memory 16 or not yet written to NAND memory 16. Alternatively, an example of the difference data is a specific size of data written to buffer memory 22, including the most recent data written to buffer memory 22.

[0082] Figure 11 This is a view illustrating the PLP function of the SSD 4 according to the first embodiment when the health value is less than the second threshold and greater than or equal to the fault threshold. In this case, the size of the data that can be written to the NAND memory 16 by the output voltage of the PLP capacitor 28 is greater than the size of the PLP object data 126 stored in the buffer memory 22. All PLP object data 126 can be written to the NAND memory 16 by the PLP function, and the PLP function operates normally.

[0083] Figure 12This is a view showing the PLP function of the SSD 4 according to the first embodiment when the health value is less than the fault threshold. In this case, the amount of data that can be written to the NAND memory 16 by the output voltage of the PLP capacitor 28 is smaller than the size of the PLP object data 128 stored in the buffer memory 22. A portion 128a of the PLP object data 128 (the portion 128a corresponding to the health value) can be written to the NAND memory 16 by the PLP function, but the remaining portion 128b cannot be written to the NAND memory 16 by the PLP function (non-volatile failure). The PLP function cannot operate normally, so the SSD 4 is considered to have failed.

[0084] Figure 13 It shows the basis Figures 7 to 12 The flowchart shown is a first embodiment of the process example in which the controller 14 performs the PLP function of the SSD 4.

[0085] In step S102, controller 14 determines whether it has received a boot command from host 20. Controller 14 repeats step S102 until it receives a boot command. DDS 4 can be set with a first threshold, a second threshold, and a fault threshold. Alternatively, host 2 can set these thresholds. When host 2 sets these thresholds in SSD 4, host 2 can send a boot command along with information representing the thresholds to SSD 4.

[0086] When a start command is received (Yes in S102), the controller 14 performs a diagnostic of the PLP capacitor 28 in step S104. Specifically, the controller 14 receives the health value measured by the health value measurement circuit 74.

[0087] In step S106, controller 14 determines whether the health value is greater than or equal to the first threshold. When the health value is greater than or equal to the first threshold (yes in S106), controller 14 determines in step S108 whether the PLP activation time has arrived. When control logic 70 notifies controller 14 that the output voltage of load switch 64 has become 0V, controller 14 determines that the PLP activation time has arrived even if controller 14 has not received a shutdown command.

[0088] Controller 14 repeats step S108 until the PLP activation time arrives. When the PLP activation time arrives (Yes in S108), controller 14 executes the PLP function in step S112. In this case, all PLP object data 112 is made non-volatile, such as... Figure 7 As shown in the image.

[0089] When it is determined in step S106 that the health value is less than the first threshold (No in S106), the controller 14 determines in step S114 whether the health value is greater than or equal to the second threshold. When the health value is greater than or equal to the second threshold (Yes in S114), the controller 14 reduces the effective size of the buffer memory 22 in step S116 to a size corresponding to the second threshold, such as... Figure 8 As shown, this is because the health value is less than the first threshold and greater than or equal to the second threshold.

[0090] In step S118, controller 14 determines whether the PLP activation time has arrived. Controller 14 repeats the determination in step S118 until the PLP activation time arrives. When the PLP activation time arrives (yes in S118), controller 14 executes the PLP function in step S122. In this case, all PLP object data 118 is made non-volatile, such as... Figure 9 As shown in the image.

[0091] When it is determined in step S114 that the health value is less than the second threshold (No in S114), the controller 14 determines in step S124 whether the health value is greater than or equal to the fault threshold. When the health value is greater than or equal to the fault threshold (Yes in S124), the health value is less than the second threshold and greater than or equal to the fault threshold. Therefore, in step S126, the controller 14 reduces the effective size of the buffer memory 22 to a size corresponding to the fault threshold, such as... Figure 10 As shown in the image.

[0092] In step S128, controller 14 determines whether the PLP activation time has arrived. Controller 14 repeats the determination in step S128 until the PLP activation time arrives. When the PLP activation time arrives (yes in S128), controller 14 executes the PLP function in step S132. In this case, all PLP object data 126 is made non-volatile, such as... Figure 11 As shown in the image.

[0093] When it is determined in step S124 that the health value is less than the fault threshold (No in S124), the controller 14 performs fault handling in step S134. As an example of fault handling, the controller 14 may notify the host 2 that the PLP function cannot work properly due to the performance degradation of the PLP capacitor 28 (i.e., the SSD 4 has failed).

[0094] Figure 14 It shows the basis Figures 7 to 12 The flowchart shown in the first embodiment illustrates another processing example of the controller 14 performing the PLP function of the SSD 4.

[0095] In step S152, controller 14 determines whether it has received a shutdown command from host 20. Controller 14 repeats step S152 until it receives a shutdown command. Host 2 may send a shutdown command to SSD 4, which includes information representing a first threshold, a second threshold, and a fault threshold.

[0096] Upon receiving a shutdown command (Yes in S152), controller 14 performs a diagnostic check on PLP capacitor 28 in step S154. Subsequently, controller 14 determines in step S106 whether the health value is greater than or equal to a first threshold, similar to... Figure 13 The process is shown in the diagram. After this, the effective size of buffer memory 22 is changed as needed. The changed effective size is permanently stored in NAND memory 16.

[0097] Figure 13 An example of performing diagnostics on PLP capacitor 28 during boot is shown. Figure 14 An example of performing a diagnostic on PLP capacitor 28 during power-off is shown. Diagnostics on PLP capacitor 28 and changes to the effective size of buffer memory 22 can be performed at other times. For example, the diagnostic can be performed when command processing on host 2 is infrequent, or periodically.

[0098] According to the first embodiment, even when the performance of the PLP capacitor 28 deteriorates and the combined electrostatic capacitance of the PLP capacitor 28 decreases, the controller 14 does not immediately determine that the PLP function will malfunction. Instead, it is set to reduce the effective size of the buffer memory 22 (i.e., the PLP object data size) to continue the operation of the PLP function. By reducing the effective size of the buffer memory 22, the frequency of waiting for the buffer memory 22 to have sufficient available space corresponding to the size of the data to be written increases, and the frequency of executing the internal processing of writing data from the buffer memory 22 to the NAND memory 16 of the SSD 4 also increases. Therefore, the SSD 4's processing capability for commands from the host 2 is reduced, but the time of PLP function cessation and the eventual failure of the SSD 4 can be delayed. In other words, the operating cycle of the SSD 4 can be extended.

[0099] Figure 15 This is a flowchart illustrating a processing example of the controller 14 performing the PLP function according to the second embodiment. The hardware configuration of the second embodiment is... Figures 1 to 4 The hardware configuration is the same as in the first embodiment shown. However, the control operation of the controller 14 associated with the PLP function differs from that in the first embodiment.

[0100] In step S202, controller 14 determines whether it has received a boot command from host 20. Controller 14 repeats the determination in step S102 until it receives a boot command. Host 2 may send a boot command to SSD 4, which includes information representing a first threshold, a second threshold, and a fault threshold.

[0101] When a start command is received (Yes in S202), the controller 14 performs a diagnostic of the PLP capacitor 28 in step S204.

[0102] In step S206, controller 14 determines whether it has received a PLP mode specification command from host 20. In the second embodiment, a single-threshold mode where the health value threshold is only the fault threshold set in the comparative example, and a multi-threshold mode where the health value threshold includes at least one threshold other than the fault threshold set in the first embodiment, are set to PLP mode. After sending a start command to SSD 4, host 2 sends a PLP mode specification command to specify either single-threshold mode or multi-threshold mode. Controller 14 repeats the determination in step S206 until it receives the PLP mode specification command.

[0103] When a PLP mode specification command is received (Yes in S206), the controller 14 determines in step S208 whether the PLP mode specification command specifies a single threshold mode or a multi-threshold mode. When a multi-threshold mode is specified, the controller 14 determines in step S106 whether the health value is greater than or equal to the first threshold, similar to the first embodiment. Afterwards, the effective size of the buffer memory 22 may be changed in certain situations.

[0104] When a single threshold mode is specified, controller 14 determines in step S212 whether the health value is greater than or equal to the fault threshold. If the health value is greater than or equal to the fault threshold (Yes in S212), controller 14 determines whether the PLP activation time has arrived. Controller 14 repeats the determination in step S214 until the PLP activation time arrives. When the PLP activation time arrives (Yes in S214), controller 14 executes the PLP function in step S216. In this case, all PLP object data 102 is non-volatile, such as... Figure 5 As shown in the diagram, the fault threshold for the single-threshold mode is set to a different value than the fault threshold for the multi-threshold mode. For example, the fault threshold for the single-threshold mode can be set to the first threshold of the multi-threshold mode.

[0105] When it is determined in step S212 that the health value is less than the fault threshold (No in S212), the controller 14 performs fault handling in step S218.

[0106] Host 2 can send a PLP mode specified command after the shutdown command, send the command when Host 2 has processed fewer commands, or send the command at fixed intervals.

[0107] According to the second embodiment, as a PLP mode, the SSD 4 has a single threshold mode with a single threshold for determining the health value of the PLP capacitor 28 for PLP function failure and a multi-threshold mode with multiple thresholds, and the host 2 can select the PLP mode.

[0108] Figure 16 This is a flowchart illustrating a processing example of the controller 14 performing the PLP function according to the third embodiment. The hardware configuration of the third embodiment and... Figures 1 to 4 The hardware configuration is the same as in the first embodiment shown. However, the control operation of the controller 14, which is related to the PLP function, differs from that in the first embodiment. Figure 16 In the flowchart, the same reference numerals are used to represent the same... Figure 13 The same processing is used.

[0109] The controller 14 receives the start command (step S102), performs the diagnosis of the PLP capacitor 28 (step 104), and determines whether the health value is greater than or equal to the first threshold (step S106).

[0110] When the health value is less than the first threshold (No in S106), the controller 14 determines whether the health value is greater than or equal to the second threshold (step S114).

[0111] When the health value is greater than or equal to the second threshold (Yes in S114), the controller 14 reduces the effective size of the buffer memory 22 to a size corresponding to the second threshold in step S116. In step S302, the controller 14 sends information to the host 2 indicating at least one of the health value of the PLP capacitor 28 and the reduced effective size of the buffer memory 22. In step S118, the controller 14 determines whether the PLP activation time has arrived.

[0112] When the health value is less than the second threshold (No in S114), the controller determines whether the health value is greater than or equal to the fault threshold (step S124). When the health value is greater than or equal to the fault threshold (Yes in S124), the controller 14 reduces the effective size of the buffer memory 22 to a size corresponding to the fault threshold in step S126. In step S304, the controller 14 sends information to the host 2 indicating at least one of the health value of the PLP capacitor 28 and the reduced effective size of the buffer memory 22. In step S128, the controller 14 determines whether the PLP activation time has arrived.

[0113] When the health value is less than the fault threshold (No in S124), the controller 14 performs fault handling in step S134.

[0114] According to the third embodiment, the host 2 can receive information representing at least one of the health value of the PLP capacitor 28 and the reduced effective size of the buffer memory 22. The host 2 can predict the time before the SSD 4 fails due to a PLP function malfunction based on the change in the health value of the PLP capacitor 28. Alternatively, the host 2 can predict the time before the SSD 4 fails due to a PLP function malfunction based on the reduction rate of the effective size of the buffer memory 22 (=(CB) / C), where C is the initial value of the effective size of the buffer memory 22 and B is the reduced effective size of the buffer memory 22.

[0115] A modified example of performing diagnostics on PLP capacitor 28 after receiving a shutdown command has been described in the first embodiment. Figure 14 In the third embodiment, the diagnosis of PLP capacitor 28 can also be performed after receiving the shutdown command. In this case, after receiving the shutdown command and diagnosing PLP capacitor 28, controller 14 sends information to host 2 indicating at least one of the health value of PLP capacitor 28 and the reduced effective size of buffer memory 22.

[0116] Figure 17 This is a flowchart illustrating a processing example of the controller 14 performing the PLP function according to the fourth embodiment. The hardware configuration of the fourth embodiment and... Figures 1 to 4 The hardware configuration is the same as in the first embodiment shown. However, the control operation of the controller 14 associated with the PLP function differs from that in the first embodiment.

[0117] In step S312, controller 14 determines whether it has received a notification request command from host 20. Controller 14 performs the determination in step S312 in the background while executing other processing. When host 20 requests information from controller 14 indicating at least one of the health value of PLP capacitor 28 and the reduced effective size of buffer memory 22, host 20 sends a notification request command to controller 14. Controller 14 repeats the determination in step S132 until it receives the notification request command.

[0118] When a notification request command is received (Yes in S312), the controller 14 performs a diagnosis of the PLP capacitor 28 in step S314.

[0119] In step S316, the controller 14 sends information to the host 2 indicating at least one of the health value of the PLP capacitor 28 and the effective size of the buffer memory 22.

[0120] According to the fourth embodiment, the host 2 can receive information indicating at least one of the health value of the PLP capacitor 28 and the effective size of the buffer memory 22 at the required time.

[0121] Although certain embodiments have been described, they are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein can be embodied in many other forms; furthermore, various omissions, substitutions, and changes can be made to the forms of the embodiments described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover these forms or modifications that fall within the scope and spirit of the invention.

[0122] Figure label:

[0123] 2: Host

[0124] 4: SSD

[0125] 14: Controller

[0126] 16: NAND memory

[0127] 22: Buffer memory

[0128] 24: Power supply circuit

[0129] 30: Backup power supply circuit

Claims

1. A storage system comprising: a nonvolatile memory; a volatile memory; a controller that controls writing of data to the nonvolatile memory and writing of data to the volatile memory; a power supply circuit that is connected to the nonvolatile memory, the volatile memory, and the controller, and generates a plurality of voltages using a first voltage supplied from the outside and supplies the plurality of voltages to the nonvolatile memory, the volatile memory, and the controller; and a backup power supply circuit that is charged using one of the plurality of voltages, the power supply circuit generates the plurality of voltages using an output voltage from the backup power supply circuit when the first voltage is not reduced due to a shutdown command, the controller changes a size of data storable in the volatile memory in accordance with a power supply capacity fed from the backup power supply circuit, when the power supply capacity is smaller than a first value, the controller writes first data of the data stored in the volatile memory to the nonvolatile memory and reduces the size of the data storable in the volatile memory by the size of the first data.

2. The storage system according to claim 1, wherein the backup power supply circuit includes a plurality of capacitors, and the power supply capacity corresponds to electrostatic capacitances of the plurality of capacitors charged.

3. The storage system according to claim 1, wherein when the first voltage is smaller than a first level without receiving a shutdown command from an external device, the power supply circuit supplies a voltage corresponding to an output voltage of the backup power supply circuit to the nonvolatile memory, the volatile memory, and the controller.

4. The storage system according to claim 1, wherein after reducing the size of the data storable in the volatile memory, and when the power supply capacity is smaller than a second value, the controller writes second data of the data stored in the volatile memory to the nonvolatile memory and reduces the size of the data storable in the volatile memory by the size of the second data, wherein the second value is smaller than the first value.

5. The storage system according to claim 1, wherein the controller receives a second value smaller than the first value, after reducing the size of the data storable in the volatile memory, and when the power supply capacity is smaller than the second value, the controller writes second data of the data stored in the volatile memory to the nonvolatile memory and reduces the size of the data storable in the volatile memory by the size of the second data.

6. The storage system according to claim 1, wherein the nonvolatile memory includes: a write buffer that stores data that is being written to the nonvolatile memory in progress or data that has not been written to the nonvolatile memory; a read buffer that stores data that is read out from the nonvolatile memory and is being transmitted to an external device or data that has not been transmitted to the external device; and a cache memory that stores data that is read out from the nonvolatile memory and is being transmitted to the external device or data that has not been transmitted to the external device. managing data buffer storing management data for writing data to the nonvolatile memory, when the power supply capability is less than the first value, the controller writes data in the write buffer to the nonvolatile memory and reduces the size of the data storable in the volatile memory by the size of the write buffer.

7. The storage system according to claim 6, wherein after reducing the size of the data storable in the volatile memory, and when the power supply capability is less than a second value, the controller writes data in the write buffer to the nonvolatile memory and reduces the size of the data storable in the volatile memory by the size of the write buffer, wherein the second value is less than the first value.

8. The storage system according to claim 1, wherein when the power supply capability is less than the first value, the controller writes data of a size to the nonvolatile memory and reduces the size of the data storable in the volatile memory by the size, wherein the data of the size includes latest data written to the volatile memory.

9. The storage system according to claim 8, wherein after reducing the size of the data storable in the volatile memory, and when the power supply capability is less than a second value, the controller writes data of a size to the nonvolatile memory and reduces the size of the data storable in the volatile memory by the size, wherein the second value is less than the first value, the data of the size includes latest data written to the volatile memory.

10. A storage system comprising: a nonvolatile memory; a volatile memory; a controller that controls writing of data to the nonvolatile memory and writing of data to the volatile memory; a power supply circuit that is connected to the nonvolatile memory, the volatile memory and the controller, and generates a plurality of voltages using a first voltage supplied from outside and supplies the plurality of voltages to the nonvolatile memory, the volatile memory and the controller; and a backup power supply circuit that is charged using one of the plurality of voltages, when the first voltage is not reduced due to a power-off command, the power supply circuit generates the plurality of voltages using an output voltage from the backup power supply circuit, the controller changes a size of data storable in the volatile memory in accordance with a power supply capability fed from the backup power supply circuit, the controller receives information indicating a first value from an external device, when the power supply capability is less than the first value, the controller writes first data of data stored in the volatile memory to the nonvolatile memory and reduces the size of the data storable in the volatile memory by the size of the first data.

11. The storage system according to claim 10, wherein ​ When the power supply capability is less than a third value, the controller transmits information indicating the power supply capability to the external device, wherein the third value is less than the second value.

12. The storage system according to claim 10, wherein the controller receives information indicating a third value less than the second value from the external device, When the power supply capability is less than the third value, the controller transmits information indicating the power supply capability to the external device.

13. The storage system according to claim 10, wherein the backup power supply circuit includes a plurality of capacitors, and the power supply capability corresponds to an electrostatic capacitance charged by the plurality of capacitors.

14. The storage system according to claim 10, wherein When the first voltage is less than the first level without receiving a shutdown command from the external device, the power supply circuit supplies a voltage corresponding to an output voltage of the backup power supply circuit to the nonvolatile memory, the volatile memory, and the controller.

15. A storage system comprising: a nonvolatile memory; a volatile memory; a controller that controls writing of data to the nonvolatile memory and writing of data to the volatile memory; a power supply circuit that is connected to the nonvolatile memory, the volatile memory, and the controller, and generates a plurality of voltages using a first voltage supplied from the outside, and supplies the plurality of voltages to the nonvolatile memory, the volatile memory, and the controller; and a backup power supply circuit that is charged using one of the plurality of voltages, when the first voltage is not reduced due to a shutdown command, the power supply circuit generates the plurality of voltages using an output voltage from the backup power supply circuit, the controller changes a size of data storable in the volatile memory in accordance with a power supply capability fed from the backup power supply circuit, the controller transmits information indicating at least one of the power supply capability and the size of the data storable in the volatile memory to an external device, after reducing the size of the data storable in the volatile memory, the controller transmits information indicating at least one of the power supply capability and the size of the data storable in the volatile memory to the external device.

16. The storage system according to claim 15, wherein the backup power supply circuit includes a plurality of capacitors, and the power supply capability corresponds to an electrostatic capacitance charged by the plurality of capacitors.

17. The storage system according to claim 15, wherein When the first voltage is less than the first level without receiving a shutdown command from the external device, the power supply circuit supplies a voltage corresponding to an output voltage of the backup power supply circuit to the nonvolatile memory, the volatile memory, and the controller.

18. A storage system comprising: a nonvolatile memory; a volatile memory; a controller that controls writing of data to the nonvolatile memory and writing of data to the volatile memory; a power supply circuit connected to the nonvolatile memory, the volatile memory, and the controller, and generating a plurality of voltages using a first voltage supplied from the outside and supplying the plurality of voltages to the nonvolatile memory, the volatile memory, and the controller; and a backup power supply circuit charged with one of the plurality of voltages, when the first voltage is not reduced due to a shutdown command, the power supply circuit generates the plurality of voltages using an output voltage from the backup power supply circuit, the controller changes a size of data storable in the volatile memory in accordance with a power supply capacity fed from the backup power supply circuit, the controller transmits information indicating at least one of the power supply capacity and the size of data storable in the volatile memory to an external device, after receiving a notification request from the external device, the controller transmits information indicating at least one of the power supply capacity and the size of data storable in the volatile memory to the external device.

19. The storage system according to claim 18, wherein the backup power supply circuit includes a plurality of capacitors, and the power supply capacity corresponds to electrostatic capacitances charged by the plurality of capacitors.

20. The storage system according to claim 18, wherein when the first voltage is less than a first level without receiving a shutdown command from an external device, the power supply circuit supplies a voltage corresponding to an output voltage of the backup power supply circuit to the nonvolatile memory, the volatile memory, and the controller.

21. A storage system comprising: a nonvolatile memory; a volatile memory; a controller that controls writing of data to the nonvolatile memory and writing of data to the volatile memory; a power supply circuit connected to the nonvolatile memory, the volatile memory, and the controller, and generating a plurality of voltages using a first voltage supplied from the outside and supplying the plurality of voltages to the nonvolatile memory, the volatile memory, and the controller; and a backup power supply circuit charged with one of the plurality of voltages, when the first voltage is not reduced due to a shutdown command, the power supply circuit generates the plurality of voltages using an output voltage from the backup power supply circuit, the controller operates in one of a first mode and a second mode, in the first mode, when a power supply capacity supplied from the backup power supply is less than a first value, the controller changes a size of data storable in the volatile memory, and when the power supply capacity is less than a second value, transmits information indicating the power supply capacity to an external device, wherein the second value is less than the first value, and in the second mode, when the power supply capacity is less than a third value, the controller transmits information indicating the power supply capacity to the external device, wherein the third value is less than the second value.

22. The storage system according to claim 21, wherein The backup power supply circuit includes a plurality of capacitors, and the power supply capacity corresponds to an electrostatic capacity charged by the plurality of capacitors.

23. The storage system according to claim 21, wherein The controller receives a mode designation signal for designating one of the first mode and the second mode from the external device.

24. The storage system according to claim 21, wherein When the power supply capacity is smaller than the first value, the controller writes first data among data stored in the volatile memory to the non-volatile memory, and reduces a size of the data storable in the volatile memory by a size of the first data.

25. The storage system according to claim 21, wherein When the first voltage is smaller than the first level without receiving a power-off command from an external device, the power supply circuit supplies a voltage corresponding to an output voltage of the backup power supply circuit to the non-volatile memory, the volatile memory, and the controller.

26. A control method of a storage system, The storage system includes: a non-volatile memory; a volatile memory; a controller that controls writing of data to the non-volatile memory and writing of data to the volatile memory; a power supply circuit that is connected to the non-volatile memory, the volatile memory, and the controller, and generates a plurality of voltages using a first voltage supplied from the outside; a backup power supply circuit that is charged using one of the plurality of voltages; and a measurement circuit that measures a power supply capacity fed from the backup power supply circuit, The method includes: generating the plurality of voltages using an output voltage from the backup power supply circuit by the power supply circuit when the first voltage is not reduced due to a power-off command; supplying the plurality of voltages to the non-volatile memory, the volatile memory, and the controller; and changing a size of data storable in the volatile memory in accordance with the power supply capacity, When the power supply capacity is smaller than a first value, the controller writes first data among data stored in the volatile memory to the non-volatile memory, and reduces a size of the data storable in the volatile memory by a size of the first data. ​

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