Backside illuminated image sensor and method of forming the same

Abstract

The application provides a back-illuminated image sensor and a forming method thereof. The back-illuminated image sensor comprises a plurality of first isolation structures extending into a semiconductor substrate from a first surface and having a first opening extending from a top of the first isolation structure into the first isolation structure; a first epitaxial layer covering a sidewall and a bottom of the first opening; and a grid structure comprising a first grid part and a second grid part connected in sequence. The first epitaxial layer is formed by a low-temperature epitaxial process, avoiding the influence of a high-temperature process on the first isolation structure. The first grid part is arranged on the first epitaxial layer and fills the first opening. The second grid part extends along a top of the first grid part and covers the first opening. Color filters and microlenses are embedded between adjacent second grid parts, avoiding crosstalk effects and improving the performance of the back-illuminated image sensor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a back-illuminated image sensor and a forming method thereof. BACKGROUND

[0002] At present, CMOS image sensors have been widely applied to static digital cameras, photographic mobile phones, digital video cameras, medical camera devices (such as gastroscopes), vehicle camera devices, etc. CMOS image sensor products can be divided into FSI (Front Side Illumination) and BSI (Back Side Illumination).

[0003] The back-illuminated image sensor has superior performance and thus has been widely applied, but the existing back-illuminated image sensor adopts an HfO2 layer as a pin (pinned layer) of a light-in surface, and utilizes the negative charge of the HfO2 to induce a positive charge on the surface of the back-illuminated image sensor to pin the surface, but there is a problem of insufficient pin capacity. SUMMARY

[0004] The present application aims to provide a back-illuminated image sensor and a forming method thereof. On the one hand, in order to solve the problem of insufficient pin capacity of HfO2, a structure of a BSI surface pinned layer and a forming method thereof are provided. On the other hand, a new structure of DTI (deep trench isolation) and Metal Grid (metal grid) and a forming method thereof are provided. The photosensitivity and relative luminance of the back-illuminated image sensor are better, the crosstalk between pixels is smaller, and the process is more stable.

[0005] Based on the above considerations, the present application provides a back-illuminated image sensor in a first aspect, comprising: a semiconductor substrate having opposite first and second surfaces; a plurality of first isolation structures extending into the semiconductor substrate from the first surface and having a first opening extending from a top of the first isolation structure into the first isolation structure; a plurality of light sensing units including photodiodes, each of the photodiodes being arranged side by side between adjacent first isolation structures; a first epitaxial layer covering a sidewall and a bottom of the first opening; and a grid structure including a first grid portion and a second grid portion connected in sequence; wherein the first grid portion is arranged on the first epitaxial layer and fills the first opening; and the second grid portion extends along a top of the first grid portion and covers the first opening.

[0006] Preferably, the top of the first grid portion is higher than or flush with a top surface of the first epitaxial layer relative to the first surface.

[0007] Preferably, the first epitaxial layer further extends longitudinally along a sidewall of the first opening.

[0008] Preferably, the sidewall of the second grid portion is flush with the sidewall of the first opening.

[0009] Preferably, further comprising: a second epitaxial layer covering the first surface and laterally connecting the first epitaxial layer along the first surface.

[0010] Preferably, the top surface of the second epitaxial layer is higher than or flush with the top of the first grid portion relative to the first surface.

[0011] Preferably, further comprising: a first dielectric layer covering the first epitaxial layer along the sidewall and the bottom of the first opening, and / or a second dielectric layer covering the second epitaxial layer along the first surface.

[0012] Preferably, the second dielectric layer laterally connects the first dielectric layer along the surface of the second epitaxial layer.

[0013] The second aspect of the present application provides a method for forming a back-illuminated image sensor, comprising: providing a semiconductor substrate having opposite first and second surfaces; forming a plurality of first isolation structures, each of the first isolation structures extending into the semiconductor substrate from the second surface; forming a plurality of light sensing units in the semiconductor substrate, each of the light sensing units comprising a plurality of photodiodes arranged side by side between adjacent ones of the first isolation structures; forming a mask layer covering the first surface and the first isolation structures; etching the mask layer and the first isolation structures to form a second opening and a first opening connected in series, the second opening penetrating through the mask layer, and the first opening extending into the first isolation structures from a bottom of the second opening; forming a first epitaxial layer covering the sidewall and the bottom of the first opening by a first epitaxial process; sequentially filling the second opening and the first opening to form a first grid portion and a second grid portion connected in series to form a grid structure; and removing the mask layer.

[0014] Preferably, a lateral dimension of the first opening is less than or equal to a lateral dimension of the second opening.

[0015] Preferably, after the mask layer is removed, the method further comprises: forming a second epitaxial layer covering the first surface by a second epitaxial process.

[0016] Preferably, the first epitaxial process and the second epitaxial process are both at a process temperature not higher than 500 °C.

[0017] Preferably, the first epitaxial process and the second epitaxial process both comprise a low-temperature epitaxial process.

[0018] Preferably, the thickness of the second epitaxial layer is greater than or equal to the vertical distance between the top surface of the first epitaxial layer and the first surface.

[0019] Preferably, both the first epitaxial layer and the second epitaxial layer are 0.05μm~0.1μm.

[0020] Preferably, the semiconductor substrate includes a single-crystal silicon substrate, and the materials of the first epitaxial layer and the second epitaxial layer include one or a combination of silicon and germanium.

[0021] Preferably, the materials of the first grid portion and the second grid portion include one or more combinations of amorphous silicon, polycrystalline silicon, and metallic materials.

[0022] Preferably, before sequentially filling the second opening and the first opening to form the first grid portion and the second grid portion connected vertically to form a grid structure, the method further includes: forming a first dielectric layer covering the first epitaxial layer, wherein the material of the first dielectric layer includes a high-k material.

[0023] Preferably, after forming the second epitaxial layer on the first surface, the method further includes forming a second dielectric layer covering the second epitaxial layer, wherein the material of the second dielectric layer includes a high-k material.

[0024] Preferably, after forming the second epitaxial layer on the first surface, the method further includes: sequentially forming a color filter and a microlens on the second epitaxial layer.

[0025] The grid structure of this invention includes a first grid portion and a second grid portion connected vertically. The first epitaxial layer and / or the second epitaxial layer are formed by a low-temperature epitaxial process, avoiding the influence of high-temperature processes on the first isolation structure and simultaneously forming good electrical isolation to prevent electrical crosstalk between adjacent photosensitive units. The first grid portion is disposed on the first epitaxial layer and fills the first opening. The second grid portion extends along the top of the first grid portion and covers the first opening. Color filters and microlenses are embedded between adjacent second grid portions to avoid crosstalk effects and improve the performance of the back-illuminated image sensor. Attached Figure Description

[0026] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.

[0027] Figure 1 A flowchart illustrating a method for forming a back-illuminated image sensor according to an embodiment of the present invention;

[0028] Figure 2 - Figure 6This is a schematic diagram illustrating the process of forming an image sensor chip according to Embodiment 1 of the present invention.

[0029] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation

[0030] To make the content of this invention clearer and easier to understand, the following description, in conjunction with the accompanying drawings, further illustrates the invention. Of course, this invention is not limited to this specific embodiment, and common substitutions well-known to those skilled in the art are also covered within the scope of protection of this invention.

[0031] It should be noted that in the following specific embodiments, in order to clearly illustrate the structure of the present invention and facilitate explanation, the structure in the accompanying drawings is not drawn to scale and has been partially enlarged, deformed and simplified. Therefore, it should be avoided to interpret this as a limitation of the present invention.

[0032] Figure 1 A flowchart illustrating a method for forming a back-illuminated image sensor according to an embodiment of the present invention; Figure 2 - Figure 6 This is a schematic diagram illustrating the process of forming an image sensor chip according to Embodiment 1 of the present invention. In the following example, one photosensitive unit is shown; however, those skilled in the art will understand that the number of photosensitive units can be set as needed, and the embodiments of this disclosure are not limited in this respect.

[0033] See Figure 1 , Figure 1 A flowchart illustrating a method for forming a back-illuminated image sensor according to an embodiment of the present invention is shown. Figure 1 A total of 8 steps are shown:

[0034] Step S01: Provide a semiconductor substrate 100, the semiconductor substrate 100 having opposing first surfaces 101 and second surfaces 102.

[0035] Step S02: Form a plurality of first isolation structures 111, each of the first isolation structures 111 extending from the first surface 101 into the semiconductor substrate 100.

[0036] Step S03: A plurality of photosensitive units are formed in the semiconductor substrate 100, each photosensitive unit including a photodiode, and each photodiode is arranged side by side between adjacent first isolation structures 111.

[0037] Please refer to the reference. Figure 2The semiconductor substrate 100 may be a monolithic semiconductor material (such as silicon or germanium), or a silicon-on-insulator substrate or a germanium-on-insulator substrate. Preferably, the semiconductor substrate 100 may also be a lightly doped semiconductor substrate 100.

[0038] In this embodiment, the semiconductor substrate 100 is a single-crystal silicon substrate. Depending on the type of photosensitive unit of the back-illuminated image sensor, the semiconductor substrate 100 may also be doped with different types of impurity ions.

[0039] Specifically, when the photosensitive unit of the back-illuminated image sensor is of type N, the semiconductor substrate 100 is doped with P-type impurity ions, wherein the P-type impurity ions are one or more of boron ions, gallium ions, or indium ions; or, when the photosensitive unit of the back-illuminated image sensor is of type P, the semiconductor substrate 100 is doped with N-type impurity ions, wherein the N-type impurity ions are phosphorus ions. Deep well implantation is achieved by ion implantation into the semiconductor substrate 100. As a non-limiting example, the doping concentration of the semiconductor substrate 100 can be 1E15 atom / cm³. 3 Up to 2.5E15atom / cm 3 .

[0040] The back-illuminated image sensor includes a plurality of first isolation structures 111, which extend from the first surface 101 into the semiconductor substrate 100. In this embodiment, the back-illuminated image sensor further includes a second isolation structure 112, which corresponds to each of the first isolation structures 111 and extends from the second surface 102 into the semiconductor substrate 100. The bottom of the second isolation structure 112 is connected to the bottom of the deep trench isolation structure 111, forming a trench region penetrating the semiconductor substrate 100. The trench is located on both sides of each photosensitive unit, or surrounds the photosensitive unit, to isolate adjacent photosensitive units and avoid signal crosstalk.

[0041] A plurality of photosensitive units are arranged side-by-side within the semiconductor substrate 100. Each photosensitive unit includes a photodiode. The photodiodes are arranged side-by-side and positioned between adjacent first isolation structures 111 and corresponding second isolation structures 112. Light is incident on each photodiode from the first surface 101. Each photodiode senses the light and generates photogenerated carriers. In this embodiment, the photodiode includes a deeply doped region 131 and a shallowly doped region 132 stacked vertically. Ion implantation is performed on the second surface 102 of the semiconductor substrate 100 to sequentially form the deeply doped region 131 and the shallowly doped region 132 within the semiconductor substrate 100.

[0042] The deep doped region 131 and the shallow doped region 132 have the same doping type, and are both opposite to the doping type of the semiconductor substrate 100. If the semiconductor substrate 100 is N-type doped, the dopant ions in the deep doped region 131 and the shallow doped region 132 are P-type ions, such as B; conversely, if the semiconductor substrate 100 is P-type doped, the dopant ions in the deep doped region 131 and the shallow doped region 132 are N-type ions, such as P or As. Typically, the semiconductor substrate 100 is set to P-type doping, and the deep doped region 131 and the shallow doped region 132 are set to N-type doping.

[0043] Specifically, the dopant ions in the deep doped region 131 and the shallow doped region 132 can be arsenic, the implantation energy of the deep doped region 131 can be from 1000 keV to 2000 keV, and the doping dose of the deep doped region 131 can be 1 E12 atom / cm 3 Up to 1E13atom / cm 3 The dopant ions in the shallow doped region 132 can be arsenic, and the implantation energy of the shallow doped region 132 can be from 100 keV to 1000 keV. The maximum implantation energy of the shallow doped region 132 is less than the maximum implantation energy of the deep doped region 131. The doping dose of the shallow doped region 132 can be 1 E12 atom / cm. 3 Up to 1E13atom / cm 3 In specific implementations, the doping dose of the shallow doped region 132 can be set to be the same as that of the deep doped region 131. Those skilled in the art will understand that, since the deep doped region 131 is deeper than the shallow doped region 132 relative to the second surface 102, a stepped implantation energy can be used to perform ion implantation on the semiconductor substrate 100, thereby achieving uniform doping of the deep doped region 131.

[0044] like Figure 2 As shown, in this embodiment, the lateral dimension of the deeply doped region 131 is smaller than the lateral dimension of the shallowly doped region 132. In another embodiment, the lateral dimension of the deeply doped region 131 is smaller than the lateral dimension of the shallowly doped region 132 and is located on both sides of the bottom of the shallowly doped region 132 to improve the carrier depletion rate in the central region of the photodiode, thereby improving the output image quality. Of course, the lateral dimension of the deeply doped region 131 should not be too narrow, otherwise the improvement in full-well capacity will be limited and it will be difficult to meet the improvement requirements. As a non-limiting example, the total lateral width of the deeply doped regions 131 on both sides of the bottom of the shallowly doped region 132 can account for 50% to 80% of the lateral dimension of the shallowly doped region 132, which can achieve a balance between improving the output image quality and improving the full-well capacity of the photodiode.

[0045] In this embodiment, the photosensitive unit further includes a corresponding floating diffusion region 113, such as... Figure 2 As shown, the floating diffusion region 113 extends from the second surface 102 into the second isolation structure 112 on the corresponding photodiode side. The doping type of the floating diffusion region 113 is different from the doping type of the semiconductor substrate 100. The photocharge generated by the photodiode flows to the floating diffusion region 113 and is read out. The method for forming the floating diffusion region 113 is, for example, to perform doping at a predetermined depth on the second surface 102 of the semiconductor substrate 100. In some embodiments of this application, when the semiconductor substrate 100 is P-type doped, the floating diffusion region 113 is N-type doped. When performing the floating diffusion region 113 doping process, the energy range for N-type doping is 50 KeV to 150 KeV, and the dopant ion concentration is 1 E15 atom / cm³. 3 Up to 5E15atom / cm 3 The dopant ion in the floating diffusion region 113 can be phosphorus, the doping energy in the floating diffusion region 113 can be from 1 keV to 100 keV, and the doping dose in the floating diffusion region 113 can be 1 E15 atom / cm. 3 Up to 1E16atom / cm 3 .

[0046] like Figure 2 As shown, the photosensitive unit further includes a transmission gate structure 114 disposed on the second surface 102, comprising a gate dielectric layer (not shown) and a gate (not shown) located on the gate dielectric layer. In addition, a source (not shown) and a drain (not shown) are formed in the semiconductor substrate 100; for simplicity, the source and drain are not shown in the figure. The transmission gate structure 114 acts as a switch on the photocharge transport channel, used to control the movement of the photocharge from the photodiode to the floating diffusion region.

[0047] Those skilled in the art will understand that the process for forming the transmission gate structure 114 includes, for example, sequentially forming a gate dielectric layer material and a gate material on the surface of a semiconductor substrate 100, and then etching the gate material and the gate dielectric layer material under the protection of a mask to form the transmission gate structure 114. The gate dielectric layer material is silicon oxide or a composite material layer including a silicon oxide layer. Those skilled in the art will also understand that the transmission gate structure 114 may further include sidewalls located on the gate dielectric layer and the gate sidewalls. The sidewalls may be silicon oxide or a composite structure including silicon oxide. The process for forming the sidewalls includes covering the surface of the semiconductor substrate 100, the gate dielectric layer, the gate top, and the sidewalls with a sidewall material layer including silicon oxide, and etching away the sidewall material layer located on the surface of the semiconductor substrate 100 to form the sidewalls.

[0048] The process of forming the first isolation structure 111 and / or the second isolation structure 112, the photodiode, the floating diffusion region 113, and the transmission gate structure 114 includes multiple process steps of ion implantation, photolithography, resist removal, and / or deposition and removal of oxide layers on the first surface 101 and the second surface 102 of the semiconductor substrate 100. The above process steps are known to those skilled in the art and will not be described in detail here.

[0049] like Figure 2 As shown, a pinning layer 115 is also formed within the semiconductor substrate 100. The pinning layer 115 extends from the second surface 102 into the semiconductor substrate 100, at least partially covering the photodiode, and is located away from the floating diffusion region 113 and the corresponding second isolation structure 112. In another embodiment, the pinning layer 115 further extends along the second surface 102 into the second isolation structure 112, away from the floating diffusion region 113. The pinning layer 115 has the opposite doping type to the photodiode, that is, the same doping type as the semiconductor substrate 100.

[0050] Specifically, the dopant ions of the pinning layer 115 can be boron, the doping energy of the pinning layer 115 can be from 1 keV to 50 keV, and the doping dose of the pinning layer 115 can be 1 E13 atom / cm 3 Up to 1E14atom / cm 3 The pinning layer 115 partially corresponds to the photodiode and has good conductivity. When the back-illuminated image sensor is working, the pinning layer 115 is connected to a negative voltage, attracting holes to the second surface 102 corresponding to the position of the pinning layer 115 to form a hole accumulation layer, so that it cannot hinder the operation of photoelectrons, reduce dark current, and thus improve quantum efficiency.

[0051] Step S04: Form a mask layer 121 covering the first surface 101 and the first isolation structure 111.

[0052] Step S05: Etch the mask layer 121 and the first isolation structure 111 to form a second opening 122 and a first opening 123 that are connected vertically. The second opening 122 penetrates the mask layer 121, and the first opening 123 extends from the bottom of the second opening 122 into the first isolation structure 111.

[0053] like Figure 3 As shown, the mask layer 121 can be formed by methods such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), etc. For example, the thickness of the mask layer 121 is 500 angstroms to 800 angstroms.

[0054] The mask layer 121 and the first isolation structure 111 are patterned using photolithography, etching and other processes to define the position and size of the second opening 122 and the first opening 123.

[0055] Specifically, a patterned photoresist layer (not shown) covering the mask layer 121 is first formed. Then, using the patterned photoresist layer as a mask, the mask layer 121 and the first isolation structure 111 are etched by a suitable dry or wet etching process. The wet etching process includes wet etching processes such as a mixture of nitric acid and hydrofluoric acid. The dry etching process includes, but is not limited to, reactive ion etching (RIE), ion beam etching, and plasma etching.

[0056] The second opening 122 and the first opening 123 can be formed simultaneously or sequentially. In one embodiment, the patterned photoresist layer is first used as a mask to etch the mask layer 121 to form the second opening 122, exposing a portion of the first isolation structure 111 at the bottom of the second opening 122. Then, the patterned photoresist layer is removed. Next, the mask layer 121 is used as a mask to etch the exposed first isolation structure 111 at the bottom of the second opening 122 to form the first opening 123, and the lateral dimension of the first opening 123 is smaller than the lateral dimension of the second opening 122. In another embodiment, the second opening 122 and the first opening 123 are formed simultaneously, and the lateral dimension of the first opening 123 is equal to the lateral dimension of the second opening 122.

[0057] In some embodiments, both the second opening 122 and the first opening 123 have a trapezoidal cross-section. In a particular embodiment, both the second opening 122 and the first opening 123 have a rectangular cross-section. The second opening 122 and the first opening 123 can be arranged periodically. Depending on the requirements of the back-illuminated image sensor, the spacing between the second opening 122 and the first opening 123, as well as the depth and lateral dimensions of the second opening 122 and the first opening 123, can be modified.

[0058] Step S06: Using a first epitaxial process, a first epitaxial layer 124 is formed covering the sidewalls and bottom of the first opening 123.

[0059] like Figure 4 As shown, since the first surface 101 is covered with a mask layer, a first epitaxial layer 124 is formed on the surface of the deep trench structure exposed on the sidewall and bottom of the first opening 123 using a first epitaxial process.

[0060] In this embodiment, since several photosensitive units have been formed within the semiconductor substrate 100, to avoid the impact of high-temperature processing on the performance of the photodiode and other devices, the process temperature of the first epitaxial process is no higher than 500°C. Preferably, a low-temperature epitaxial process can be used to form the first epitaxial layer 124. The low-temperature epitaxial process includes a hot-wire CVD process. In one embodiment, the first epitaxial layer 124 is formed on a single-crystal substrate using a hot-wire CVD process. The process temperature of the hot-wire CVD process is less than or equal to 300°C. Preferably, the process temperature of the hot-wire CVD process is equal to 200°C. In this embodiment, the semiconductor substrate 100 is a single-crystal silicon substrate. The deep trench structure dops the single-crystal silicon substrate. The hot-wire CVD process forms intrinsic silicon on the surface of the deep trench structure exposed on the sidewalls and bottom of the first opening 123. The intrinsic silicon is the first epitaxial layer 124 with a crystal quality approximately equivalent to a bulk single-crystal orientation.

[0061] The thickness of the first epitaxial layer 124 is adjusted by regulating the process time of the first epitaxial process. For example... Figure 4 As shown, since the low-temperature epitaxial process is anisotropic epitaxy, the first epitaxial layer 124 also extends longitudinally along the sidewall of the first opening 123. The top surface of the first epitaxial layer 124 is higher than the first surface 101, which facilitates connection with the subsequently formed second epitaxial layer 125.

[0062] Step S07: Sequentially fill the second opening 122 and the first opening 123 to form the first grid part 141 and the second grid part 142 connected vertically to form a grid structure 140.

[0063] like Figure 5As shown, the first grid portion 141 is disposed on the first epitaxial layer 124 and fills the first opening 123; the second grid portion 142 covers the top of the first grid portion 141 and extends along the top of the first grid portion 141 to cover the first epitaxial layer 124, so as to completely cover the first opening 123. The first grid portion 141 and the second grid portion 142 are stacked vertically to form a grid structure 140. In this embodiment, the first epitaxial layer 124 also extends longitudinally along the sidewall of the first opening 123. The top of the first grid portion 141 is flush with the top surface of the first epitaxial layer 124 and is higher than the first surface 101, the top surface of the deep trench structure, and the top of the first opening 123. The second grid portion 142 fills the second opening 122 along the sidewall of the second opening 122, and its bottom surface covers the first grid portion 141 and the first epitaxial layer 124, and its sidewall is flush with the sidewall of the first opening 123 and the first epitaxial layer 124. The materials of the first grid portion 141 and the second grid portion 142 may be the same or different. The materials of the first grid portion 141 and the second grid portion 142 include one or more combinations of amorphous silicon, polycrystalline silicon, doped polycrystalline silicon, and metal materials. The metal material may be a pure metal or a metal alloy, such as tungsten or aluminum-copper alloy, preferably tungsten, molybdenum, or other metal materials with heat resistance, corrosion resistance, and wear resistance.

[0064] In another embodiment, before sequentially filling the first opening 123 and the second opening 122 to form the vertically connected first grid portion 141 and second grid portion 142 to form the grid structure 140, a first dielectric layer covering the first epitaxial layer 124 is also formed. The material of the first dielectric layer includes one or more combinations of high-k materials, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride to reduce dark current and signal delay. The first dielectric layer can effectively block light diffusion to adjacent photosensitive units to improve the quantum efficiency of the back-illuminated image sensor, while crosstalk effect and image quality are also greatly improved. The first dielectric layer covers the first epitaxial layer 124.

[0065] Specifically, the first epitaxial layer 124 and the first dielectric layer are formed sequentially from the sidewall and bottom of the first opening 123. The first dielectric layer covers the first epitaxial layer 124 along the sidewall and bottom of the first opening 123. The vertical distance between the top surface of the first dielectric layer and the first surface 101 is greater than or equal to the thickness of the first dielectric layer. Then, the first grid portion 141 and the second grid portion 142 are formed. The top surface of the first dielectric layer and the top surface of the first grid portion 141 are flush with each other and both exceed the top surface of the first epitaxial layer 124, the first surface 101, the top of the deep trench structure, and the top of the first opening 123. The top of the grid structure 140 exceeds the first surface 101 to absorb scattered or reflected light incident on the photosensitive unit, thereby concentrating the light and reducing or eliminating optical crosstalk.

[0066] After forming the first grid portion 141 and the second grid portion 142 connected vertically, the mask layer and the second grid portion 142 can be ground by chemical mechanical polishing (CMP) to ensure the flatness of the second grid portion 142.

[0067] Step S08: Remove the mask layer 121.

[0068] like Figure 6As shown, corresponding to the first epitaxial layer 124, in this embodiment, after removing the mask layer 121, a second epitaxial process is used to form a second epitaxial layer 125 on the first surface 101. Similar to the first epitaxial layer 124, the process temperature of the second epitaxial process is no higher than 500°C and includes a low-temperature epitaxial process. The thickness of the second epitaxial layer 125 is adjusted by regulating the process time of the second epitaxial process. In this embodiment, both the first epitaxial layer 124 and the second epitaxial layer 125 are formed using a low-temperature epitaxial process including hot-wire CVD. The thickness of both the first epitaxial layer 124 and the second epitaxial layer 125 is 0.05μm to 0.1μm. The thickness of the second epitaxial layer 125 is greater than or equal to the vertical distance between the top surface of the first epitaxial layer 124 and the first surface 101. In this embodiment, the first epitaxial layer 124 extends longitudinally along the sidewall of the first opening 123. The thickness of the second epitaxial layer 125 is equal to the thickness of the first epitaxial layer 124, and the thickness of the second epitaxial layer 125 is equal to the vertical distance between the top surface of the first epitaxial layer 124 and the first surface 101. The top surface of the second epitaxial layer 125 is flush with the top surface of the first epitaxial layer 124 and the top of the first grid portion 141, and is laterally connected to the first epitaxial layer 124 along the first surface 101. Preferably, the thickness of the second epitaxial layer 125 is greater than the vertical distance between the top surface of the first epitaxial layer 124 and the first surface 101 to ensure that the side surface of the second epitaxial layer 125 is sufficiently connected to the side surface of the first epitaxial layer 124.

[0069] In one embodiment, corresponding to the first dielectric layer, after forming the second epitaxial layer 125, a second dielectric layer (not shown) is formed on the surface of the second epitaxial layer 125. The vertical distance between the top surface of the second epitaxial layer 125 and the first surface 101 is less than the vertical distance between the top surface of the first dielectric layer and the first surface 101. The second dielectric layer covers the surface of the second epitaxial layer 125 and is laterally connected to the first dielectric layer. The material of the second dielectric layer includes one or more combinations of high-k materials, silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride.

[0070] Finally, a color filter (not shown) and a microlens (not shown) are sequentially formed on the second epitaxial layer 125. Since the hard film layer is formed on the first surface 101, the second grid portion 142 fills the opening of the hard film layer, thus forming a groove between adjacent second grid portions 142. The bottom of the groove is the second epitaxial layer 125 and / or the second dielectric layer. The color filter and the microlens are embedded in the groove, ultimately forming an embedded color filter and / or microlens. The second grid portion 142 isolates adjacent photosensitive units, avoiding crosstalk effects and improving the performance of the back-illuminated image sensor.

[0071] The grid structure 140 of the present invention includes a first grid portion 141 and a second grid portion 142 connected vertically. A first epitaxial layer 124 and / or a second epitaxial layer 125 formed by a low-temperature epitaxial process avoids the influence of high-temperature processes on the first isolation structure 111, while simultaneously forming good electrical isolation to prevent electrical crosstalk between adjacent photosensitive units. The first grid portion 141 is disposed on the first epitaxial layer 124 and fills the first opening 123; the second grid portion 142 extends along the top of the first grid portion 141 and covers the first opening 123. Color filters and microlenses are embedded between adjacent second grid portions 142 to avoid crosstalk effects and improve the performance of the back-illuminated image sensor.

[0072] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plurality. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for forming a back-illuminated image sensor, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having opposing first and second surfaces; A plurality of first isolation structures are formed, each of the first isolation structures extending from the first surface into the semiconductor substrate; A plurality of photosensitive units are formed in the semiconductor substrate, each photosensitive unit including a photodiode, and each photodiode is arranged side by side between adjacent first isolation structures; A mask layer is formed covering the first surface and the first isolation structure; The mask layer and the first isolation structure are etched to form a second opening and a first opening that are connected vertically. The second opening penetrates the mask layer, and the first opening extends from the bottom of the second opening into the first isolation structure. A first epitaxial layer is formed by using a first epitaxial process to cover the sidewalls and bottom of the first opening; The second opening and the first opening are filled in sequence to form a first grid section and a second grid section connected vertically to form a grid structure; Remove the mask layer.

2. The method for forming a back-illuminated image sensor according to claim 1, characterized in that, The lateral dimension of the first opening is less than or equal to the lateral dimension of the second opening.

3. The method for forming a back-illuminated image sensor according to claim 1, characterized in that, After removing the mask layer, the process further includes: using a second epitaxial process to form a second epitaxial layer covering the first surface.

4. The method for forming a back-illuminated image sensor according to claim 3, characterized in that, The process temperatures of both the first epitaxial process and the second epitaxial process are not higher than 500℃.

5. The method for forming a back-illuminated image sensor according to claim 4, characterized in that, Both the first epitaxial process and the second epitaxial process include low-temperature epitaxial processes.

6. The method for forming a back-illuminated image sensor according to claim 3, characterized in that, The thickness of the second epitaxial layer is greater than or equal to the vertical distance between the top surface of the first epitaxial layer and the first surface.

7. The method for forming a back-illuminated image sensor according to claim 6, characterized in that, Both the first epitaxial layer and the second epitaxial layer are 0.05μm~0.1μm.

8. The method for forming a back-illuminated image sensor according to any one of claims 3 to 7, characterized in that, The semiconductor substrate includes a single-crystal silicon substrate, and the materials of the first epitaxial layer and the second epitaxial layer include one or a combination of silicon and germanium.

9. The method for forming a back-illuminated image sensor according to claim 8, characterized in that, The materials of the first grid section and the second grid section include one or more combinations of amorphous silicon, polycrystalline silicon, and metallic materials.

10. The method for forming a back-illuminated image sensor according to claim 1, characterized in that, Before sequentially filling the second opening and the first opening to form the first grid portion and the second grid portion connected vertically to form a grid structure, the method further includes: forming a first dielectric layer covering the first epitaxial layer, wherein the material of the first dielectric layer includes a high-k material.

11. The method for forming a back-illuminated image sensor according to claim 3, characterized in that, After forming the second epitaxial layer on the first surface, the method further includes forming a second dielectric layer covering the second epitaxial layer, wherein the material of the second dielectric layer includes a high-k material.

12. The method for forming a back-illuminated image sensor according to claim 11, characterized in that, After the second epitaxial layer is formed on the first surface, the method further includes: sequentially forming a color filter and a microlens on the second epitaxial layer.

13. A back-illuminated image sensor, characterized in that, It is formed using the method for forming a back-illuminated image sensor as described in any one of claims 1 to 12.

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