Metal oxide semiconductor field effect transistor and method of making the same

Abstract

The embodiment of the present application provides a MOSFET and a manufacturing method thereof, wherein the MOSFET comprises at least one transistor unit, and the at least one transistor unit comprises: a drift region (20); a first trench (110) formed on a first surface (201) of the drift region (20); a first polysilicon layer (222) and a second polysilicon layer (42) formed by ion implantation on a first surface (2201) of polysilicon (22) filled in the first trench (110). The MOSFET and the manufacturing method thereof provided by the embodiment of the present application design a MOSFET integrated with a HJD and a VU-MOSFET in a single chip, and the manufacturing difficulty is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a metal oxide semiconductor field effect transistor (MOSFET) and a manufacturing method thereof. BACKGROUND

[0002] The parasitic diode of a conventional vertical trench metal oxide semiconductor field effect transistor (VU-MOSFET) has a high turn-on voltage, a slow reverse recovery speed, and a large switching loss during freewheeling. A common solution is to integrate a Schottky diode (SBD) in parallel.

[0003] However, this solution must control the temperature to form a satisfactory Schottky junction to balance the leakage current and the on-voltage of the body diode, and it is necessary to form the SBD on the trench sidewall, which all bring difficulties to actual manufacturing. SUMMARY

[0004] Embodiments of the present application provide a MOSFET and a manufacturing method thereof, which are used to solve the technical problem of difficulty in manufacturing a MOSFET in the prior art.

[0005] In a first aspect, embodiments of the present application provide a MOSFET, comprising at least one transistor unit, wherein the at least one transistor unit comprises:

[0006] a drift region;

[0007] a first trench formed on a first surface of the drift region;

[0008] a first polysilicon layer and a second polysilicon layer formed by ion implantation on a first surface of the polysilicon filled in the first trench.

[0009] In some embodiments, the at least one transistor unit further comprises:

[0010] a second trench formed on the first surface of the drift region;

[0011] a gate oxide layer formed on the sidewall and the bottom of the second trench, the thickness of the gate oxide layer being suitable for the size of the second trench, so that a first remaining trench is reserved after the gate oxide layer is formed;

[0012] a third polysilicon layer formed on the bottom of the first remaining trench, the thickness of the third polysilicon layer being suitable for the size of the first remaining trench, so that a second remaining trench is reserved after the third polysilicon layer is formed;

[0013] a fourth polysilicon layer filled in the second remaining trench.

[0014] In some embodiments, the at least one transistor unit further comprises:

[0015] a gate formed above a first surface of the fourth polysilicon layer.

[0016] In some embodiments, the at least one transistor cell further comprises:

[0017] a glass layer covering the gate.

[0018] In some embodiments, the at least one transistor cell further comprises:

[0019] a P-well region formed by ion implantation at the first surface of the drift region and a P + region formed by ion implantation at the first surface of the P-well region.

[0020] In some embodiments, the at least one transistor cell further comprises:

[0021] a P-base formed by ion implantation at the first surface of the drift region.

[0022] In some embodiments, the at least one transistor cell further comprises:

[0023] a source region formed by ion implantation at the first surface of the P-base.

[0024] In some embodiments, the at least one transistor cell further comprises:

[0025] a source formed above a first surface of the second polysilicon layer.

[0026] In some embodiments, the at least one transistor cell further comprises:

[0027] a drain;

[0028] a substrate;

[0029] a buffer region;

[0030] the substrate is arranged between the drain and the buffer region;

[0031] the buffer region is arranged between the substrate and the drift region.

[0032] In a second aspect, embodiments of the present application provide a method for fabricating a MOSFET, comprising:

[0033] forming a first trench at a first surface of the drift region;

[0034] filling the first trench with polysilicon;

[0035] forming a first polysilicon layer and a second polysilicon layer from the first surface of the polysilicon by ion implantation.

[0036] The MOSFET and the manufacturing method thereof provided by the embodiment of the present application, a MOSFET integrated with a heterojunction diode (HJD) and a VU-MOSFET is designed, the turn-on voltage and the dead time of the diode during freewheeling are reduced, the reverse recovery speed and the reverse recovery charge are faster, the current peak caused by the MOSFET opening is smaller, and the manufacturing difficulty is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 A structure schematic diagram of a MOSFET provided by the embodiment of the present application is provided;

[0038] Figure 2 A structure schematic diagram of a MOSFET provided by the embodiment of the present application is provided;

[0039] Figure 3 A structure schematic diagram of a MOSFET provided by the embodiment of the present application is provided;

[0040] Figure 4 A structure schematic diagram of a MOSFET provided by the embodiment of the present application is provided;

[0041] Figure 5 A structure schematic diagram of a MOSFET provided by the embodiment of the present application is provided;

[0042] Figure 6 A structure schematic diagram of a MOSFET provided by the embodiment of the present application is provided;

[0043] Figure 7 A structure schematic diagram of a MOSFET provided by the embodiment of the present application is provided;

[0044] Figure 8 A structure schematic diagram of a MOSFET provided by the embodiment of the present application is provided;

[0045] Figure 9 A structure schematic diagram of a MOSFET provided by the embodiment of the present application is provided;

[0046] Figure 10 A structure schematic diagram of a MOSFET provided by the embodiment of the present application is provided;

[0047] Figure 11 A structure schematic diagram of a MOSFET provided by the embodiment of the present application is provided;

[0048] Figure 12 Fig. 10 is a structural schematic diagram of a MOSFET in a process of manufacturing the MOSFET according to an embodiment of the present application;

[0049] Figure 13 Fig. 11 is a structural schematic diagram of a MOSFET in a process of manufacturing the MOSFET according to an embodiment of the present application;

[0050] Figure 14 Fig. 12 is a structural schematic diagram of a MOSFET in a process of manufacturing the MOSFET according to an embodiment of the present application;

[0051] Figure 15 Fig. 13 is an equivalent circuit schematic diagram of a MOSFET according to an embodiment of the present application;

[0052] Figure 16 Fig. 14 is a band structure schematic diagram of an HJD in a MOSFET according to an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0054] Figure 1 Fig. 1 is a structural schematic diagram of a MOSFET according to an embodiment of the present application, as shown in the figure, the MOSFET according to the embodiment of the present application comprises at least one transistor unit, and the at least one transistor unit comprises: Figure 1

[0055] a drift region 20;

[0056] a first trench 110 formed on a first surface 201 of the drift region 20;

[0057] a first polysilicon layer 222 and a second polysilicon layer 42 formed by ion implantation on a first surface 2201 of the polysilicon 22 filled in the first trench 110.

[0058] Specifically, the drift region 20 can comprise N - type silicon carbide (SiC).

[0059] The polysilicon 22 can be deposited in the first trench 110, and the polysilicon 22 is filled in the first trench 110.

[0060] ​The polysilicon 22 can be P - The polysilicon (P - -poly).

[0061] The first polysilicon layer 222 formed by ion implantation on the first surface 2201 of the polysilicon 22, and the second polysilicon layer 42, the first polysilicon layer 222 formed includes P - -poly, and the second polysilicon layer 42 formed includes N + The polysilicon (N + -poly).

[0062] In some embodiments, the at least one transistor unit further comprises:

[0063] The second trench 120 formed on the first surface 201 of the drift region 20;

[0064] The gate oxide layer 12 formed on the sidewall and bottom of the second trench 120, the thickness of the gate oxide layer 12 is suitable for the size of the second trench 120, so that after the formation of the gate oxide layer 12, the first remaining trench 120' is reserved;

[0065] The third polysilicon layer 221 formed on the bottom of the first remaining trench 120', the thickness of the third polysilicon layer 221 is suitable for the size of the first remaining trench 120', so that after the formation of the third polysilicon layer 221, the second remaining trench 120" is reserved;

[0066] The fourth polysilicon layer 41 filled in the second remaining trench 120".

[0067] Specifically, the SiO2 can be deposited on the sidewall and bottom of the second trench 120 to form the gate oxide layer 12.

[0068] A layer of P - -poly can be grown on the bottom of the first remaining trench 120' as the third polysilicon layer 221, the second remaining trench 120" is formed, and then a layer of N + -poly is grown on the bottom of the second remaining trench 120" to form the fourth polysilicon layer 41, which is filled in the second remaining trench 120".

[0069] In some embodiments, the at least one transistor unit further comprises:

[0070] The gate 21 formed above the first surface 4101 of the fourth polysilicon layer 41.

[0071] In particular, the gate 21 can be formed by a deposition method, the thickness of the gate 21 being between 5 nanometers (nm) and 100 nanometers, in particular between 10 nanometers and 50 nanometers. The gate 21 can comprise a metal, a metal alloy, a metal nitride or a metal carbide. The metal can be titanium (Ti), molybdenum (Mo) or tantalum (Ta). The metal alloy can be TiAl or TiW. The metal nitride can be titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN) or molybdenum nitride (MoN). The carbide can be titanium carbide (TiC).

[0072] In some embodiments, the at least one transistor cell further comprises:

[0073] a glass layer 24 covering the gate 21.

[0074] In particular, the glass layer 24 covering the gate 21 can be formed by a deposition method, the glass layer 24 can comprise a phosphosilicate glass, a borophosphosilicate glass, a borosilicate glass.

[0075] In some embodiments, the at least one transistor cell further comprises:

[0076] a P-well region 151 and a P + region 152 formed by ion implantation at the first surface 201 of the drift region 20, respectively.

[0077] In some embodiments, the at least one transistor cell further comprises:

[0078] a P-base 6 formed by ion implantation at the first surface 201 of the drift region 20.

[0079] In some embodiments, the at least one transistor cell further comprises:

[0080] a source region 5 formed by ion implantation at the first surface of the P-base 6.

[0081] In particular, the source region 5 can be an N ++ source region.

[0082] In some embodiments, the at least one transistor cell further comprises:

[0083] a source formed above the first surface 4201 of the second polysilicon layer 42.

[0084] In some embodiments, the at least one transistor cell further comprises:

[0085] a drain 14;

[0086] a substrate 7;

[0087] a buffer region 9;

[0088] Substrate 7 is disposed between drain 14 and buffer 9;

[0089] Buffer 9 is arranged between substrate 7 and drift region 20.

[0090] Specifically, substrate 7 may include silicon carbide (SiC).

[0091] The MOSFET provided in this embodiment of the invention is a monolithically integrated HJD and VU-MOSFET, which reduces the turn-on voltage and dead time of the diode during freewheeling, has a faster reverse recovery speed and reverse recovery charge, causes a smaller current spike when the MOSFET is turned on, and reduces the manufacturing difficulty.

[0092] The VU-MOSFET and HJD are monolithically integrated in the y-direction, which solves the problems of low reverse withstand voltage and unsaturated reverse leakage current, and can increase the switching speed of the MOSFET and reduce losses.

[0093] It further reduces the footprint compared to traditional MOSFETs that integrate VDMOSFET and SBD.

[0094] Figure 2 A schematic diagram of a method for fabricating a MOSFET provided in an embodiment of the present invention is shown below. Figure 2 As shown, an embodiment of the present invention provides a method for fabricating a MOSFET, the method comprising:

[0095] Step 201: Form a first groove 110 on the first surface 201 of the drift region 20;

[0096] Step 202: Fill the first trench 110 with polysilicon 22;

[0097] Step 203: Ion implantation is performed from the first surface 2201 of polysilicon 22 to form a first polysilicon layer 222 and a second polysilicon layer 42.

[0098] Specifically, the following describes the method for fabricating MOSFETs using some exemplary processes:

[0099] 1. Figure 3 This is one of the schematic diagrams of a MOSFET structure during the fabrication process provided by an embodiment of the present invention, as shown below. Figure 3 As shown, a buffer layer is grown on SiC substrate 7, and an N layer is grown on the buffer layer. - -SiC drift region 20.

[0100] 2. Figure 4 This is a second schematic diagram of the structure of a MOSFET during the fabrication process, as provided in an embodiment of the present invention.Figure 4 As shown, P well region 151 and P base region 152 are formed by ion implantation on first surface 201 of drift region 20, respectively. + Region 152.

[0101] 3、 Figure 5 As shown, a second trench 120 for gate is etched on first surface 201 of drift region 20, and second trench 120 can be a U-shaped trench. Figure 5

[0102] 4、 Figure 6 As shown, a second trench 120 for gate is etched on first surface 201 of drift region 20, and second trench 120 can be a U-shaped trench. Figure 6

[0103] 5、 Figure 7 As shown, a second trench 120 for gate is etched on first surface 201 of drift region 20, and second trench 120 can be a U-shaped trench. Figure 7 - -poly as third polysilicon layer 221, forming a second remaining trench 120".

[0104] 6、 Figure 8 As shown, a second trench 120 for gate is etched on first surface 201 of drift region 20, and second trench 120 can be a U-shaped trench. Figure 8 + -poly forming fourth polysilicon layer 41, which fills in second remaining trench 120".

[0105] 7、 Figure 9 As shown, P base 6 is formed by ion implantation on first surface 201 of drift region 20, and then source region 5 is formed by ion implantation on first surface of P base 6. Figure 9

[0106] 8、 Figure 10 As shown, P base 6 is formed by ion implantation on first surface 201 of drift region 20, and then source region 5 is formed by ion implantation on first surface of P base 6. Figure 10 ​​​​​As shown, a first trench 110 forming the HJD is etched on the first surface 201 of the drift region 20, and the first trench 110 can be a U-shaped trench.

[0107] 9、 Figure 11 A ninth structure diagram of a MOSFET in a process of manufacturing the MOSFET is provided for an embodiment of the present application, as shown in the figure. Figure 11 As shown, a P-poly layer 22 is filled in the first trench 110 by using a deposition method. - -poly22.

[0108] 10、 Figure 12 A tenth structure diagram of a MOSFET in a process of manufacturing the MOSFET is provided for an embodiment of the present application, as shown in the figure. Figure 12 As shown, a first P-poly layer 222 and a second N-poly layer 42 are formed by ion implantation on the first surface 2201 of the P-poly layer 22 filled in the first trench 110. - -poly) layer 42. +

[0109] 11、 Figure 13 An eleventh structure diagram of a MOSFET in a process of manufacturing the MOSFET is provided for an embodiment of the present application, as shown in the figure. Figure 13 As shown, a gate 21 is formed by depositing a gate metal on the first surface 4101 of the fourth P-poly layer 41.

[0110] 12、 Figure 14 A twelfth structure diagram of a MOSFET in a process of manufacturing the MOSFET is provided for an embodiment of the present application, as shown in the figure. Figure 14 As shown, a layer of phosphor silicon glass 24 is deposited outside the gate 21, and the phosphor silicon glass 24 covers the gate 21.

[0111] 13、Finally, source metal and drain metal are deposited to obtain the MOSFET as shown in the figure. Figure 1

[0112] It should be noted that the present disclosure is not limited to the above exemplary process, and the sequence of the above manufacturing steps can be adjusted according to actual conditions, for example, the sequence of steps 7 and 8 can be interchanged, and the sequence of steps 7 and 11 can also be interchanged.

[0113] Figure 15 An equivalent circuit diagram of the MOSFET provided for an embodiment of the present application, Figure 16 ​​The band structure schematic diagram of HJD in the MOSFET provided by the embodiment of the present application, the method for manufacturing the MOSFET provided by the embodiment of the present application, and the MOSFET manufactured by the method are monolithic integrated with the HJD and the VU-MOSFET, the turn-on voltage and the dead time of the diode during the freewheeling are reduced, the reverse recovery speed and the reverse recovery charge are faster, the current spike caused by the MOSFET opening is smaller, and the manufacturing difficulty is reduced.

[0114] The VU-MOSFET and the HJD are monolithic integrated in the y direction, the reverse withstand voltage is small, the reverse leakage current is not saturated, the switching speed of the MOSFET can be increased, and the loss can be reduced.

[0115] Compared with the conventional MOSFET integrated with the VDMOSFET and the SBD, the occupied area is further reduced.

[0116] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A metal oxide semiconductor field effect transistor, characterized by, The metal oxide semiconductor field effect transistor is a vertical trench type, comprising at least one transistor unit, the at least one transistor unit comprises: a drift region (20); a P-well region (151) formed by ion implantation at a side edge region of a first surface (201) of the drift region (20); P+ region (151) is formed by ion implantation at both ends of the other side edge region of the first surface (201) of the drift region (20) + region (152); In two P + a first trench (110) formed between two P + regions (152); A second trench (120) is formed between the P-well region (151) and the P + region (152). a first polysilicon layer (222) and a second polysilicon layer (42) formed by ion implantation at a first surface (2201) of the polysilicon (22) filled in the first trench (110), the first polysilicon layer (222) and the second polysilicon layer (42) are of different doping types, constituting a heterojunction diode; a gate oxide layer (12) formed on a sidewall and a bottom of the second trench (120), a thickness of the gate oxide layer (12) is suitable for a size of the second trench (120), so that a first remaining trench (120') is reserved after the gate oxide layer (12) is formed; a third polysilicon layer (221) formed on a bottom of the first remaining trench (120'), a thickness of the third polysilicon layer (221) is suitable for a size of the first remaining trench (120'), so that a second remaining trench (120'') is reserved after the third polysilicon layer (221) is formed; a fourth polysilicon layer (41) filled in the second remaining trench (120'').

2. The metal oxide semiconductor field effect transistor of claim 1, wherein, The at least one transistor unit further comprises: a gate (21) formed above a first surface (4101) of the fourth polysilicon layer (41).

3. The MOSFET of claim 2, wherein, The at least one transistor unit further comprises: a glass layer (24) covering the gate (21).

4. The MOSFET of claim 1, wherein: The at least one transistor unit further comprises: a P-base (6) formed by ion implantation at the first surface (201) of the drift region (20).

5. The MOSFET of claim 4, wherein: The at least one transistor unit further comprises: a source region (5) formed by ion implantation at a first surface of the P-base (6).

6. The MOSFET of claim 1, wherein: The at least one transistor unit further comprises: a source formed above a first surface (4201) of the second polysilicon layer (42).

7. The metal oxide semiconductor field effect transistor according to any one of claims 1 to 6, characterized by, The at least one transistor unit further comprises: a drain (14); a substrate (7); a buffer region (9); the substrate (7) is arranged between the drain (14) and the buffer region (9); the buffer region (9) is arranged between the substrate (7) and the drift region (20).

8. A method of fabricating a metal oxide semiconductor field effect transistor, characterized by, The metal oxide semiconductor field effect transistor is a vertical trench type, the method comprises: A P-well region (151) is formed by ion implantation at one side edge region of a first surface (201) of the drift region (20), and P + regions (152) are formed by ion implantation at both ends of the other side edge region, and a first trench (110) is formed between the two P + regions (152), and a second trench (120) is formed between the P-well region (151) and the P + regions (152); filling the polysilicon (22) in the first trench (110); forming the first polysilicon layer (222) and the second polysilicon layer (42) by ion implantation at a first surface (2201) of the polysilicon (22), the first polysilicon layer (222) and the second polysilicon layer (42) are of different doping types, constituting a heterojunction diode; forming the gate oxide layer (12) on a sidewall and a bottom of the second trench (120), a thickness of the gate oxide layer (12) is suitable for a size of the second trench (120), so that the first remaining trench (120') is reserved after the gate oxide layer (12) is formed; A third polysilicon layer (221) is formed at the bottom of the first remaining trench (120'), the thickness of the third polysilicon layer (221) being suitable for the size of the first remaining trench (120'), so that after the formation of the third polysilicon layer (221), the second remaining trench (120'') is reserved; A fourth polysilicon layer (41) is filled into the second remaining trench (120'').

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