A lock-in amplifier with a combined front-end amplifier circuit structure

Abstract

The present invention discloses a phase-locked amplifier (PLA) with a combined front-end amplification circuit structure, comprising unit circuits for input signal acquisition, digital processing, voltage monitoring, bias adjustment, and signal output. The input signal acquisition circuit and the voltage monitoring circuit input an analog input signal and output a first analog-to-digital conversion signal and a second analog-to-digital conversion signal to the digital processing unit. The signal output circuit receives a modulated signal from the digital processing unit and outputs an analog modulated signal. The bias adjustment circuit outputs a first bias voltage and a second bias voltage to the input signal acquisition circuit and the signal output circuit. The digital processing unit automatically configures gain based on the second analog-to-digital conversion signal and outputs a control signal to the other unit circuits. The present invention is used for weak signal detection and can expand the input range while maintaining a low equivalent input noise level. Its real-time automatic gain configuration function can maintain the lowest equivalent input noise during signal measurement.

Description

Technical Field

[0001] The present invention relates to a lock-in amplifier, more specifically to a lock-in amplifier with a combined front-end amplification circuit structure, and is particularly used for detecting weak signals buried in strong background noise. Background Art

[0002] Detecting weak signals buried in a strong noise background is a common problem in scientific research and engineering. A lock-in amplifier is a weak signal detection instrument based on correlation detection. When using a lock-in amplifier, the signal to be detected is first modulated to a specific frequency. This signal is then demodulated using a reference signal with the same frequency as the signal to be detected. After low-pass filtering, the amplitude and phase information of the signal to be detected are obtained, while the noise of the remaining frequency components in the input signal is suppressed.

[0003] Lock-in amplifiers are categorized into analog and digital lock-in amplifiers. Analog-digital lock-in amplifiers utilize analog components for lock-in demodulation and filtering. Digital lock-in amplifiers utilize digital signal processing for reference signal generation, signal demodulation, and low-pass filtering. By avoiding the input range limitations of analog demodulators and minimizing the effects of analog component offset drift and nonlinearity, digital lock-in amplifiers offer superior performance in dynamic range and other metrics, making them the current mainstream implementation of lock-in amplifiers.

[0004] The nominal noise specifications of commercial lock-in amplifiers are generally given at the minimum range, around a kHz frequency. In reality, the instrument's equivalent input noise increases with increasing range, and due to the presence of 1 / f noise, the noise level in the frequency range from tens to hundreds of Hz increases further. However, current commercial lock-in amplifiers pay little attention to the degradation of equivalent input noise at a wide range, and there is little dedicated optimization for equivalent input noise at low frequencies. When measuring subtle changes in large signals, the equivalent input noise of a typical commercial lock-in amplifier at a wide input range can be over a hundred times higher than its nominal value, severely impacting signal resolution. Furthermore, the low equivalent input noise of commercial lock-in amplifiers relies on low-noise, high-gain front-end amplifier circuitry. When inputting a wide range of signals, the linearity of these components can affect the signal, making it difficult to achieve both low noise and a wide range with this type of architecture.

[0005] Chinese patent CN 114039557A discloses a precision, high-bandwidth digital lock-in amplifier with a hybrid sampling structure. This amplifier adds a mixer, a digitally controlled oscillator, a second low-pass filter, and an analog-to-digital converter to the input signal chain. The available sampling structures include low-frequency, down-conversion, and high-frequency sampling modes. By selecting the appropriate sampling mode, the signal-to-noise ratio (SNR) of signals of different frequencies can be improved. However, this design primarily considers the impact of the input signal frequency on the performance of the lock-in amplifier, ignoring the impact of the input signal amplitude. The input chain shares the same front-end amplifier circuit. As the range increases, the gain multiplier decreases, weakening the noise suppression capability of the front-end amplifier circuit. This increases the equivalent input noise of the device and degrades the SNR.

[0006] Chinese patent CN 104092442A discloses a hybrid analog-digital lock-in amplifier and a method for the same. The lock-in amplifier combines analog mixing, analog low-pass filtering, and digital low-pass filtering to filter out interference from the input signal and improve the signal-to-noise ratio. However, the analog structure, such as the analog multiplier, used in the lock-in amplifier limits its dynamic range and other indicators. Furthermore, the drift and offset of the analog components also affect the noise performance.

[0007] Chinese patent CN 103389161A discloses a lock-in amplifier device for detecting weak terahertz signals. This device extracts microvolt-level terahertz signals from millivolt-level background noise. Its gain module consists of at least three amplifiers with different gains connected in parallel via a switching signal to meet the gain requirements of signals with different amplitudes. However, the variable gain mode of connecting multiple fixed gains in parallel within the signal amplification module significantly limits the gain multiplier to the operational amplifier, making it difficult to achieve high gain and detect weaker signals.

[0008] In some experiments, a lock-in amplifier is required to detect input signals in the volt range while having a low equivalent input noise. For example, in a vibrating sample magnetometer system, a high-precision lock-in amplifier is needed to measure resonance signals with amplitudes in the volt range, and the noise level of the lock-in amplifier determines the resolution of the magnetic field intensity. In some displacement sensor systems, a high-precision lock-in amplifier is needed to measure the output signal of the photoelectric conversion circuit with amplitudes in the volt range, and the noise level of the lock-in amplifier determines the resolution of the displacement sensor system. In addition, the signals to be detected in the above experiments are all only in the hundreds of hertz range and will be affected by the 1 / f noise of the input instrument. The poor noise floor of existing commercial lock-in amplifiers under large-scale conditions and the serious 1 / f noise interference will seriously affect the final results of these experimental systems. Summary of the Invention

[0009] The present invention is to avoid the shortcomings of the above-mentioned prior art. In order to solve the problem of equivalent input noise degradation of the phase-locked amplifier under large-scale conditions and low-frequency bands, a phase-locked amplifier with a combined front-end amplification circuit structure is provided. In addition to having nanovolt-level noise under small-scale input conditions, the phase-locked amplifier can achieve large-scale and low-frequency band signal acquisition while maintaining decanovolt-level equivalent input noise.

[0010] The present invention adopts the following technical solutions to achieve the purpose of the invention:

[0011] The lock-in amplifier of the combined front-end amplifier circuit structure of the present invention is characterized in that it includes an input signal acquisition circuit, a digital processing unit, a voltage monitoring circuit, a bias adjustment circuit and a signal output circuit; the input signal acquisition circuit receives an analog input signal, sequentially performs low-noise analog-to-digital conversion for the analog input signal through a gating circuit, a combined front-end circuit, a filtering circuit and an analog-to-digital converter, and outputs a first analog-to-digital conversion signal to the digital processing unit; the combined front-end circuit has two front-end amplifier circuits that can be selected, namely a first front-end amplifier circuit and a second front-end amplifier circuit; the voltage monitoring circuit acquires the analog input signal, converts it into a second analog-to-digital conversion signal after ADC conversion, and outputs a second analog-to-digital conversion signal to the digital processing unit; the bias adjustment circuit receives a control signal from the digital processing unit and outputs two bias voltages, respectively. It is a first bias voltage and a second bias voltage, the first bias voltage is connected to the input signal acquisition circuit, and the second bias voltage is connected to the signal output circuit; the signal output circuit receives the modulation signal from the digital processing unit, converts it into an analog modulation signal after ADC conversion; the digital processing unit outputs the modulation signal to the signal output circuit according to the second analog-to-digital conversion signal, and outputs control signals to the input signal acquisition circuit, the bias adjustment circuit and the signal output circuit respectively; the digital processing unit is implemented by an FPGA configured with a firmware program; the digital processing unit determines the minimum noise range that meets the analog input signal range, and configures the gain multiple of the input signal acquisition circuit in real time according to the minimum noise range, thereby realizing the automatic gain configuration function of the digital processing unit.

[0012] The phase-locked amplifier of the combined front-end amplifier circuit structure of the present invention is also characterized in that: in the combined front-end circuit: the first front-end amplifier circuit and the second front-end amplifier circuit both use 10Mohm resistors for impedance matching; the second front-end amplifier circuit has a smaller gain multiple, a higher input range and a larger equivalent input noise than the first front-end amplifier circuit.

[0013] The phase-locked amplifier of the combined front-end amplifier circuit structure of the present invention is also characterized in that: the two front-end amplifier circuits are both composed of an input stage and a variable gain circuit of their own, namely: the first front-end amplifier circuit is composed of a first input stage and a first variable gain circuit; the second front-end amplifier circuit is composed of a second input stage and a second variable gain circuit; the analog input signal is connected to the input stage, and is output to the filter circuit after being amplified by the subsequent variable gain circuit; the first input stage is an amplifier circuit implemented with a common source amplifier circuit structure using discrete JFET devices; the second input stage is a follower circuit composed of two JFET integrated operational amplifiers; the first variable gain circuit and the second variable gain circuit are both cascaded negative feedback amplifier circuits, which are operational amplifiers using BJT technology; the control signal from the digital processing unit is used to control the relay in the negative feedback circuit, thereby obtaining the set gain multiple of the variable gain circuit.

[0014] The lock-in amplifier of the combined front-end amplification circuit structure of the present invention is also characterized in that: the filtering circuit in the input signal acquisition circuit is composed of a notch filter and an anti-aliasing low-pass filter; the notch filter is a band-stop filter, and an adjustable resistor is provided in the notch filter to adjust the stop-band suppression ratio and center frequency of the notch filter; the anti-aliasing low-pass filter is a low-pass filter, which is implemented by using a generalized impedance transformer structure to equivalently replace the LC filter circuit.

[0015] The lock-in amplifier of the combined front-end amplification circuit structure of the present invention is also characterized in that: the signal output circuit is composed of a DAC circuit, a variable gain circuit, an output filter circuit and a drive circuit; the DAC circuit is an R / 2R type high-precision DAC circuit including AD5791, which is used to receive the modulation signal from the digital processing unit and convert it into an analog modulation signal; the variable gain circuit is composed of a cascade of a first-level variable gain operational amplifier and a first-level passive attenuation network, which is used to receive the analog modulation signal from the high-precision DAC and output the gained analog modulation signal to the output filter circuit; the output filter circuit is an LC low-pass filter, which is used to output the filtered analog modulation signal to the drive circuit; the drive circuit uses the drive operational amplifier to provide a drive current for the output signal, thereby realizing the output of the analog modulation signal in the signal output circuit.

[0016] The lock-in amplifier of the combined front-end amplification circuit structure of the present invention is also characterized in that: the voltage monitoring circuit is composed of an input isolation operational amplifier and a multi-channel ADC; the input isolation operational amplifier receives an analog input signal through a gating circuit in an input signal acquisition circuit and outputs it to the multi-channel ADC; the multi-channel ADC outputs a second analog-to-digital conversion signal; the bias adjustment circuit is composed of an output isolation operational amplifier and a multi-channel DAC, and the multi-channel DAC outputs a first bias voltage and a second bias voltage respectively through the output isolation operational amplifier according to a control signal of a digital processing unit.

[0017] The phase-locked amplifier of the combined front-end amplification circuit structure of the present invention is also characterized in that: the digital processing unit is a control module, a communication module, a digital operation module, a DDS module and a clock module generated in the FPGA; the submodules of the control module include: a master control state machine, a data cache module, a data transmission module and an automatic gain configuration judgment module; the communication module receives an instruction from the host computer and outputs it to the master control state machine in the control module, and the master control state machine sends a control signal according to the instruction of the host computer and performs data scheduling between the modules; the digital operation module is composed of a phase-sensitive detector, a digital low-pass filter and an amplitude and phase calculation module; the phase-sensitive detector multiplies the first analog-to-digital conversion signal and the reference signal to obtain a product, and the product is filtered by the digital low-pass filter and input into the amplitude and phase calculation module, which calculates the amplitude and phase of the signal to be detected in the analog input signal and uploads it to the host computer; the DDS module is used to generate the reference signal and modulation signal of the digital LIA.

[0018] The lock-in amplifier of the combined front-end amplifier circuit structure of the present invention is also characterized in that:

[0019] The automatic gain configuration function of the digital processing unit is implemented as follows:

[0020] First, the control module in the digital processing unit performs an initial range determination: the control module receives N data point signals of the second analog-to-digital conversion signal, and takes the maximum value of the N data point signals as the maximum amplitude of the second analog-to-digital conversion signal. The control module then compares the maximum amplitude of the second analog-to-digital conversion signal with the maximum input amplitudes of different ranges one by one. When the maximum amplitude of the second analog-to-digital conversion signal is less than the maximum input amplitude of range A for the first time, range A is determined as the initial range. The control module then searches for and obtains a configuration instruction based on a written configuration word lookup table and sends it to complete the initial range setting of the automatic gain configuration.

[0021] Subsequently, the digital processing unit enters a real-time automatic gain configuration state and performs a range setting operation in a loop; the control module generates an upper amplitude threshold and a lower amplitude threshold according to the result of the last range setting operation;

[0022] The control module generates a FLAG_O signal when it is determined that the second analog-to-digital conversion signal is higher than an upper amplitude threshold;

[0023] The control module generates a FLAG_U signal when it is determined that the second analog-to-digital conversion signal is lower than the amplitude lower limit threshold;

[0024] During a range determination process, the control module receives N data point signals of the second analog-to-digital conversion signal and counts the number of FLAG_O signals as a and the number of FLAG_U signals as b. The following determination is made based on the values ​​of a and b:

[0025] If m1>a>0, it is determined that the gain multiplier of the input signal acquisition circuit is increased by one gear;

[0026] If a>m1, it is determined that the gain multiplier of the input signal acquisition circuit is increased by two levels;

[0027] If a=0 and b>m2, it is determined that the gain of the input signal acquisition circuit is reduced by one level;

[0028] Among them, m2 and m1 are both adjustable statistical thresholds;

[0029] After completing the range judgment operation, the control module will search and send the configuration instruction according to the configuration word lookup table written in advance to complete an automatic gain configuration operation; after the set time delay, the next range judgment operation will begin;

[0030] The lock-in amplifier of the combined front-end amplifier circuit structure of the present invention is also characterized in that: the manual control method for setting the gain configuration of the lock-in amplifier is to manually configure the gain multiple of the lock-in amplifier according to the control instruction of the host computer when the digital processing unit receives the control instruction from the host computer.

[0031] Compared with the existing technology, the beneficial effects of the present invention are embodied in:

[0032] 1. The input signal acquisition circuit of the present invention utilizes a combined front-end structure, comprising a first amplifier circuit and a second amplifier circuit that can be selected. The first amplifier circuit can achieve a gain of tens to thousands of times on weak analog input signals. When the first amplifier circuit is selected, the equivalent input noise of the present invention is in the nanovolt range. The second amplifier circuit of the combined front-end structure has an input range far greater than that of the first amplifier circuit. When the second amplifier circuit is selected, the equivalent input noise of the present invention is at most on the order of tens of nanovolts. By selecting the first and second amplifier circuits of the combined front-end structure, the present invention can expand the input range while maintaining a low equivalent input noise level.

[0033] 2. The present invention features automatic gain configuration. When automatic gain configuration is enabled, the digital processing unit determines the amplitude of the second analog-to-digital conversion signal input by the voltage monitoring circuit and selects a gain configuration that meets the analog input signal amplitude range requirements while minimizing equivalent input noise. This automatic gain configuration function operates in real time, ensuring that the present invention always operates within the optimal range, further reducing the impact of equivalent input noise.

[0034] 3. The input signal acquisition circuit of the present invention adopts JFET and BJT process devices. Relying on the characteristics of the JFET and BJT devices having an early 1 / f noise inflection point, the 1 / f noise inflection point of the equivalent input noise of the present invention is at hundreds of hertz, and has good low-frequency noise performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a basic structural block diagram of a lock-in amplifier with a combined front-end amplifier circuit structure in the present invention;

[0036] Figure 2 This is a structural block diagram of the combined front-end amplifier circuit in the present invention;

[0037] Figure 3 This is a structural diagram of the input signal acquisition circuit in the present invention;

[0038] Figure 4 This is a structural block diagram of the signal output circuit in the present invention;

[0039] Figure 5 This is a structural block diagram of the digital processing unit in the present invention;

[0040] Figure 6 This is a control flow chart of the automatic gain configuration function in the present invention; DETAILED DESCRIPTION

[0041] like Figure 1 As shown, the lock-in amplifier with a combined front-end amplifier circuit structure in this embodiment includes an input signal acquisition circuit, a digital processing unit, a voltage monitoring circuit, a bias adjustment circuit and a signal output circuit.

[0042] The input signal acquisition circuit receives an analog input signal and performs low-noise analog-to-digital conversion on the analog input signal through a gating circuit, a combined front-end circuit, a filtering circuit, and an analog-to-digital converter. The circuit then outputs a first analog-to-digital conversion signal to the digital processing unit. The combined front-end circuit includes two selectable front-end amplifier circuits: a first front-end amplifier circuit and a second front-end amplifier circuit. The analog input signal is split into two paths at the gating circuit of the input signal acquisition circuit and output to the combined front-end circuit and the voltage monitoring circuit, respectively.

[0043] The voltage monitoring circuit collects the analog input signal and converts it through the ADC, then outputs a second analog-to-digital conversion signal to the digital processing unit.

[0044] The bias adjustment circuit receives a control signal from the digital processing unit and outputs two bias voltages, namely a first bias voltage and a second bias voltage. The first bias voltage is connected to the input signal acquisition circuit, and the second bias voltage is connected to the signal output circuit.

[0045] The signal output circuit receives the modulation signal from the digital processing unit and outputs an analog modulation signal after conversion by ADC;

[0046] The digital processing unit outputs a modulated signal to the signal output circuit based on the second analog-to-digital conversion signal, and outputs control signals to the input signal acquisition circuit, the bias adjustment circuit, and the signal output circuit respectively; the digital processing unit is implemented by an FPGA configured with a firmware program; the digital processing unit determines the minimum noise range that meets the analog input signal range, and configures the gain multiple of the input signal acquisition circuit in real time based on the minimum noise range, thereby realizing the automatic gain configuration function of the digital processing unit.

[0047] In specific implementation, the corresponding technical measures also include:

[0048] In the combined front-end circuit, both the first and second front-end amplifier circuits use 10Mohm resistors for impedance matching. The second front-end amplifier circuit has a smaller gain, a wider input range, and greater equivalent input noise than the first. Activating the first front-end amplifier circuit corresponds to the small-range condition of the present invention, while activating the second front-end amplifier circuit corresponds to the large-range condition of the present invention.

[0049] like Figure 2 As shown, the two front-end amplifier circuits are composed of their own input stages and variable gain circuits, which are:

[0050] The first front-end amplifier circuit is composed of a first input stage and a first variable gain circuit;

[0051] The second front-end amplifier circuit is composed of a second input stage and a second variable gain circuit;

[0052] The analog input signal is connected to the input stage and is amplified by the subsequent variable gain circuit and then output to the filter circuit;

[0053] The first input stage is an amplifier circuit implemented with a common source amplifier circuit structure using a discrete JFET device LSK389C, which has a fixed gain of 5 times. The 1 / f noise inflection point of the small-scale input stage equivalent input noise is less than 100Hz, with a 300mV input amplitude range and a high input impedance of 10Tohm.

[0054] The second input stage is a follower circuit composed of two JFET integrated operational amplifiers OPA141, which has It has an equivalent input noise platform of about 100mA, an input amplitude range of more than 3V, and a high input impedance of 10Tohm.

[0055] The first variable gain circuit and the second variable gain circuit are both cascade negative feedback amplifier circuits, which are variable gain stages implemented by using BJT process full differential operational amplifier THS4131. Their equivalent input noise floor is The input impedance is 10kohm, and the 1 / f noise inflection point is at a few hundred hertz. Each variable-gain op amp has two selectable positions. Multiple variable-gain stages are connected in series, resulting in a variable-gain circuit with multiple selectable gain multiples. Control signals from the digital processing unit control relays in the negative feedback circuit to achieve the desired gain multiple.

[0056] The equivalent input noise E of the signal chain of the input signal acquisition circuit has the following relationship with the gain of each level:

[0057]

[0058] in:

[0059] A n is the gain multiple of the input stage and each variable gain stage; E n is the equivalent input noise of the input stage and each variable gain stage; E other It is the equivalent input noise of the filter circuit and ADC and other circuits at the back end of the variable gain circuit. Under small-scale conditions, the gain of each stage of the variable gain circuit is relatively high, and the total equivalent input noise approaches the equivalent input noise of the input stage. Therefore, the high-gain and extremely low-noise design of the first variable gain circuit input stage ensures that the phase-locked amplifier has extremely low equivalent input noise under small-scale conditions. Under large-scale conditions, the total gain decreases, and the equivalent input noise of the input signal acquisition circuit under large-scale conditions needs to consider the noise contribution of each stage. Therefore, when designing each module of the circuit, this embodiment follows the principle that the 1 / f noise inflection point of the selected scheme is lower than 1kHz and the equivalent input noise of the selected scheme is the lowest. In addition, the input stage of the variable gain circuit has an extremely high input impedance, which reduces the requirements for the driving capability of the analog input signal.

[0060] Figure 3The filtering circuit in the input signal acquisition circuit shown in the figure consists of a notch filter and an anti-aliasing low-pass filter. The notch filter in the filtering circuit is a band-stop filter, and an adjustable resistor is set in the notch filter to adjust the notch filter's stopband rejection ratio and center frequency. The specific circuit consists of two stages: a multi-feedback active filter and a driver, with center frequencies of 50Hz and 100Hz, respectively. This corresponds to the power system's power frequency noise and its second harmonic. The notch filter can suppress interference caused by the power system's AC power while having little impact on the remaining frequency components of the analog input signal. Furthermore, the notch filter is designed to be selectively engaged. A control signal controls the relay switch, allowing the notch filter to be engaged only when power frequency noise interference is severe. Normally, it can be disconnected from the circuit to prevent the introduction of additional noise.

[0061] The anti-aliasing low-pass filter is implemented by replacing the LC filter circuit with a generalized impedance transformer. The anti-aliasing low-pass filter has an extremely high roll-off rate, effectively preventing signals with frequencies greater than half the sampling rate from aliasing into the low-frequency region. This solution avoids the implementation difficulties caused by inductor component accuracy issues in passive LC filter circuits and the degradation of amplitude-frequency response caused by significant deviations from ideal component values.

[0062] The analog-to-digital converter uses the LTC2380-24 as a high-precision successive approximation ADC. This model ADC has a maximum full-scale input amplitude of 5V. When the same amplitude signal is input, the front-end variable gain circuit has a higher gain multiple, thereby suppressing the overall noise. This model ADC also has dozens of The noise level can be reduced to avoid the influence of ADC on the overall equivalent input noise under a large range condition.

[0063] like Figure 4 As shown, the signal output circuit is composed of a DAC circuit, a variable gain circuit, an output filter circuit and a drive circuit;

[0064] The DAC circuit is an R / 2R type high-precision DAC, AD5791, which is used to receive the modulation signal from the digital processing unit and convert it into an analog modulation signal;

[0065] The variable gain circuit is composed of a cascade of a first-stage variable gain operational amplifier and a first-stage passive attenuation network, and is used to receive the analog modulation signal from the high-precision DAC and output the analog modulation signal after gain to the output filter circuit;

[0066] The output filter circuit is an LC low-pass filter, which is used to output the filtered analog modulated signal to the drive circuit, and can suppress high-frequency noise in the output signal;

[0067] The driver circuit uses a driver op amp to provide drive current for the output signal, realizing the output of the analog modulated signal in the signal output circuit. The driver op amp model used is THS3001, which can reach an output current of more than 100mA and can ensure that it can drive a minimum 50ohm load when outputting the maximum range signal.

[0068] The voltage monitoring circuit consists of an input isolation op amp and a multi-channel ADC;

[0069] The input isolation operational amplifier receives the analog input signal through the gating circuit in the input signal acquisition circuit and outputs it to the multi-channel ADC; the multi-channel ADC outputs a second analog-to-digital conversion signal;

[0070] The bias adjustment circuit is composed of an output isolation operational amplifier and a multi-channel DAC. The multi-channel DAC outputs a first bias voltage and a second bias voltage respectively through the output isolation operational amplifier according to a control signal of a digital processing unit.

[0071] like Figure 5 As shown, the digital processing unit is a control module, a communication module, a digital operation module, a DDS module and a clock module generated in the FPGA;

[0072] The submodules of the control module include: a master control state machine, a data buffer module, a data transmission module and an automatic gain configuration judgment module;

[0073] After receiving the host computer instructions, the communication module outputs them to the master control state machine in the control module. The master control state machine sends control signals according to the host computer instructions and performs data scheduling between modules. Figure 5 The communication module includes USB communication and Ethernet communication. The communication method can be selected based on the experimental requirements for data transmission speed, noise, etc.

[0074] The digital operation module consists of a phase-sensitive detector, a digital low-pass filter, and an amplitude-phase calculation module. The phase-sensitive detector multiplies the first analog-to-digital conversion signal and the reference signal to obtain a product. The phase-sensitive detection result consists of a DC term, a double frequency term, and a noise term. After the product is filtered by the digital low-pass filter, the double frequency term and most of the noise term can be removed. The output contains the DC term of the amplitude and phase information of the signal to be detected, which is output to the amplitude-phase calculation module. The amplitude and phase of the signal to be detected in the analog input signal are calculated and uploaded to the host computer.

[0075] The DDS module is used to generate the reference and modulation signals for the digital LIA. This module consists of multiple independently configurable DDSs that can simultaneously generate reference signals of varying frequencies and sinusoidal modulation signals for input to the digital operation module.

[0076] like Figure 6As shown, the automatic gain configuration function of the digital processing unit is implemented as follows:

[0077] First, the control module in the digital processing unit performs an initial range judgment: the control module receives N data point signals of the second analog-to-digital conversion signal, and takes the maximum value of the N data point signals as the maximum amplitude AMP of the second analog-to-digital conversion signal. The control module then compares the maximum amplitude of the second analog-to-digital conversion signal with the maximum input amplitudes AMP_i of different ranges one by one. When the maximum amplitude AMP of the second analog-to-digital conversion signal is less than the maximum input amplitude of range A for the first time, range A is determined as the initial range. The control module then searches the written configuration word lookup table to obtain and send the corresponding configuration instruction to the input signal acquisition circuit, which can change the connection between the gating circuit and the relay in the combination front-end circuit, thereby completing the initial range setting of the automatic gain configuration.

[0078] Subsequently, the digital processing unit enters the real-time automatic gain configuration state and performs the range setting operation in a loop; the control module generates the upper and lower amplitude thresholds according to the result of the last range setting operation;

[0079] The control module generates a FLAG_O signal when determining that the second analog-to-digital conversion signal is higher than an upper amplitude threshold;

[0080] The control module generates a FLAG_U signal when determining that the second analog-to-digital conversion signal is lower than the amplitude lower limit threshold;

[0081] During a range determination process, the control module receives N data point signals of the second analog-to-digital conversion signal and counts the number of FLAG_O signals as a and the number of FLAG_U signals as b. The following determination is made based on the values ​​of a and b:

[0082] If m1>a>0, it is determined that the gain multiplier of the input signal acquisition circuit is increased by one gear;

[0083] If a>m1, it is determined that the gain multiplier of the input signal acquisition circuit is increased by two levels;

[0084] If a=0 and b>m2, it is determined that the gain of the input signal acquisition circuit is reduced by one level;

[0085] Among them, m2 and m1 are both adjustable statistical thresholds;

[0086] After completing the range judgment operation, the control module will search and send the configuration instruction according to the configuration word lookup table written in advance to complete an automatic gain configuration operation; after the set time delay, the next range judgment operation will begin;

[0087] In this embodiment, the manual control method for setting the gain configuration of the lock-in amplifier is to manually configure the gain multiple of the lock-in amplifier according to the control instruction of the host computer when the digital processing unit receives the control instruction from the host computer.

Claims

1. A lock-in amplifier with a combined front-end amplifier circuit structure, characterized in that It includes an input signal acquisition circuit, a digital processing unit, a voltage monitoring circuit, a bias adjustment circuit and a signal output circuit; The input signal acquisition circuit receives an analog input signal, sequentially performs low-noise analog-to-digital conversion on the analog input signal through a gating circuit, a combined front-end circuit, a filtering circuit, and an analog-to-digital converter, and outputs a first analog-to-digital conversion signal to a digital processing unit; the combined front-end circuit has two selectable front-end amplifier circuits, namely, a first front-end amplifier circuit and a second front-end amplifier circuit; the voltage monitoring circuit acquires the analog input signal, performs ADC conversion, and outputs a second analog-to-digital conversion signal to the digital processing unit; the bias adjustment circuit receives a control signal from the digital processing unit and outputs two bias voltages, namely, a first bias voltage and a second bias voltage, wherein the first bias voltage is connected to the input signal acquisition circuit, and the second bias voltage is connected to the signal output circuit; The signal output circuit receives a modulated signal from the digital processing unit and outputs an analog modulated signal after ADC conversion; the digital processing unit outputs the modulated signal to the signal output circuit based on the second analog-to-digital conversion signal, and outputs control signals to the input signal acquisition circuit, the bias adjustment circuit, and the signal output circuit respectively; the digital processing unit is implemented by an FPGA configured with a firmware program; the digital processing unit determines the minimum noise range that meets the analog input signal range, and configures the gain multiple of the input signal acquisition circuit in real time based on the minimum noise range, thereby realizing the automatic gain configuration function of the digital processing unit; The digital processing unit is a control module, a communication module, a digital operation module, a DDS module and a clock module generated in the FPGA; the submodules of the control module include: a master control state machine, a data buffer module, a data transmission module and an automatic gain configuration judgment module; After receiving the host computer instruction, the communication module outputs it to the master control state machine in the control module. The master control state machine sends a control signal according to the host computer instruction and performs data scheduling between modules. The digital operation module is composed of a phase-sensitive detector, a digital low-pass filter and an amplitude-phase calculation module. The phase-sensitive detector multiplies the first analog-to-digital conversion signal and the reference signal to obtain a product. The product is filtered by the digital low-pass filter and input into the amplitude-phase calculation module to calculate the amplitude and phase of the signal to be detected in the analog input signal and upload it to the host computer. The DDS module is used to generate the reference signal and modulation signal of the digital LIA.

2. The lock-in amplifier of the combined front-end amplifier circuit structure according to claim 1, characterized in that: In the combined front-end circuit: the first front-end amplifier circuit and the second front-end amplifier circuit both use 10Mohm resistors for impedance matching; the second front-end amplifier circuit has a smaller gain multiple, a higher input range, and a larger equivalent input noise than the first front-end amplifier circuit.

3. The lock-in amplifier of the combined front-end amplifier circuit structure according to claim 1, characterized in that: The two front-end amplifier circuits are both composed of their own input stage and variable gain circuit, namely: the first front-end amplifier circuit is composed of a first input stage and a first variable gain circuit; the second front-end amplifier circuit is composed of a second input stage and a second variable gain circuit; the analog input signal is connected to the input stage, and is output to the filter circuit after being amplified by the subsequent variable gain circuit; the first input stage is an amplifier circuit implemented with a common source amplifier circuit structure using discrete JFET devices; the second input stage is a follower circuit composed of two JFET integrated operational amplifiers; the first variable gain circuit and the second variable gain circuit are both cascaded negative feedback amplifier circuits, which are operational amplifiers using BJT technology; the control signal from the digital processing unit is used to control the relay in the negative feedback circuit, so as to obtain the set gain multiple of the variable gain circuit.

4. The lock-in amplifier of the combined front-end amplifier circuit structure according to claim 1, characterized in that: The filtering circuit in the input signal acquisition circuit is composed of a notch filter and an anti-aliasing low-pass filter; the notch filter is a band-stop filter, and an adjustable resistor is set in the notch filter to adjust the stopband suppression ratio and center frequency of the notch filter; the anti-aliasing low-pass filter is a low-pass filter, which is implemented by using a generalized impedance transformer structure to equivalently replace the LC filter circuit.

5. The lock-in amplifier of the combined front-end amplifier circuit structure according to claim 1, characterized in that: The signal output circuit is composed of a DAC circuit, a variable gain circuit, an output filter circuit, and a drive circuit; the DAC circuit is an R / 2R type high-precision DAC circuit including an AD5791, which is used to receive the modulated signal from the digital processing unit and convert it into an analog modulated signal; the variable gain circuit is composed of a cascade of a first-stage variable gain operational amplifier and a first-stage passive attenuation network, which is used to receive the analog modulated signal from the high-precision DAC and output the gained analog modulated signal to the output filter circuit; The output filter circuit is an LC low-pass filter, which is used to output the filtered analog modulated signal to the drive circuit; the drive circuit uses a drive op amp to provide a drive current for the output signal, thereby realizing the output of the analog modulated signal in the signal output circuit.

6. The lock-in amplifier with a combined front-end amplifier circuit structure according to claim 1, wherein: The voltage monitoring circuit consists of an input isolation op amp and a multi-channel ADC; the input isolation op amp receives an analog input signal through a gating circuit in an input signal acquisition circuit and outputs it to the multi-channel ADC; the multi-channel ADC outputs a second analog-to-digital conversion signal; the bias adjustment circuit consists of an output isolation op amp and a multi-channel DAC; the multi-channel DAC outputs a first bias voltage and a second bias voltage respectively through the output isolation op amp according to a control signal of a digital processing unit.

7. The lock-in amplifier with a combined front-end amplifier circuit structure according to claim 1, wherein: The automatic gain configuration function of the digital processing unit is implemented as follows: First, the control module in the digital processing unit performs an initial range determination: the control module receives N data point signals of the second analog-to-digital conversion signal, and takes the maximum value of the N data point signals as the maximum amplitude of the second analog-to-digital conversion signal. The control module then compares the maximum amplitude of the second analog-to-digital conversion signal with the maximum input amplitudes of different ranges one by one. When the maximum amplitude of the second analog-to-digital conversion signal is less than the maximum input amplitude of range A for the first time, range A is determined as the initial range. The control module then searches for and obtains a configuration instruction based on a written configuration word lookup table and sends it to complete the initial range setting of the automatic gain configuration. Subsequently, the digital processing unit enters a real-time automatic gain configuration state and performs a range setting operation in a loop; the control module generates an upper amplitude threshold and a lower amplitude threshold according to the result of the last range setting operation; The control module generates a FLAG_O signal when it is determined that the second analog-to-digital conversion signal is higher than an upper amplitude threshold; The control module generates a FLAG_U signal when it is determined that the second analog-to-digital conversion signal is lower than the amplitude lower limit threshold; During a range determination process, the control module receives N data point signals of the second analog-to-digital conversion signal and counts the number of FLAG_O signals as a and the number of FLAG_U signals as b. The following determination is made based on the values ​​of a and b: If m1>a>0, it is determined that the gain multiplier of the input signal acquisition circuit is increased by one gear; If a>m1, it is determined that the gain multiplier of the input signal acquisition circuit is increased by two levels; If a=0 and b>m2, it is determined that the gain of the input signal acquisition circuit is reduced by one level; Among them, m2 and m1 are both adjustable statistical thresholds; After completing the range judgment operation, the control module will search and send the configuration instruction according to the configuration word lookup table written in advance to complete an automatic gain configuration operation; after the set time delay, the next range judgment operation will begin.

8. The lock-in amplifier with a combined front-end amplifier circuit structure according to claim 1, wherein: The manual control method for setting the gain configuration of the lock-in amplifier is to manually configure the gain multiple of the lock-in amplifier according to the control instruction of the host computer when the digital processing unit receives the control instruction from the host computer.

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