Display panel and electronic device

Abstract

Embodiments of the present application provide a display panel and an electronic device, which relate to the technical field of display, and can improve the blocking effect of the partition part on water and oxygen. The display panel comprises a display area and an opening area, the opening area comprises an opening and a partition area, and the partition area is located between the opening and the display area; the display panel comprises, in the display area, a circuit layer, a planarization layer, an anode layer and a light-emitting layer which are sequentially stacked; the planarization layer has a first partition structure in the partition area, and the side surface of the first partition structure has a groove; the anode layer has a second partition structure at the top end of the first partition structure in the partition area, and the first partition structure and the second partition structure form a partition part; the display panel has a base layer in the partition area, and the partition part is a protruding structure relative to the base layer; the light-emitting layer comprises, in the partition area, a first part on the surface of the partition part and a second part on the surface of the base layer outside the partition part, and the first part and the second part have a spacing in the direction perpendicular to the plane of the display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and electronic equipment. BACKGROUND

[0002] With the development of display technology, the screen ratio of electronic equipment such as mobile phones is getting higher and higher. In order to further improve the screen ratio and enable the mobile phone to have a front camera, a technology of opening a hole on the display panel to set an optical device such as a front camera is generated. In order to prevent water and oxygen from entering the display area from the hole of the display panel, so as to avoid the problem of black spots caused by the erosion of water and oxygen to the display panel, a partition is arranged between the hole and the display area to block water and oxygen. However, the blocking effect of the partition on water and oxygen is poor. SUMMARY

[0003] A display panel and electronic equipment can improve the blocking effect of the partition on water and oxygen.

[0004] In a first aspect, a display panel is provided, comprising: a display area and a hole area, the hole area comprising a hole and a partition area, the partition area being located between the hole and the display area; the display panel comprising, in the display area, a circuit layer, a planarization layer, an anode layer and a light-emitting layer which are sequentially stacked; the planarization layer has a first partition structure in the partition area, the first partition structure comprising a top surface and a bottom surface opposite in a direction perpendicular to the plane of the display panel, and a side surface connecting the top surface and the bottom surface, the side surface of the first partition structure having a groove; the anode layer has a second partition structure located at the top end of the first partition structure in the partition area, the first partition structure and the second partition structure forming a partition; the display panel has a base layer in the partition area, the partition being a protruding structure relative to the base layer; the light-emitting layer comprises, in the partition area, a first part located on the surface of the partition and a second part located on the surface of the base layer outside the partition, the first part and the second part having a gap in the direction perpendicular to the plane of the display panel. Wherein the first partition structure is made around the hole by the planarization layer, and the second partition structure is made on the top of the first partition structure by the anode layer, wherein the side surface of the first partition structure has a groove, and the partition formed by the first partition structure and the second partition structure realizes the partition of the light-emitting layer, improves the partition effect of the light-emitting layer, that is, improves the blocking effect of water and oxygen, and improves the problem of black spots caused by the invasion of water and oxygen into the display area. The partition made of the planarization layer and the anode layer has a large thickness and is not easy to collapse, and is not easy to form a climbing of the light-emitting layer at the edge, so the partition effect of the light-emitting layer is good; the manufacturing process takes less time; and the process control is less difficult.

[0005] In a possible implementation, the depth of the groove on the side of the first partition structure is L, and 0.8 μm≤L≤1.2 μm. On the one hand, the blocking effect on the light-emitting layer is improved, and on the other hand, the probability of cracking of the encapsulation layer at the groove is reduced, so as to improve the encapsulation isolation effect.

[0006] In a possible implementation, the thickness of the first partition structure is H, and 1.5 μm≤H≤2.5 μm. The overall thickness of the display panel is controlled on the premise of ensuring that the encapsulation layer covers and fills the area around the first partition structure well.

[0007] In a possible implementation, the partition portion extends along the edge of the opening, and the width of the partition portion is W, and 10 μm≤W≤15 μm.

[0008] In a possible implementation, the thickness of the second partition structure is h, and 100 nm≤h≤120 nm. The thickness of the second partition structure is large, and the second partition structure is not easy to collapse.

[0009] In a possible implementation, the plurality of partition portions, and the spacing distance between any two adjacent partition portions is M, and 10 μm≤M≤15 μm. The organic material between the partition portions is easy to be cleaned, the adverse effect of the blocking effect on the light-emitting layer caused by residues is improved, and the space utilization is improved.

[0010] In a possible implementation, the circuit layer includes a semiconductor layer, a gate insulating layer, a gate metal layer, a capacitor dielectric layer, a capacitor metal layer, an interlayer insulating layer, and a source-drain metal layer which are sequentially stacked; the gate metal layer and / or the capacitor metal layer has a raised structure in the partition area, and the raised structure is located below the partition portion. The raised structure makes the difference between the light-emitting layer at the top of the partition portion and the light-emitting layer outside the partition portion larger, so as to improve the blocking effect of the light-emitting layer.

[0011] In a possible implementation, the display panel further includes, in the display area, an anode layer located on the side of the light-emitting layer away from the anode layer, and an encapsulation layer located on the side of the cathode layer away from the light-emitting layer; the encapsulation layer includes a first encapsulation inorganic layer, an inkjet printing layer, and a second encapsulation inorganic layer which are sequentially stacked; the display panel has an inkjet printing partition portion in the partition area, and in the partition area, the inkjet printing layer extends from the display area to the inkjet printing partition portion; the partition portion includes an outer partition portion and an inner partition portion, the inkjet printing partition portion is located between the outer partition portion and the inner partition portion, the inner partition portion is located between the inkjet printing partition portion and the display area, the outer partition portion is located between the opening and the inkjet printing partition portion, the first encapsulation inorganic layer, the inkjet printing layer, and the second encapsulation inorganic layer cover the inner partition portion, the first encapsulation inorganic layer and the second encapsulation inorganic layer cover the outer partition portion, and the inkjet printing layer does not overlap the outer partition portion.

[0012] In one possible implementation, the anode layer comprises indium tin oxide, silver, and indium tin oxide stacked sequentially.

[0013] In one possible implementation, the display panel further includes a flexible substrate layer located on the side of the circuit layer away from the planarization layer, the flexible substrate layer covering the display area and the partition area.

[0014] In one possible implementation, the flexible substrate layer includes a first polyimide layer, an isolation layer, an amorphous silicon layer, and a second polyimide layer stacked sequentially.

[0015] Secondly, an electronic device is provided, including the aforementioned display panel. Attached Figure Description

[0016] Figure 1 This is a schematic cross-sectional view of a portion of a display panel in a related art.

[0017] Figure 2 This is a schematic diagram of a cross-sectional structure of a portion of another display panel in the related technology;

[0018] Figure 3 This is a schematic diagram of a cross-sectional structure of a portion of another display panel in the related technology;

[0019] Figure 4A This is a schematic diagram of the structure of a display panel according to an embodiment of this application;

[0020] Figure 4B This is a schematic diagram of another display panel structure in an embodiment of this application;

[0021] Figure 5 for Figure 4A A schematic diagram of a cross-sectional structure along the AA' direction;

[0022] Figure 6 for Figure 5 A partially enlarged schematic diagram of the partition area;

[0023] Figure 7 for Figure 4A An enlarged schematic diagram of the central region;

[0024] Figure 8 for Figure 4A Another cross-sectional view of the structure along the AA' direction;

[0025] Figure 9 for Figure 4A Another cross-sectional view of the structure along the AA' direction;

[0026] Figure 10 A schematic diagram of a planarization layer protrusion formed in a partition area during the fabrication process of a display panel according to an embodiment of this application;

[0027] Figure 11 This is a schematic diagram of the formation of a first partition structure in the partition area during the manufacturing process of a display panel according to an embodiment of this application;

[0028] Figure 12 This is a schematic diagram of the formation of a partition portion in the partition area during the manufacturing process of a display panel according to an embodiment of this application. Detailed Implementation

[0029] Before introducing the embodiments of this application, the structures of several opening area partitions in related technologies will first be described, such as... Figure 1 As shown, the display panel includes a display area 001, an opening 002, and a partition area 003 located between the display area 001 and the opening 002. The display panel in the display area 001 includes, in sequence, a substrate layer 01, a buffer layer 02, a semiconductor layer 03, a gate insulating layer 04, a gate metal layer 05, a capacitor dielectric layer 06, a capacitor metal layer 07, an interlayer insulating layer 08, a source / drain metal layer 09, a planarization layer 010, an anode layer 011, a pixel definition layer 012, a light-emitting layer 013, a cathode layer 014, and an encapsulation layer 015. In a first related technology, a partition portion 020 formed by the source / drain metal layer 09 is provided in the partition area 003. The source / drain metal layer 09 is a stack of titanium (Ti), aluminum (Al), and titanium (Ti), wherein the Al layer forms a recessed structure with the Ti layer through side etching to facilitate the blocking of the light-emitting layer. The partition portion 020 is used to allow the light-emitting layer (Ti) to pass through. Figure 1 The light-emitting layer between the partition 020 and the encapsulation layer 015 is omitted in the original text. During the fabrication process, the partition 020 is broken at its edge to block the transmission of water and oxygen to the light-emitting layer 013, preventing water and oxygen at the edge of the opening 002 from intruding through the light-emitting layer 013 and extending to the display area 001. However, because the thickness of the Ti layer at the top of the source / drain metal layer 09 is small, less than 50nm, it is prone to collapse during subsequent photoresist stripping and washing, resulting in poor isolation effect on the light-emitting layer. Furthermore, the small thickness of the source / drain metal layer 09 makes it easy for the light-emitting layer to form a ramp at the edge of the partition 020, which can easily lead to isolation failure. Figure 2 As shown, in the second related technology, a partition portion 020 formed by a portion of the substrate layer 01 and a buffer layer 02 is provided in the partition region 003. The substrate layer 01 portion of the partition portion 020 is made of polyimide (PI) material. During the fabrication of the partition portion 020, it is necessary to first etch downwards with oxygen to obtain PI protrusions, and then etch the side surfaces of the PI protrusions to form side grooves. This process is time-consuming. Figure 3As shown, in the third related technology, a partition portion 020 formed by an inorganic layer 030 and a planarization layer 010 is provided in the partition region 003. The inorganic layer 030 can be a film layer among the buffer layer 02, gate insulating layer 04, capacitor dielectric layer 06, and interlayer insulating layer 08. The process of fabricating the partition portion 020 requires etching the sides of the protruding inorganic layer 030 to form grooves to isolate the light-emitting layer. However, controlling the etching process on the sides of the inorganic layer 030 is quite difficult. The display panel in the embodiments of this application will be described below.

[0030] like Figure 4A , Figure 4B , Figure 5 , Figure 6 and Figure 7 As shown, one embodiment of this application provides a display panel, including: a display area 1 and an opening area 2, wherein the display area 1 is disposed around or partially around the opening area 2, for example... Figure 4A The central display area 1 surrounds the opening area 2. Figure 4B The central display area 1 partially surrounds the opening area 2, which includes an opening 21 and a partition area 22 located between the opening 21 and the display area 1. The display panel in the display area 1 includes a circuit layer 3, a planarization layer 4, an anode layer 5, a light-emitting layer 6, a cathode layer 7, and an encapsulation layer 8 stacked sequentially. The planarization layer 4 has a first partition structure 11 in the partition area 22. The first partition structure 11 includes a top surface and a bottom surface opposite each other in a direction perpendicular to the plane of the display panel, and a side surface connecting the top and bottom surfaces. The side surface of the first partition structure 11 has a groove. The anode layer 5 has a groove located at the top of the first partition structure 11 in the partition area 22. The second partition structure 12, the first partition structure 11, and the second partition structure 12 constitute the partition portion 10. The cross-sectional structure of the partition portion 10 can be mushroom-shaped. The display panel has a base layer 201 in the partition area 22, and the partition portion 10 is a protruding structure relative to the base layer 201. The light-emitting layer 6 in the partition area 22 includes a first portion 61 located on the surface of the partition portion 10 and a second portion 62 located on the surface of the base layer 201 outside the partition portion 10. There is a gap between the first portion 61 and the second portion 62 in a direction perpendicular to the plane of the display panel, so that the light-emitting layer 6 is broken at the edge of the partition portion 10 in the partition area 22. The planarization layer 4 can be made of organic material, and the anode layer 5 can be a metal material or a composite film layer of metal and other materials. In the display area 1, the planarization layer 4 is used to provide a planarized surface for the anode layer 5 to facilitate light extraction, and the cathode layer 7 is used to provide electrons for the light-emitting layer 6. The base layer 201 located in the partition region 22 can be formed as a portion of the film layer in the circuit layer 3, or as a portion of the film layer below the circuit layer 3, for example, in Figure 5 and Figure 6In the structure shown, the base layer 201 includes a flexible substrate layer 20 and a buffer layer 30 located in the partition area 22. The specific composition of the base layer 201 is not limited in the embodiments of this application.

[0031] Specifically, the partition 10 can be a dam or retaining wall structure extending along the edge of the opening 21, used to block the light-emitting layer 6 in the partition area 22, so that a continuous film layer from the opening 21 to the display area 1 cannot be formed. The number of partitions 10 can be one or more. In this embodiment, the number of partitions 10 is not limited. For example, for a circular opening 21, partitions 10 can be provided around it, that is, in the partition area 22. If there are multiple partitions 10, that is, each partition 10 forms an annular structure around the opening 21, multiple annular partitions 10 around the opening 21 are formed. During the manufacturing process of the display panel, the light-emitting layer 6 is fabricated after the partition portion 10 is completed. Therefore, in the partition area 22, since the partition portion 10 forms a protrusion relative to the base layer 201, during the formation of the light-emitting layer 6, in the partition area 22, the first portion 61 of the light-emitting layer 6 is formed at the top of the partition portion 10, and the second portion 62 is formed on the surface of the base layer 201 outside the partition portion 10. This causes the first portion 61 at the top of the partition portion 10 and the second portion 62 outside the partition portion 10 to be separated due to the protrusion difference of the partition portion 10 itself. Furthermore, since the side of the first partition structure 11 has a groove, it further hinders the connection between the first portion 61 of the light-emitting layer 6 at the top of the partition portion 10 and the second portion 62 of the light-emitting layer 6 outside the partition portion 10, enhancing the separation effect of the light-emitting layer 6 at the edge of the partition portion 10. By separating the light-emitting layer 6, it is possible to prevent water and oxygen from the opening 21 from intruding through the light-emitting layer 6 and extending to the display area 1, causing black spot problems. The portion of planarization layer 4 in display area 1 needs to be patterned to form vias. Electrical connections between the anode layer 5 and the circuitry in the circuitry layer 3 are achieved through these vias. Therefore, during the patterning of planarization layer 4, protrusions can be simultaneously formed in partition area 22 (the protrusions are used to form the first partition structure 11 in subsequent processes). Then, the anode layer 5 is fabricated. The portion of anode layer 5 in display area 1 needs to be patterned to form the anode pattern corresponding to each light-emitting device. Therefore, during the patterning of anode layer 5, protrusions can be simultaneously formed in partition area 22. The pattern of the second partition structure 12 is formed in the break region 22. Then, using the structure of the second partition structure 12 as a mask, the sides of the protruding structure are etched with oxygen to form inward grooves on the sides, thus forming the first partition structure 11, i.e., the partition portion 10. It can be seen that most of the patterning etching process for the partition portion 10 is achieved through the same patterning process as the corresponding film layer in the display area 1, requiring only additional etching of the sides of the first partition structure 11. Therefore, the fabrication process of the partition portion 10 is relatively simple, time-consuming, and easy to control. Figure 1Compared to the first related technology shown, the thickness of the second partition structure 12 in this embodiment is the same as the thickness of the anode in the light-emitting device, which is larger and less prone to collapse; and the overall thickness of the planarization layer 4 and the anode layer 5 in the partition portion 10 is larger, making it less likely for the light-emitting layer 6 to form a slope at the edge of the partition portion 10, thus preventing partition failure, and can more effectively improve the partitioning effect on the light-emitting layer 6. Figure 2 Compared to the second related technology shown, in the embodiments of this application, the main patterning process of the partition 10 can be manufactured using the same communication process as the patterning process of the display area 1 itself. Only the sides of the first partition structure 11 need to be etched additionally, thus the process is less time-consuming. Figure 3 Compared with the third related technology shown, in the embodiment of this application, the fabrication of the side groove of the first partition structure 11 can be carried out by using the second partition structure 12 as a mask for oxygen etching. The process control is less difficult, and it is easier to fabricate the required groove so as to improve the isolation effect on the light-emitting layer 6.

[0032] The display panel in this embodiment utilizes a planarization layer to create a first partition structure around the opening, and an anode layer to create a second partition structure on top of the first partition structure. The first partition structure has grooves on its sides. The partition formed by the first and second partition structures effectively isolates the light-emitting layer, improving its isolation effect and thus enhancing its barrier effect against water and oxygen, thereby mitigating the black spot problem caused by water and oxygen intrusion into the display area. The partition structure created using the planarization layer and the anode layer has a relatively large thickness, making it less prone to collapse and less likely to form a slope of the light-emitting layer at the edges, resulting in a better isolation effect on the light-emitting layer. The manufacturing process is also faster and less difficult to control.

[0033] In some embodiments of this application, the depth of the groove on the side of the first partition structure 11 is L, which can be in the range of 0.8μm≤L≤1.2μm. The groove depth L on the side of the first partition structure 11 has a significant impact on the isolation effect of the light-emitting layer 6. Through experiments, if the groove depth L is less than 0.8μm, it is easy for the light-emitting layer 6 to form a ramp on the side of the partition portion 10 during the subsequent fabrication of the light-emitting layer 6. This could cause the light-emitting layer 6 at the top of the partition portion 10 and the light-emitting layer 6 outside the partition portion 10 to be connected through the ramp on the side. On the other hand, after the partition portion 10 and the light-emitting layer 6 are fabricated, an encapsulation layer 8 is fabricated. In the partition area 22, the encapsulation layer 8 covers the partition portion 10 to further block the intrusion and transmission of water and oxygen. If the groove depth L on the side of the first partition structure 11 is greater than 1.2μm, the corner of the encapsulation layer 8 at the groove on the side of the first partition structure 11 is larger and more prone to cracking, thereby reducing the encapsulation and isolation effect. Therefore, in this embodiment, the side groove depth L of the first partition structure 11 has a range of 0.8μm≤L≤1.2μm, which improves the blocking effect on the light-emitting layer 6 on the one hand, and reduces the probability of the encapsulation layer 8 cracking at the groove on the other hand, thereby improving the encapsulation isolation effect.

[0034] In some embodiments of this application, the thickness of the first partition structure 11 is H, which can range from 1.5μm ≤ H ≤ 2.5μm. The thicknesses in these embodiments refer to the dimension perpendicular to the plane of the display panel. If the thickness H of the first partition structure 11 is too small, the encapsulation layer 8 may have a poor covering and filling effect; if the thickness H of the first partition structure 11 is too large, the overall thickness of the display panel may be too large, which is not conducive to improving space utilization. Therefore, in these embodiments, the rear end H of the first partition structure 11 has a moderate range, controlling the overall thickness of the display panel while ensuring that the encapsulation layer 8 effectively covers and fills the area around the first partition structure 11.

[0035] In some embodiments of this application, the partition portion 10 extends along the edge of the opening 21, and the width of the partition portion 10 is W, which can be in the range of 10μm≤W≤15μm. The width W of the partition portion 10 refers to the dimension of the partition portion 10 perpendicular to its extension direction.

[0036] In some embodiments of this application, the thickness of the second partition structure 12 is h, which can range from 100nm ≤ h ≤ 120nm. The relatively large thickness of the second partition structure 12 makes it less prone to collapse.

[0037] In other embodiments of this application, the display panel may include a plurality of partition portions 10, wherein the spacing between any two adjacent partition portions 10 is M, and 10μm≤M≤15μm. If the spacing between the partition portions 10 is too small, the first partition structure 11 of the organic material is not easily cleaned away, and residues may remain between the partition portions 10, thereby adversely affecting the partitioning effect of the light-emitting layer 6. If the spacing between the partition portions 10 is too large, the overall space utilization rate is low, and the number of partition portions 10 that can be set in the limited space is small, which may also adversely affect the partitioning effect of the light-emitting layer 6. Therefore, setting the spacing to 10μm≤M≤15μm makes it easier to clean the organic material between the partition portions 10, improves the adverse effect on the partitioning effect of the light-emitting layer 6 caused by residues, and improves the space utilization rate.

[0038] In some embodiments of this application, such as Figure 8 As shown, circuit layer 3 includes a semiconductor layer 31, a gate insulating layer 32, a gate metal layer 33, a capacitor dielectric layer 34, a capacitor metal layer 35, an interlayer insulating layer 36, and a source / drain metal layer 37 stacked sequentially. The gate metal layer 33 and / or the capacitor metal layer 35 have a raised structure 9 in the isolation region 22. That is, the raised structure 9 can be formed by the gate metal layer 33 or by the capacitor metal layer 35, or by both the gate metal layer 33 and the capacitor metal layer 35. The raised structure 9 is located below the isolation portion 10. An inorganic layer 91 can be disposed between the raised structure 9 and the planarization layer 4. The inorganic layer 91 can be one or more of the gate insulating layer 32, the capacitor dielectric layer 34, and the interlayer insulating layer 36. A raised structure 9 is provided below the partition portion 10, but not outside the partition portion 10. This is to increase the step difference between the light-emitting layer 6 at the top of the partition portion 10 and the light-emitting layer 6 outside the partition portion 10, thereby improving the isolation effect of the light-emitting layer 6. Since the source / drain metal layer 37 is adjacent to the planarization layer 4, it is difficult to implement the raised structure using the source / drain metal layer 37. Therefore, the raised structure 9 can be formed using the gate metal layer 33 or the capacitor metal layer 35.

[0039] Specifically, the semiconductor layer 31 is used to form the channel pattern of the transistor and the wiring pattern in the circuit; the gate insulating layer 32 can be made of silicon oxide (SiO2) with a thickness of, for example, 120 nm, to achieve insulation between the transistor gate and the semiconductor layer 31; the gate metal layer 33 can be made of molybdenum (Mo) with a thickness of, for example, 220 nm, to form the gate pattern of the transistor and the lower electrode pattern of the capacitor. In embodiments where the raised structure 9 is not required, the gate metal layer 33 can be removed in the isolation region 22; in embodiments where the raised structure 9 is required, the isolation region 22 can retain only the gate metal layer 33 pattern used to form the raised structure 9; the capacitor dielectric layer 34 can be made of silicon nitride (SiN).x The thickness is, for example, 130 nm, serving as the capacitor dielectric; the capacitor metal layer 35 can be made of metallic Mo, with a thickness of, for example, 220 nm, used to form the upper electrode pattern of the capacitor. In embodiments where the raised structure 9 is not required, the capacitor metal layer 35 can be removed from the partition region 22. In embodiments where the raised structure 9 is required, the partition region 22 can retain only the pattern of the capacitor metal layer 35 used to form the raised structure 9; the interlayer insulating layer 36 can be a composite film layer, for example, a silicon oxide (SiO2) film layer with a thickness of 300 nm at the bottom and a silicon nitride (SiN) film layer at the top. x The film layer, with a thickness of 200 nm, includes an interlayer insulating layer 36 that insulates the gate of the transistor from the source / drain metal layer 37 and provides H atoms to fill defects in the polysilicon channel of the semiconductor layer 31. The source / drain metal layer 37 can be a composite film of titanium (Ti), aluminum (Al), and titanium (Ti), with thicknesses of 50 nm, 650 nm, and 50 nm respectively. That is, the Ti layer is 50 nm thick, the Al layer is 650 nm thick, and the source / drain metal layer 37 forms metal traces to provide current to the anode of the light-emitting device and control its brightness. The source / drain metal layer 37 can be removed in the isolation region 22. Figure 8 In the structure shown, the base layer 201 includes a flexible substrate layer 20, a buffer layer 30, and an inorganic layer 91 located in the partition area 22.

[0040] In one possible implementation, such as Figure 9 As shown, the display panel includes a cathode layer 7 located on the side of the light-emitting layer 6 away from the anode layer 5 in the display area 1, and an encapsulation layer 8 located on the side of the cathode layer 7 away from the light-emitting layer 6. The encapsulation layer 8 includes a first encapsulation inorganic layer 81, an inkjet printing layer 80, and a second encapsulation inorganic layer 82 stacked sequentially. The display panel has an inkjet printing partition 13 in the partition area 22, where the inkjet printing layer 80 extends from the display area 1 to the inkjet printing partition 13. The partition 10 includes an outer partition 101 and an inner partition 101. 102. The inkjet printing partition 13 is located between the outer partition 101 and the inner partition 102. The inner partition 102 is located between the inkjet printing partition 13 and the display area 1. The outer partition 101 is located between the opening 21 and the inkjet printing partition 13. The first encapsulation inorganic layer 81, the inkjet printing layer 80, and the second encapsulation inorganic layer 82 cover the inner partition 102. The first encapsulation inorganic layer 81 and the second encapsulation inorganic layer 82 cover the outer partition 101. The inkjet printing layer 80 does not overlap with the outer partition 101.

[0041] Specifically, the material of the first encapsulation inorganic layer 81 can be silicon oxynitride (SiON), and the thickness can range from 0.8 μm to 1 μm (inclusive). The material of the second encapsulation inorganic layer 82 can be silicon nitride (SiN). xThe thickness ranges from 1 μm to 1.2 μm (inclusive). The first encapsulation inorganic layer 81 and the second encapsulation inorganic layer 82 are used to ensure that the light-emitting device and the cathode are not invaded by water and oxygen. The first encapsulation inorganic layer 81 and the second encapsulation inorganic layer 82 cover the partition area 22, forming a good encapsulation barrier effect. The inkjet printing layer 80 is an organic material with a thickness range from 10 μm to 12 μm (inclusive). The inkjet printing layer 80 is used to achieve planarization and a certain degree of foreign matter encapsulation, improving the encapsulation performance. The inkjet printing partition 13 is used to prevent the inkjet printing layer 80 from overflowing, achieving a better edge encapsulation effect.

[0042] In one possible implementation, the anode layer 5 comprises indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) stacked sequentially. The thicknesses of the three layers can be 10 nm, 100 nm, and 7 nm, respectively, in the direction from bottom to top, i.e., from the direction gradually away from the circuit layer 3.

[0043] In one possible implementation, the display panel further includes a flexible substrate layer 20 located on the side of the circuit layer 3 away from the planarization layer 4, the flexible substrate layer 20 covering the display area 1 and the partition area 22.

[0044] In one possible implementation, the flexible substrate layer 20 includes a first polyimide layer, a barrier layer, an amorphous silicon layer, and a second polyimide layer stacked sequentially.

[0045] Specifically, the thickness of the first polyimide layer can be 10±1 μm, the isolation layer can be SiO2 material with a thickness of, for example, 650 nm, the thickness of the amorphous silicon a-Si layer can be 5 nm, and the thickness of the second polyimide layer can be 10±1 μm. Additionally, a buffer layer 30 can be disposed between the flexible substrate layer 20 and the circuit layer 3; the buffer layer 30 can be SiN. x Composite film of SiN and SiO2, wherein SiN x The film thickness can be 200 nm, and the SiO2 film thickness can be 350 nm. Additionally, in display area 1, a pixel definition layer 40 (PDL) is disposed between the planarization layer 4 and the light-emitting layer 6. The pixel definition layer 40 is used to form patterned openings, each opening corresponding to a light-emitting device, defining the light-emitting area. The thickness of the pixel definition layer 40 is, for example, between 1.5 μm and 2 μm (inclusive). The thickness of the light-emitting layer 6 can be 300 nm. The cathode layer 7 can be made of a magnesium-silver-Ag alloy, and its thickness is, for example, 12 nm.

[0046] The following describes the display panel in the embodiments of this application through a complete display panel manufacturing method:

[0047] Step S1: Clean the glass substrate and coat the surface of the glass substrate with PI material with a thickness of 10±1um to form the first polyimide layer in the flexible substrate layer 20;

[0048] Step S2: On the first polyimide layer, an isolation layer barrier and an amorphous silicon a-Si film are sequentially deposited using plasma-enhanced chemical vapor deposition (PECVD). The barrier can be a SiO2 film with a thickness of 650 nm, and the a-Si (amorphous silicon) film can be 5 nm thick. In the subsequent process of peeling off the glass substrate, it can absorb the energy of laser lift-off (LLO) and prevent damage to the transistors.

[0049] Step S3: Continue coating the PI layer with a thickness of 10±1um to form the second polyimide layer in the flexible substrate layer 20;

[0050] Step S4: Deposit a buffer layer 30 on the PI using PECVD technology. The buffer layer 30 is SiN. x The composite film layers with SiO2 have thicknesses of 200nm and 350nm, respectively, which can provide heat preservation for the subsequent excimer laser annealing (ELA) process. The isolation layer and buffer layer 30 can also isolate Na+ and K+ ions in the glass substrate.

[0051] Step S5: Deposit an amorphous silicon layer using PECVD and perform hydrogen removal treatment (450℃, 2 hours), followed by ELA process to realize the conversion of amorphous silicon to polycrystalline silicon, i.e., to form semiconductor layer 31.

[0052] Step S6: Expose, develop, and etch the polysilicon to achieve patterning of the thin film transistor (TFT) channel and the wiring.

[0053] Step S7: Deposit a gate insulating layer 32 using PECVD. The material is SiO2 and the thickness is 120nm, which serves as the gate insulating layer.

[0054] Step S8: Deposit a gate metal layer 33 using a sputtering process. The material is Mo metal with a thickness of 220nm. Then perform exposure, development and etching to form gate and capacitor electrode patterns, which can serve as the lower electrode of the TFT gate and capacitor. Remove the Mo metal at the edge of the opening 21.

[0055] Step S9: Deposit capacitor dielectric layer 34 using PECVD, the material being SiN. x It has a thickness of 130nm and serves as the dielectric layer for capacitors.

[0056] Step S10: Deposit a capacitor metal layer 35 using the Sputter process. The material is Mo metal with a thickness of 220nm. Then perform exposure, development and etching to form the upper electrode of the storage capacitor. However, remove the Mo metal at the edge of the opening 21.

[0057] Step S11: Deposit an interlayer insulating layer 36 using PECVD technology. The interlayer insulating layer 36 is a composite film layer, with a SiO2 film layer at the bottom and a SiN film layer at the top. x The film, with a thickness of 200 nm, is then subjected to hydrogenation treatment (350 degrees Celsius, 2 hours). The interlayer insulating layer 36 can be used to repair dangling bonds on the polycrystalline silicon surface.

[0058] Step S12: Etch the interlayer insulating layer 36 to form the via required for the TFT, and then deposit the source drain metal layer 37. The source drain metal layer 37 is a Ti, Al, Ti composite film with thicknesses of 50 nm, 650 nm, and 50 nm, respectively.

[0059] Step S13: After the source / drain metal layer 37 is deposited, exposure etching and development are performed to form a metal trace pattern. The source / drain metal layer 37 is removed at the edge of the opening 21.

[0060] Step S14: After the source / drain metal layer 37 is deposited, a planarization layer 4 is coated and exposed and developed (thickness 1.5-2µm). An anode via is formed in the display area 1, as shown below. Figure 10 As shown, an annular planarization layer 4 with protrusions is formed in the partition region 22. The protrusion width W is 10-15 μm, the gap M is 10-15 μm, and the height H is 1.5-2.5 μm. Figure 10 The display panel is fabricated on the glass substrate 50;

[0061] Step S15: After the planarization layer 4 is coated and patterned, the anode layer 5 is formed. The anode layer material is an ITO / AG / ITO composite material with thicknesses of 10 nm, 100 nm, and 7 nm, respectively. After deposition, etching and patterning are performed to complete the anode fabrication. Figure 11 As shown, ITO / AG / ITO is also deposited and patterned in the partition region 22 to form a second partition structure 12 in the shape of a column mushroom head;

[0062] Step S16: After the second partition structure 12 supported by ITO / AG / ITO material is fabricated, the planarization layer 4 of the partition region 22 is side-etched using oxygen etching gas, with the second partition structure 12 as a self-aligned mask. The side etching width is 0.8-1.2 mm (photoresist is applied to the display region 1 during etching to avoid adverse effects on the structure of the display region 1). A groove is formed on the side of the protrusion of the planarization layer 4, forming a groove like... Figure 12 The diagram shows a first partition structure 11, and a second partition structure 12 forming a partition portion 10.

[0063] Step S17: Coating, exposing, and developing the pixel definition layer 40 with a thickness of 1.5-2 μm; the opening area formed by etching the pixel definition layer 40 is the light-emitting area.

[0064] Step S18: Coating, exposing, and developing a pixel spacer (PS) layer (not shown in the figure) with a thickness of 2µm. The PS layer serves to support the ultra-fine metal mask (FMM) during the subsequent evaporation of the light-emitting layer 6, so that the light-emitting layer 6 can be fabricated based on the FMM in subsequent processes.

[0065] Step S19: After the PS layer is fabricated, the normal evaporation of the light-emitting layer 6 is performed to form the light-emitting layer 6 and the cathode layer 7. The cathode layer 7 can be made of Mg / Ag alloy. The thickness of the light-emitting layer 6 is 300nm and the thickness of the cathode layer 7 is 12nm. Subsequently, the optical coupling layer (CPL) and LiF (CPL and LiF are not shown in the figure) are deposited. CPL is an organic layer, whose main function is to adjust the refractive index to maximize the light emission efficiency. LiF is an inorganic salt, which mainly plays the role of electromagnetic shielding.

[0066] Step S20: Then, a first encapsulation inorganic layer 81 is deposited. The first encapsulation inorganic layer 81 is made of SiON material and has a thickness of 0.8-1 μm. Subsequently, an inkjet printing layer 80 is coated and cured. The inkjet printing layer 80 is made of organic material and has a thickness of 10-12 μm. Finally, a second encapsulation inorganic layer 82 is deposited. The material is SiNx and the thickness is 1-1.2 μm. The stack of the first encapsulation inorganic layer 81 and the second encapsulation inorganic layer 82 covers the partition portion 10 in the partition region 22. At this point, the entire display panel manufacturing process is completed. The glass substrate can be peeled off from the display panel using LLO to form a flexible display panel.

[0067] This application also provides an electronic device, including the display panel in any of the above embodiments. The specific structure and principle of the display panel are the same as those in the above embodiments, and will not be repeated here. The electronic device can be any product or component with display function, such as a monitor, mobile phone, television, tablet computer, navigator, watch, or bracelet.

[0068] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the existence of A alone, the simultaneous existence of A and B, or the existence of B alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0069] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, include: A display area and an opening area, wherein the opening area includes an opening and a partition area, and the partition area is located between the opening and the display area; The display panel includes a circuit layer, a planarization layer, an anode layer, and a light-emitting layer stacked sequentially in the display area, wherein the planarization layer is made of an organic material; The planarization layer has a first partition structure in the partition area. The first partition structure includes a top surface and a bottom surface opposite each other in a direction perpendicular to the plane of the display panel, and a side surface connecting the top surface and the bottom surface. The side surface of the first partition structure has a groove. The anode layer has a second partition structure located at the top of the first partition structure in the partition area, and the first partition structure and the second partition structure constitute a partition portion; The display panel has a base layer in the partition area, and the partition portion is a raised structure relative to the base layer; The light-emitting layer in the partition area includes a first portion located on the surface of the partition portion and a second portion located on the surface of the base layer outside the partition portion, and there is a gap between the first portion and the second portion in a direction perpendicular to the plane where the display panel is located; The first part and the base layer have a first partition structure and a second partition structure stacked together; The second part is in direct contact with the base layer.

2. The display panel according to claim 1, characterized in that, The depth of the groove on the side of the first partition structure is L, 0.8μm≤L≤1.2μm.

3. The display panel according to claim 1, characterized in that, The thickness of the first partition structure is H, where 1.5μm≤H≤2.5μm.

4. The display panel according to claim 1, characterized in that, The partition extends along the edge of the opening, and the width of the partition is W, 10μm≤W≤15μm.

5. The display panel according to claim 1, characterized in that, The thickness of the second partition structure is h, where 100nm ≤ h ≤ 120nm.

6. The display panel according to claim 1, characterized in that, include: The plurality of partitions are provided, and the distance between any two adjacent partitions is M, where 10μm≤M≤15μm.

7. The display panel according to claim 1, characterized in that, The circuit layer includes a semiconductor layer, a gate insulating layer, a gate metal layer, a capacitor dielectric layer, a capacitor metal layer, an interlayer insulating layer, and a source / drain metal layer stacked sequentially. The gate metal layer and / or the capacitor metal layer have a raised structure in the partition region, and the raised structure is located below the partition portion.

8. The display panel according to claim 1, characterized in that, The display panel further includes a cathode layer located on the side of the light-emitting layer away from the anode layer in the display area, and an encapsulation layer located on the side of the cathode layer away from the light-emitting layer. The encapsulation layer includes a first encapsulation inorganic layer, an inkjet printing layer, and a second encapsulation inorganic layer stacked sequentially. The display panel has an inkjet-printed partition in the partition area, and the inkjet-printed layer extends from the display area to the inkjet-printed partition in the partition area. The partition includes an outer partition and an inner partition. The inkjet-printed partition is located between the outer partition and the inner partition. The inner partition is located between the inkjet-printed partition and the display area. The outer partition is located between the opening and the inkjet-printed partition. The first encapsulation inorganic layer, the inkjet-printed layer, and the second encapsulation inorganic layer cover the inner partition. The first encapsulation inorganic layer and the second encapsulation inorganic layer cover the outer partition. The inkjet-printed layer does not overlap with the outer partition.

9. The display panel according to claim 1, characterized in that, The anode layer comprises indium tin oxide, silver, and indium tin oxide stacked sequentially.

10. The display panel according to claim 1, characterized in that, Also includes: A flexible substrate layer located on the side of the circuit layer away from the planarization layer, the flexible substrate layer covering the display area and the partition area.

11. The display panel according to claim 10, characterized in that, The flexible substrate layer includes a first polyimide layer, an isolation layer, an amorphous silicon layer, and a second polyimide layer stacked sequentially.

12. An electronic device, characterized in that, Includes the display panel as described in any one of claims 1 to 11.

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