FPGA-based sidelobe cancellation stream processing method and phased array radar sidelobe cancellation system

Abstract

The application discloses a sidelobe cancellation stream processing method based on FPGA and a phased array radar sidelobe cancellation system. The sidelobe cancellation stream processing method based on FPGA comprises the following steps: instantiating a first complex multiplier IP core in FPGA, which is one more than the auxiliary array antenna, to calculate the covariance matrix and the covariance vector of the received interference signal vector; instantiating a second complex multiplier IP core in FPGA, which is the same as the number of the auxiliary array antennas, to calculate the determinant of the covariance matrix and the determinant of the combination matrix of the covariance matrix and the covariance vector by using the determinant calculation rule, and then calculate the sidelobe cancellation value and output the signal. The sidelobe cancellation stream processing method based on FPGA reduces the time consumed in the data transmission process and improves the real-time performance. Meanwhile, the complex matrix operation and the floating point operation are simplified in the FPGA, and the precision requirement of the processing is ensured.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a sidelobe cancellation flow processing method based on FPGA and a phased array radar sidelobe cancellation system. Background Art

[0002] Radar adaptive sidelobe cancellation utilizes an auxiliary antenna array to receive interference signals, adaptively calculate the interference direction and power, and then adjust the main antenna's receive pattern to position the null point in the interference direction. The auxiliary array's main lobe pattern is optimized to be as wide as possible, slightly larger than the main antenna's first sidelobe, thereby achieving better interference suppression. The principle of sidelobe cancellation requires complex and floating-point matrix operations. In engineering implementations, processors such as DSPs are often used as the primary processing unit, with FPGAs serving as data buffers and transmission interfaces. However, current mainstream processing approaches suffer from several issues: When using DSPs for processing, inter-chip transmission of echo data is time-consuming, making it difficult to process and output large amounts of data within a single radar cycle, especially during short radar cycle times. Furthermore, the response interrupt time after data transmission is unstable, resulting in poor real-time output of processing results. FPGAs offer strong real-time performance, but their complexity in floating-point and matrix operations makes them less user-friendly than DSPs. In summary, the real-time processing of adaptive sidelobe cancellation is a critical issue that needs to be addressed urgently. Summary of the Invention

[0003] The embodiment of the present invention provides a sidelobe cancellation flow processing method based on FPGA and a phased array radar sidelobe cancellation system, which are used to solve the real-time processing problem of adaptive sidelobe cancellation in the prior art.

[0004] The sidelobe cancellation flow processing method based on FPGA according to an embodiment of the present invention includes:

[0005] Instantiate n+1 first complex multiplier IP cores in the FPGA, and calculate the covariance matrix M and covariance vector S based on the n+1 first complex multiplier IP cores according to formula 1-2:

[0006]

[0007]

[0008] Among them, X0(k) represents the main antenna interference signal vector in the kth interference sampling, X i (k) represents the interference signal vector of the i-th auxiliary antenna in the k-th interference sampling, X j (k) represents the jth auxiliary antenna interference signal vector in the kth interference sampling, k∈[1,K], K is the number of interference sampling points, i,j∈[1,n], n is the number of auxiliary antennas, For X j The conjugate matrix of (k), For X i (k) conjugate matrix;

[0009] Instantiate n second complex multiplier IP cores in the FPGA, and based on the n second complex multiplier IP cores, use the determinant calculation rule to calculate the determinant |M| of M, and calculate |S according to Formula 3 1M |,|S 2M |,…,|S nM |:

[0010]

[0011] In the FPGA, based on the |M| and the |S 1M |,|S 2M |, ..., |S nM |, calculate the sidelobe cancellation value W according to formula 4, and based on W, perform stream processing weighting according to formula 5 to output signal Z:

[0012]

[0013] Where μ is a constant, ||M|| 2 is the square of |M|;

[0014] Z=X0-W T X N , Formula 5,

[0015] Among them, X0 is the echo signal vector of the main antenna, X N =[X1 X2 … X n ] T is the echo signal matrix of the auxiliary array, W T is the transposed matrix of W.

[0016] According to some embodiments of the present invention, the method further comprises:

[0017] Before instantiating the n+1 first complex multiplier IP cores in the FPGA, calculate the average power P of the main antenna interference signal according to formula 6-7. Z and the average power of the auxiliary array interference signal P F :

[0018]

[0019]

[0020] Determine the P Z and the P F Does P satisfyZ <P F If so, execute the instantiation of n+1 first complex multiplier IP cores in the FPGA; otherwise, perform main lobe protection.

[0021] According to some embodiments of the present invention, the method further comprises:

[0022] Based on the interference sampling period, the main antenna and the auxiliary array are controlled to receive the interference signal, and the received interference signal is sampled and down-converted by the AD module to obtain the main antenna interference signal vector X0(k) and the auxiliary array interference signal matrix X(k) = [X1(k), X2(k), ..., X n (k)] T .

[0023] According to some embodiments of the present invention, the X0(k) and the X(k)=[X1(k), X2(k), ..., X n (k)] T Collected before the radar transmission period.

[0024] According to some embodiments of the present invention, the n second complex multiplier IP cores are any n of the n+1 first complex multiplier IP cores.

[0025] A phased array radar sidelobe cancellation system according to an embodiment of the present invention includes: an FPGA, wherein the FPGA is configured to:

[0026] Instantiate n+1 first complex multiplier IP cores, and calculate the covariance matrix M and covariance vector S based on the n+1 first complex multiplier IP cores according to formula 1-2:

[0027]

[0028]

[0029] Among them, X0(k) represents the main antenna interference signal vector in the kth interference sampling, X i (k) represents the interference signal vector of the i-th auxiliary antenna in the k-th interference sampling, X j (k) represents the jth auxiliary antenna interference signal vector in the kth interference sampling, k∈[1,K], K is the number of interference sampling points, i,j∈[1,n], n is the number of auxiliary antennas, For X j The conjugate matrix of (k), For X i (k) conjugate matrix;

[0030] Instantiate n second complex multiplier IP cores, and based on the n second complex multiplier IP cores, use the determinant calculation rule to calculate the determinant |M| of the M, and calculate |S according to Formula 3 1M |,|S 2M |, ..., |S nM |:

[0031]

[0032] Based on the |M| and the |S 1M |,|S 2M |, ..., |S nM |, calculate the sidelobe cancellation value W according to formula 4, and based on W, perform stream processing weighting according to formula 5 to output signal Z:

[0033]

[0034] Where μ is a constant, ||M 2 is the square of |M|;

[0035] Z=X0-W T X N , Formula 5,

[0036] Among them, X0 is the echo signal vector of the main antenna, X N =[X1 X2 … X n ] T is the echo signal matrix of the auxiliary array, W T is the transposed matrix of W.

[0037] According to some embodiments of the present invention, the FPGA is further configured to:

[0038] Before instantiating the n+1 first complex multiplier IP cores, calculate the average power P of the main antenna interference signal according to formula 6-7. Z and the average power of the auxiliary array interference signal P F :

[0039]

[0040]

[0041] Determine the P Z and the P F Does P satisfy Z <P F If so, execute the instantiation of n+1 first complex multiplier IP cores in the FPGA; otherwise, perform main lobe protection.

[0042] According to some embodiments of the present invention, the system further comprises:

[0043] A main antenna, for receiving interference signals based on an interference sampling period;

[0044] an auxiliary array, configured to receive an interference signal based on an interference sampling period;

[0045] The AD module is used to sample and down-convert the interference signals received by the main antenna and the auxiliary array to obtain the main antenna interference signal vector X0(k) and the auxiliary array interference signal matrix X(k) = [X1(k), X2(k), ..., X n (k)] T .

[0046] According to some embodiments of the present invention, the X0(k) and the X(k)=[X1(k), X2(k), ..., X n (k)] T Collected before the radar transmission period.

[0047] According to some embodiments of the present invention, the n second complex multiplier IP cores are any n of the n+1 first complex multiplier IP cores.

[0048] The embodiment of the present invention uses an FPGA to perform sidelobe cancellation processing, reducing the time consumed in data transmission and improving real-time performance. At the same time, complex matrix operations and floating-point operations are simplified in the FPGA while ensuring processing accuracy requirements.

[0049] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Various other advantages and benefits will become apparent to those skilled in the art by reading the detailed description of the embodiments below. The accompanying drawings are only for the purpose of illustrating preferred embodiments and are not to be considered as limiting the present invention. In the accompanying drawings:

[0051] Figure 1 This is a principle block diagram of a sidelobe cancellation flow processing method based on FPGA in an embodiment of the present invention;

[0052] Figure 2 Flowchart of a sidelobe cancellation flow processing method based on FPGA in an embodiment of the present invention;

[0053] Figure 3 1. This is a diagram of the sidelobe cancellation system architecture of a phased array radar according to an embodiment of the present invention;

[0054] Figure 4 2 is a timing diagram of sidelobe cancellation in an embodiment of the present invention. DETAILED DESCRIPTION

[0055] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art. In addition, in some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this specification.

[0056] The embodiment of the present invention proposes a sidelobe cancellation flow processing method based on FPGA. It can be understood that the sidelobe cancellation flow processing method of the embodiment of the present invention is completed based on FPGA. The sidelobe cancellation flow processing method based on FPGA of the embodiment of the present invention includes:

[0057] Instantiate n+1 first complex multiplier IP cores in the FPGA, and calculate the covariance matrix M and covariance vector S based on the n+1 first complex multiplier IP cores according to formula 1-2:

[0058]

[0059]

[0060] M is an n×n matrix, m ij is the element of M, S is the column matrix, s i is an element in S.

[0061] Among them, X0(k) represents the main antenna interference signal vector in the kth interference sampling, X i (k) represents the interference signal vector of the i-th auxiliary antenna in the k-th interference sampling, X j (k) represents the jth auxiliary antenna interference signal vector in the kth interference sampling, k∈[1,K], K is the number of interference sampling points, i,j∈[1,n], n is the number of auxiliary antennas, For X j The conjugate matrix of (k), For X i (k) conjugate matrix;

[0062] Instantiate n second complex multiplier IP cores in the FPGA, and based on the n second complex multiplier IP cores, use the determinant calculation rule to calculate the determinant |M| of M, and calculate |S according to Formula 3 1M |,|S 2M |, ..., |SnM |:

[0063]

[0064] In the FPGA, based on the |M| and the |S 1M |,|S 2M |, ..., |S nM |, calculate the sidelobe cancellation value W according to formula 4, and based on W, perform stream processing weighting according to formula 5 to output signal Z:

[0065]

[0066] Where μ is a constant, ||M|| 2 is the square of |M|;

[0067] Z=X0-W T X N , Formula 5,

[0068] Among them, X0 is the echo signal vector of the main antenna, X N =[X1 X2 … X n ] T is the echo signal matrix of the auxiliary array, W T is the transposed matrix of W.

[0069] The embodiment of the present invention uses an FPGA to perform sidelobe cancellation processing, reducing the time consumed in data transmission and improving real-time performance. At the same time, complex matrix operations and floating-point operations are simplified in the FPGA while ensuring processing accuracy requirements.

[0070] Based on the above embodiment, various modified embodiments are further proposed. It should be noted that, in order to simplify the description, only the differences from the above embodiment are described in each modified embodiment.

[0071] According to some embodiments of the present invention, the method further comprises:

[0072] Before instantiating the n+1 first complex multiplier IP cores in the FPGA, calculate the average power P of the main antenna interference signal according to formula 6-7. Z and the average power of the auxiliary array interference signal P F :

[0073]

[0074]

[0075] Determine the P Z and the P F Does P satisfy Z<P F If so, execute the instantiation of n+1 first complex multiplier IP cores in the FPGA; otherwise, perform main lobe protection.

[0076] According to some embodiments of the present invention, the method further comprises:

[0077] Based on the interference sampling period, the main antenna and the auxiliary array are controlled to receive the interference signal, and the received interference signal is sampled and down-converted by the AD module to obtain the main antenna interference signal vector X0(k) and the auxiliary array interference signal matrix X(k) = [X1(k), X2(k), ..., X n (k)] T .

[0078] According to some embodiments of the present invention, the X0(k) and the X(k)=[X1(k), X2(k), ..., X n (k)] T Collected before the radar transmission period.

[0079] According to some embodiments of the present invention, the n second complex multiplier IP cores are any n of the n+1 first complex multiplier IP cores.

[0080] A phased array radar sidelobe cancellation system according to an embodiment of the present invention includes: an FPGA, wherein the FPGA is configured to:

[0081] Instantiate n+1 first complex multiplier IP cores, and calculate the covariance matrix M and covariance vector S based on the n+1 first complex multiplier IP cores according to formula 1-2:

[0082]

[0083]

[0084] Among them, X0(k) represents the main antenna interference signal vector, X i (k) represents the interference signal vector of the i-th auxiliary antenna in the k-th interference sampling, X j (k) represents the jth auxiliary antenna interference signal vector in the kth interference sampling, k∈[1,K], K is the number of interference sampling points, i,j∈[1,n], n is the number of auxiliary antennas, For X j The conjugate matrix of (k), For X i (k) conjugate matrix;

[0085] Instantiate n second complex multiplier IP cores, and based on the n second complex multiplier IP cores, use the determinant calculation rule to calculate the determinant |M| of the M, and calculate |S according to Formula 3 1M |,|S 2M |,…,|S nM |:

[0086]

[0087] Based on the |M| and the |S 1M |,|S 2M |,…,|S nM |, calculate the sidelobe cancellation value W according to formula 4, and based on W, perform stream processing weighting according to formula 5 to output signal Z:

[0088]

[0089] Where μ is a constant, ||M|| 2 is the square of |M|;

[0090] Z=X0-W T X N , Formula 5,

[0091] Among them, X0 is the echo signal vector of the main antenna, X N =[X1 X2 … X n ] T is the echo signal matrix of the auxiliary array, W T is the transposed matrix of W.

[0092] According to some embodiments of the present invention, the FPGA is further configured to:

[0093] Before instantiating the n+1 first complex multiplier IP cores, calculate the average power P of the main antenna interference signal according to formula 6-7. Z and the average power of the auxiliary array interference signal P F :

[0094]

[0095]

[0096] Determine the P Z and the P F Does P satisfy Z <P F If so, execute the instantiation of n+1 first complex multiplier IP cores in the FPGA; otherwise, perform main lobe protection.

[0097] According to some embodiments of the present invention, the system further comprises:

[0098] A main antenna, for receiving interference signals based on an interference sampling period;

[0099] an auxiliary array, configured to receive an interference signal based on an interference sampling period;

[0100] The AD module is used to sample and down-convert the interference signals received by the main antenna and the auxiliary array to obtain the main antenna interference signal vector X0(k) and the auxiliary array interference signal matrix X(k) = [X1(k), X2(k), ..., X n (k)] T .

[0101] According to some embodiments of the present invention, the X0(k) and the X(k)=[X1(k), X2(k), ..., X n (k)] T Collected before the radar transmission period.

[0102] According to some embodiments of the present invention, the n second complex multiplier IP cores are any n of the n+1 first complex multiplier IP cores.

[0103] The following describes in detail the FPGA-based sidelobe cancellation stream processing method according to a specific embodiment with reference to the accompanying drawings. It should be understood that the following description is merely exemplary and should not be construed as a specific limitation of the present invention.

[0104] The FPGA-based sidelobe cancellation stream processing method of the present invention ensures the accuracy of interference sampling by designing timing signals to control the opening of the antenna receiving channel and perform interference sampling and echo sampling. Using an FPGA for sidelobe cancellation stream processing reduces the time consumed during data transmission and improves real-time performance. Furthermore, the FPGA simplifies complex matrix operations and floating-point calculations while ensuring processing accuracy requirements. Figure 1 The principle block diagram of sidelobe cancellation implemented in FPGA is given.

[0105] Specifically, refer to Figure 2 As shown, the sidelobe cancellation flow processing method based on FPGA in an embodiment of the present invention includes:

[0106] Step 1: The radar timing signal controls the main antenna and auxiliary array to open the receiving channel, receive the interference signal, and after sampling and down-conversion through the AD module, send it to the FPGA of the sidelobe cancellation SLC processing module.

[0107] Step 2: The sidelobe cancellation module (sidelobe cancellation SLC processing module) receives the interference signal data, stores it in the dual-port RAM, and determines whether the interference signal comes from the main antenna sidelobe direction, thereby performing mainlobe protection.

[0108] The radiation intensity of the auxiliary antenna is equivalent to the side lobe radiation intensity of the main antenna, that is, the intensity of an interference source received by the auxiliary antenna can represent the intensity received by the main antenna side lobe. Z (Main Antenna) and P F (auxiliary antenna) to indicate signal strength, when P Z ≥P F , it is considered that the interference comes from the main lobe of the antenna pattern, and the main lobe protection is performed to protect the real target signal in the main lobe. The program jumps to step 6 to run and output the result. Z <P F , it is considered that the interference comes from the side lobe of the antenna pattern, and the side lobe cancellation is performed, and the process of jumping to step 3 to start the weight calculation process. When receiving the interference sampling data, the pipeline input is sent to the complex multiplier and the average power is accumulated. The average power P of the main antenna interference signal is calculated according to formulas 1 and 2. Z and the average power of the auxiliary array interference signal P F :

[0109]

[0110]

[0111] Among them, X0(k) represents the main antenna interference signal vector in the kth interference sampling, X i (k) represents the interference signal vector of the i-th auxiliary antenna in the k-th interference sampling, i∈[1,n], k∈[1,K], where K is the number of interference sampling points and n is the number of auxiliary arrays.

[0112] Step 3 (Calculate complex covariance): According to the sidelobe cancellation value calculation formula 3, the optimal weight W = [W1, W2, ..., W n ] T ,

[0113] W=μM -1 S (3)

[0114] Where μ is an arbitrary constant, M is the covariance matrix of the interference signal of the auxiliary array, and S is the cross-correlation covariance vector of the interference signals of the main antenna and the auxiliary array, which are calculated by Formula 4 and Formula 5 respectively:

[0115]

[0116]

[0117] Where X(k) * is the conjugate matrix of X(k), X(k) Tis the transposed matrix of X(k). The covariance value of each term in the formula is recorded as m ij and s i , i,j∈[1,n]. The covariance matrix M and covariance vector S can be written in the form of formulas 6 and 7, where all the results are complex numbers.

[0118] M=(m ij ) n×n (6)

[0119] S=(s i ) n×1 (7)

[0120] Instantiate n+1 complex multiplier IP cores in the FPGA and calculate the covariance matrix through n cycles. In each cycle, the main antenna interference X0(k) and the auxiliary antenna interference [X1(k), X2(k), ..., X n (k)] are respectively used as the input a_tdata of each multiplier and remain unchanged during the entire calculation process. The input b_tdata of all multipliers are set to the conjugate of the auxiliary antenna interference [X1 * (k),X2 * (k),…,X n * (k)], that is, in the first loop, b_tdata of all complex multipliers is set to X1 * (k), b_tdata in the second loop is X2 * (k), and so on, in the Nth cycle b_tdata is X N * (k). Set two counters cnt_k∈[0,K-1] and cnt_n∈[0,n-1] to implement the pipeline control of the loop calculation. In a single loop, cnt_k is accumulated to the number of sampling points K and reset to zero. At the same time, cnt_k is used as the address of the dual-port RAM. Data is taken out one by one and input into the multiplier for pipeline complex multiplication calculation. The result s_tdata output by the multiplier is accumulated to obtain the covariance value m corresponding to Formula 6 and Formula 7. ij and s i After completing one cycle of calculation, cnt_n+1, b_tdata is replaced for the next cycle of calculation. The entire calculation process requires n complex multiplication and accumulation cycles from 0 to K, and the total time taken is about n*K FPGA working clocks.

[0121] Step 4 (Calculate the complex determinant): According to formula 3, it is necessary to calculate the inverse matrix M of the matrix M -1 In order to reduce the amount of calculation, Formula 3 is transformed to obtain MW=μS, and then Formula 8 is obtained through Gaussian elimination method.

[0122]

[0123] Among them, I N is a unit matrix of size n, |S nM | and |M| are matrices S nM and the determinant of M. The matrix S nM Defined by Equation 9.

[0124]

[0125] The determinant terms in Formula 9 are the results of the previous step. Instantiate n complex multiplier IP cores in the FPGA or reuse the multiplier in the previous step, and use the determinant calculation rule to calculate |S 1M |,|S 2M |, ..., |S nM | and |M|, the results are both complex numbers, and the calculation time is about 2n(n-1) clock cycles;

[0126] Step 5 (calculating complex division to obtain weight): In order to simplify the complex division operation in Formula 8, the complex division is implemented by using the method of converting the denominator into a real number using conjugate complex numbers. The weight W is shown in Formula 10.

[0127]

[0128] where ||M|| 2 is the square of the modulus of the determinant |M|, a real number. The final weights are obtained using the complex multiplier IP core in the FPGA, which is a set of complex vectors.

[0129] Step 6 (weighted output of echo signal): According to the receiving cycle given by the timing signal, the radar echo data is collected and the weighted output signal Z is processed according to formula 11:

[0130] Z=X0-W T X N (11)

[0131] Where X0 is the echo signal vector of the main antenna, X N =[X1 X2 … X n ] T is the echo signal matrix of the auxiliary array.

[0132] In step 2, the direction of the interference signal is determined. If the interference signal is in the main lobe of the main antenna pattern, main lobe protection is performed without sidelobe cancellation. The weight W is set to the Nth-order zero vector, and the output signal Z = X0. Conversely, if the interference signal is in the sidelobe of the main antenna pattern, sidelobe cancellation is performed, and the weight W calculated in step 5 is substituted into Equation 11 to output the signal Z.

[0133] Correspondingly, an embodiment of the present invention further proposes a phased array radar sidelobe cancellation system, such as Figure 3 As shown, the system includes a main antenna, an auxiliary antenna array, a sidelobe cancellation module, a timer module, and an AD sampling module. The timer module and the AD sampling module serve as auxiliary devices for the sidelobe cancellation module, and are used to receive and convert spatial signals and provide working timing signals.

[0134] The main antenna, each auxiliary antenna and AD sampling module receive the timing signal given by the timer, such as Figure 4 As shown, interference sampling and echo signal sampling are performed. To minimize the impact of the radar's own transmitted signal on sidelobe cancellation, the interference sampling period is set before the radar's transmit period to minimize its influence. The interference signal and echo signal are fed into the FPGA's sidelobe cancellation module as a data stream. The FPGA immediately initiates adaptive SLC weight calculation upon receiving the interference signal and completes the calculation before the echo data stream arrives. The weight calculation takes approximately nK+2n(n-1) clock cycles. If the FPGA clock is 100MHz, the number of interference sampling points is 100 (K=100), and there are three auxiliary antennas (N=3), the calculation takes approximately 2μs. Using the radar transmit period, the calculation fully meets the requirements. Tests on a phased array radar show that when the number of interference sampling points is greater than 20 and the number of auxiliary arrays is greater than or equal to the number of interference sources, the sidelobe cancellation effect is generally satisfactory. Increasing the number of points and auxiliary arrays does not significantly improve the gain. Finally, during the radar receive period, the echo data is weighted and output based on the mainlobe protection judgment result. The entire data is stream processed to avoid cross-cycle output of processed data, thus ensuring the real-time performance of the radar system.

[0135] Key points and pre-protection features of this invention include: 1. Sidelobe cancellation flow processing method in FPGA. 2. Calculation method for inverse matrix changes in FPGA implementation. 3. Mainlobe protection determination and processing method. 4. Sidelobe cancellation timing design.

[0136] The advantages of this invention are: 1. It avoids the time wasted in transferring data between different chips, improving processing timeliness and ensuring that processing results are output in the same cycle. 2. It simplifies complex matrix operations in FPGAs while ensuring processing accuracy requirements. 3. It demonstrates the feasibility and effectiveness of sidelobe cancellation for stream processing in FPGAs.

[0137] It should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0138] The contents not described in detail in the specification of the present invention belong to the common knowledge of professionals in this field.

[0139] The terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0140] Any reference signs placed between parentheses shall not be construed as limiting the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The use of the words first, second, and third, etc., is used to distinguish similar items and does not imply any order. These words may be interpreted as names.

[0141] "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

Claims

1. A sidelobe cancellation flow processing method based on FPGA, characterized in that: include: Instantiate n+1 first complex multiplier IP cores in the FPGA, and calculate the covariance matrix M and covariance vector S based on the n+1 first complex multiplier IP cores according to formula 1-2: Among them, X0(k) represents the main antenna interference signal vector in the kth interference sampling, X i (k) represents the interference signal vector of the i-th auxiliary antenna in the k-th interference sampling, X j (k) represents the jth auxiliary antenna interference signal vector in the kth interference sampling, k∈[1,K], K is the number of interference sampling points, i,j∈[1,n], n is the number of auxiliary antennas, For X j The conjugate matrix of (k), For X i (k) conjugate matrix; Instantiate n second complex multiplier IP cores in the FPGA, and based on the n second complex multiplier IP cores, use the determinant calculation rule to calculate the determinant |M| of M, and calculate |S according to Formula 3 1M |,|S 2M |, ..., |S nM |: In the FPGA, based on the |M| and the |S 1M |,|S 2M |, ..., |S nM |, calculate the sidelobe cancellation value W according to formula 4, and based on W, perform stream processing weighting according to formula 5 to output signal Z: Where μ is a constant, ||M|| 2 is the square of |M|; Z=X0-W T X N , Formula 5, Among them, X0 is the echo signal vector of the main antenna, X N =[X1 X2…X n ] T is the echo signal matrix of the auxiliary array, W T is the transposed matrix of W.

2. The method according to claim 1, wherein The method further comprises: Before instantiating the n+1 first complex multiplier IP cores in the FPGA, calculate the average power P of the main antenna interference signal according to formula 6-7. Z and the average power of the auxiliary array interference signal P F : Determine the P Z and the P F Does P satisfy Z <P F If so, execute the instantiation of n+1 first complex multiplier IP cores in the FPGA; otherwise, perform main lobe protection.

3. The method according to claim 1, wherein The method further comprises: Based on the interference sampling period, the main antenna and the auxiliary array are controlled to receive the interference signal, and the received interference signal is sampled and down-converted by the AD module to obtain the main antenna interference signal vector X0(k) and the auxiliary array interference signal matrix X(k) = [X1(k), X2(k), ..., X n (k)] T .

4. The method according to claim 3, wherein The X0(k) and the X(k)=[X1(k),X2(k),…,X n (k)] T Collected before the radar transmission period.

5. The method according to claim 1, wherein The n second complex multiplier IP cores are any n of the n+1 first complex multiplier IP cores.

6. A phased array radar sidelobe cancellation system, characterized in that: The device comprises an FPGA, wherein the FPGA is used for: Instantiate n+1 first complex multiplier IP cores, and calculate the covariance matrix M and covariance vector S based on the n+1 first complex multiplier IP cores according to formula 1-2: Among them, X0(k) represents the main antenna interference signal vector in the kth interference sampling, X i (k) represents the interference signal vector of the i-th auxiliary antenna in the k-th interference sampling, X j (k) represents the jth auxiliary antenna interference signal vector in the kth interference sampling, k∈[1,K], K is the number of interference sampling points, i,j∈[1,n], n is the number of auxiliary antennas, For X j The conjugate matrix of (k), For X i (k) conjugate matrix; Instantiate n second complex multiplier IP cores, and based on the n second complex multiplier IP cores, use the determinant calculation rule to calculate the determinant |M| of the M, and calculate |S according to Formula 3 1M |,|S 2M |,…,|S nM |: Based on the |M| and the |S 1M |,|S 2M |,…,|S nM |, calculate the sidelobe cancellation value W according to formula 4, and based on W, perform stream processing weighting according to formula 5 to output signal Z: Where μ is a constant, ||M|| 2 is the square of |M|; Z=X0-W T X N , Formula 5, Among them, X0 is the echo signal vector of the main antenna, X N =[X1 X2…X n ] T is the echo signal matrix of the auxiliary array, W T is the transposed matrix of W.

7. The system according to claim 6, wherein: The FPGA is also used for: Before instantiating the n+1 first complex multiplier IP cores, calculate the average power P of the main antenna interference signal according to formula 6-7. Z and the average power of the auxiliary array interference signal P F : Determine the P Z and the P F Does P satisfy Z <P F If so, instantiate n+1 first complex multiplier IP cores in the FPGA; otherwise, perform main lobe protection.

8. The system according to claim 6, wherein: The system further comprises: A main antenna, for receiving interference signals based on an interference sampling period; an auxiliary array, configured to receive an interference signal based on an interference sampling period; The AD module is used to sample and down-convert the interference signals received by the main antenna and the auxiliary array to obtain the main antenna interference signal vector X0(k) and the auxiliary array interference signal matrix X(k) = [X1(k), X2(k), ..., X n (k)] T .

9. The system according to claim 8, wherein The X0(k) and the X(k)=[X1(k),X2(k),…,X n (k)] T Collected before the radar transmission period.

10. The system according to claim 6, wherein: The n second complex multiplier IP cores are any n of the n+1 first complex multiplier IP cores.

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