Method, apparatus, system and storage medium for calibrating clock phases of multiple FPGAs

Abstract

The present application provides a method, apparatus, system, and storage medium for calibrating the clock phases of multiple FPGAs, where the multiple FPGAs include a first FPGA and a second FPGA. The method includes: obtaining a first clock signal applied to the first FPGA and a second clock signal applied to the second FPGA, where the first clock signal and the second clock signal have the same period; generating a synchronous clock signal based on the first clock signal and the second clock signal; receiving a phase calibration accuracy set by a user; determining a reference time length according to the period of the synchronous clock signal and the phase calibration accuracy; respectively determining, within a given time length, the number of reference time lengths passed by the first clock signal and the second clock signal as a first count value and a second count value; and generating and sending an instruction to modify the initial phase to the second FPGA based on the first count value and the second count value.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, and particularly to a method, device, system, and storage medium for calibrating the clock phases of multiple FPGAs. Background Art

[0002] In the field of integrated circuit verification, users can use a prototype verification platform to verify a logic system design. The logic system design to be tested and verified (e.g., a circuit design) can be referred to as a Design Under Test (DUT).

[0003] The design of the prototype verification platform is complex and has high compatibility requirements. Many active devices, such as clock switches (MUX) and buffers (Buffer), often need to be added on the clock transmission path. Due to differences in process, voltage, temperature (Process, Voltage, Temperature; PVT), etc., these active devices will have end-to-end clock skew (port-to-port skew) and device-to-device clock skew. The superposition of these clock skews causes a phase difference at the receiving end of the FPGA.

[0004] Users (e.g., verification engineers) often use multiple FPGAs in the prototype verification platform to verify the same logic system design. Moreover, as the scale of the DUT increases, more and more FPGAs are needed in the verification test. To ensure that the working clocks of multiple FPGAs for verifying the same DUT are synchronized, users need to calibrate the clock phases applied to these multiple FPGAs. At the same time, for different verification projects, the clock frequencies used by the DUT are different, which leads to the need to re-calibrate the clock phases of multiple FPGAs for each new verification project to ensure that the clocks of multiple FPGAs are still synchronized at the new clock frequency. Therefore, how to quickly and simply calibrate the clock phases of multiple FPGAs is an urgent problem to be solved in the verification field. Summary of the Invention

[0005] A first aspect of the present application provides a method for calibrating the clock phases of multiple FPGAs. The multiple FPGAs include a first FPGA and a second FPGA. The method includes: obtaining a first clock signal applied to the first FPGA and a second clock signal applied to the second FPGA, where the first clock signal and the second clock signal have the same period; generating a synchronous clock signal based on the first clock signal and the second clock signal, and the initial phase difference between the synchronous clock signal and the first clock signal is less than the initial phase difference between the synchronous clock signal and the second clock signal; receiving a phase calibration accuracy set by a user; determining a reference time length based on the period of the synchronous clock signal and the phase calibration accuracy; respectively determining the number of reference time lengths passed by the first clock signal and the second clock signal within a given time length as a first count value and a second count value; and generating and sending an instruction to modify the initial phase to the second FPGA based on the first count value and the second count value.

[0006] A second aspect of the present application provides an electronic control device, including: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic control device executes the method as described in the first aspect.

[0007] A third aspect of the present application provides a system for calibrating the clock phases of multiple FPGAs. The multiple FPGAs include a first FPGA and a second FPGA. The system includes: the electronic control device as described in the second aspect, the electronic control device being connected to the first FPGA and the second FPGA; a clock distribution device configured to be connected to the first FPGA and the second FPGA, and generate and respectively send a first clock signal and a second clock signal to the first FPGA and the second FPGA based on a source clock signal; multiple transmission lines, where the multiple transmission lines connecting the electronic control device to the first FPGA and the second FPGA are of equal length, and the multiple transmission lines connecting the clock distribution device to the first FPGA and the second FPGA are of equal length; and multiple interfaces for connecting the multiple transmission lines and the first FPGA and the second FPGA.

[0008] A fourth aspect of the present application provides a non-transitory computer-readable storage medium storing a set of instructions of a computer, and the set of instructions is used to cause the computer to execute the method as described in the first aspect when being executed.

[0009] A method, device, system, and storage medium for calibrating the clock phases of multiple FPGAs provided by this application determine the number of reference time lengths passed by the clock signals applied to each FPGA within a given time length to determine whether the clock signals are synchronized. If they are not synchronized, the clock signal with the longest delay is used as the reference clock signal, and the input delay of other clock signals is adjusted to synchronize the clock signals. The method provided by this application can quickly and simply calibrate the clock phases of multiple FPGAs. At the same time, the system provided by this application is applicable not only to the scenario of independent verification of a single prototype verification platform but also to the scenario of joint verification of multiple prototype verification platforms, and has universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To more clearly illustrate the technical solutions in this application or related technologies, the following will briefly introduce the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings in the following descriptions are only the embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 The structural schematic diagram of an exemplary electronic device according to an embodiment of this application is shown.

[0012] Figure 2A The schematic diagram of an exemplary calibration system according to an embodiment of this application is shown.

[0013] Figure 2B The schematic diagram of an exemplary clock distribution device according to an embodiment of this application is shown.

[0014] Figure 3A The schematic diagram of an exemplary process for calibrating the clock phase according to an embodiment of this application is shown.

[0015] Figure 3B The schematic diagram of another exemplary process for calibrating the clock phase according to an embodiment of this application is shown.

[0016] Figure 3C The schematic diagram of yet another exemplary process for calibrating the clock phase according to an embodiment of this application is shown.

[0017] Figure 4 The flowchart of an exemplary method for calibrating the clock phases of multiple FPGAs according to an embodiment of this application is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] To make the objectives, technical solutions, and advantages of this application clearer and more understandable, the following further details this application in combination with specific embodiments and with reference to the accompanying drawings.

[0019] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in this application shall have the ordinary meanings understood by those with ordinary skills in the field to which this application belongs. The "first", "second" and similar terms used in this application do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0020] As described above, as the scale of the design under test increases, more and more FPGAs need to be cascaded in the verification test. To ensure the smooth progress of the verification, the working clocks of these cascaded FPGAs need to be synchronized. In view of this, this application proposes a method for quickly and simply calibrating the clock phases of multiple FPGAs to ensure that the working clocks of multiple FPGAs are in a synchronized state.

[0021] Figure 1 FIG. shows a schematic structural diagram of an electronic device 100 according to an embodiment of the present application. The electronic device 100 may be an electronic device running a simulation system. As Figure 1 shown, the electronic device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Among them, the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively connected to each other inside the electronic device through the bus 110.

[0022] The processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. The processor 102 may be used to execute functions related to the technologies described in this application. In some embodiments, the processor 102 may further include multiple processors integrated as a single logic component. As Figure 1 shown, the processor 102 may include multiple processors 102a, 102b, and 102c.

[0023] The memory 104 may be configured to store data (for example, instruction sets, computer codes, intermediate data, etc.). In some embodiments, the simulation test system for simulating a test design may be a computer program stored in the memory 104. As Figure 1As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the method of calibrating the clock phases of multiple FPGAs in the present application) and data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard disk, a solid state drive (SSD), a flash memory, a memory stick, etc.

[0024] The network interface 106 may be configured to provide communication with other external devices to the electronic device 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination of the above. It can be understood that the type of the network is not limited to the above specific examples. In some embodiments, the network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0025] The peripheral interface 108 may be configured to connect the electronic device 100 to one or more peripheral devices to achieve information input and output. For example, the peripheral devices may include input devices such as a keyboard, a mouse, a touchpad, a touch screen, a microphone, various sensors, etc. and output devices such as a display, a speaker, a vibrator, an indicator light, etc.

[0026] The bus 110 may be configured to transmit information between various components of the electronic device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (a USB port, a PCI-E bus), etc.

[0027] It should be noted that although the above electronic device architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in the specific implementation process, the electronic device architecture may also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above electronic device architecture may also only include the components necessary for implementing the solution of the embodiments of the present application, and does not necessarily include all the components shown in the figure.

[0028] Figure 2A A schematic diagram of an exemplary calibration system 200 according to an embodiment of the present application is shown.

[0029] In the field of chip verification, users can use a prototype verification platform to verify the design of a logic system. The prototype verification platform can be the HuaPro P1 verification platform produced by Xinhua Zhang Co., Ltd.

[0030] In some embodiments, the calibration system 200 may include an electronic control device 201, a clock distribution device 203, multiple transmission lines, and multiple interfaces 2041, 2042, 2051, 2052.

[0031] The electronic control device 201 can be, for example Figure 1 the electronic device 100 shown. The electronic control device 201 can be connected to the FPGAs 204 and 205 that perform verification tasks through transmission lines respectively. The electronic control device 201 can acquire the clock signal CLK-1 applied to the FPGA 204 and the clock signal CLK-2 applied to the FPGA 205. The electronic control device 201 can generate a synchronization signal CLK-SYNC based on the clock signals CLK-1 and CLK-2, and send the synchronization signal CLK-SYNC to the FPGAs 204 and 205 through the transmission lines. Since no active devices are used on the clock transmission path of the synchronization signal CLK-SYNC, users can ensure that the phases of the synchronization signal CLK-SYNC to the FPGAs 204 and 205 are consistent by controlling the equal length of the two transmission lines connecting the electronic control device 201 and the FPGAs 204 and 205.

[0032] The clock source 202 can generate a source clock signal. The clock distribution device 203 can generate the clock signals CLK-1 and CLK-2 based on the source clock signal, and send the clock signals CLK-1 and CLK-2 to the FPGAs 204 and 205 respectively.

[0033] In some embodiments, the calibration system 200 can be used to calibrate the clock phases of multiple FPGAs in the same verification platform. At this time, the clock source 202 can reuse the clock source within the verification platform. In other embodiments, the calibration system 200 can include a clock source 202 and can be used to calibrate the clock phases of multiple FPGAs in different verification platforms. At this time, the clock source 202 can be a clock source independent of the verification platform, and is used to provide a source clock signal for the multiple FPGAs that need to be calibrated.

[0034] Figure 2B Shows a schematic diagram of an exemplary clock distribution device 203 according to an embodiment of the present application.

[0035] As Figure 2BAs shown, the clock distribution device 203 may include buffers 2031, 2032, and 2033 with a ratio of 1:2. Based on the source clock signal generated by the clock source 202, the clock distribution device 203 can generate the clock signal CLK-1 applied to the FPGA 204 and the clock signal CLK-2 applied to the FPGA 205. Since the clock signals CLK-1 and CLK-2 are generated based on the same source clock signal, the clock frequencies of the clock signals CLK-1 and CLK-2 can be consistent. Inside the clock distribution device 203, in order to exclude the influence other than the end-to-end clock offset of the buffers 2031, 2032, and 2033, the user can control the length of the transmission lines inside the clock distribution device 203. For example, the transmission lines from the buffer 2031 to the buffers 2032 and 2033 are of equal length.

[0036] Back to Figure 2A , similarly, in order to make the phase difference between the clock signals CLK-1 and CLK-2 at the receiving ends of the FPGAs 204 and 205 only come from the end-to-end clock offset of the buffers in the clock distribution device 203, the user can control the equal length of the two transmission lines connecting the clock distribution device 203 and the FPGAs 204 and 205.

[0037] The transmission lines and the FPGAs 204 and 205 can be connected through the interfaces 2041, 2042, 2051, and 2052.

[0038] As described above, the end-to-end clock offset in the buffer causes a certain phase difference between the clock signals CLK-1 and CLK-2 generated and distributed by the clock distribution device 203 to the FPGAs 204 and 205. In view of this, the present application proposes a method for quickly and simply calibrating the phases of the applied clock signals CLK-1 and CLK-2, so as to adjust the clock signals CLK-1 and CLK-2 to the synchronous state.

[0039] Figure 3A A schematic diagram showing an exemplary process 300 for calibrating the clock phase according to an embodiment of the present application is shown.

[0040] In some embodiments, the calibration system 200 can obtain the clock signals CLK-1 and CLK-2 applied to the FPGAs 204 and 205, where there is a phase difference TD1 between the clock signals CLK-1 and CLK-2. To meet the requirement of clock synchronization of the FPGAs 204 and 205, the phase difference TD1 should be within a phase calibration accuracy. Here, the phase calibration accuracy can be set by the user according to the needs of the actual verification task.

[0041] It should be noted that due to the inherent delay of the calibration system 200, the minimum value of the phase calibration accuracy can be determined by the inherent delay of the calibration system 200. For example, the inherent delay can be caused by the control accuracy of the electronic control device 201 for generating the synchronization signal CLK-SYNC (for example, the clock frequencies generated by any clock source cannot be guaranteed to be always consistent, and there will be a small fluctuation in the clock frequency, generally in ppm (parts per million), such as 10k ± 20 ppm, where 20 ppm is the control accuracy of the clock) and the control accuracy of multiple transmission lines in the calibration system 200.

[0042] The electronic control device 201 can generate a low-frequency and continuous synchronization clock signal CLK-SYNC based on the clock signals CLK-1 and CLK-2. The initial phase difference T11 between the synchronization clock signal CLK-SYNC and the clock signal CLK-1 is less than the initial phase difference T21 between the synchronization clock signal CLK-SYNC and the clock signal CLK-2. That is to say, the input delay of the clock signal CLK-1 is greater than the input delay of the signal CLK-2.

[0043] To determine whether the clock signals CLK-1 and CLK-2 are synchronized, a reference clock length is introduced here. In some embodiments, the electronic control device 201 can use the sum of the period of the synchronization clock signal CLK-SYNC and the phase calibration accuracy set by the user as a reference time length. The electronic control device 201 can use a counter to synthesize a time length consistent with the reference time length on the clock signals CLK-1 and CLK-2. For example, the frequency of CLK_SYNC can be 10000.05 Hz (i.e., the period is 99999.5 ns), the phase calibration accuracy set by the user is 0.5 ns, and the frequencies of the clock signals CLK-1 and CLK-2 can be 1 GHz (i.e., the period is 1 ns), then the counter can be set to 100000, so as to obtain a reference time length of 100000 ns on the clock signals CLK-1 and CLK-2.

[0044] In some embodiments, the period of the synchronization clock signal CLK-SYNC can be a fixed period, for example, it can be 10 kHz.

[0045] In some other embodiments, according to the requirements of different verification tasks, the FPGA operates at different clock frequencies, such as 1 MHz or 1 GHz. Thus, if a synchronous clock signal CLK-SYNC with a fixed period is always used, for a higher clock frequency, the counter needs to count a relatively large number of counts to obtain the reference time length. In view of this, the period of the synchronous clock signal CLK-SYNC can be a period associated with the period of the working clock of the FPGA. In some embodiments, the electronic control device 201 can pre-store a plurality of coefficients set by the user, and each of these plurality of coefficients corresponds to a working frequency range of the FPGA. For example, when the working clock of the FPGA is at a working frequency A, the electronic control device 201 can determine that the working frequency A is within the frequency range (A1, A2], and determine the coefficient a pre-stored corresponding to the frequency range (A1, A2]. At this time, the electronic control device 201 can determine the frequency of the synchronous clock signal CLK-SYNC as A / a based on the working frequency A and the coefficient a. Furthermore, the electronic control device 201 can control the number of counts of the counter when synthesizing a time length consistent with the reference time length on the clock signals CLK-1 and CLK-2, preventing the counter from having an overly large number of counts.

[0046] The starting times of the clock signals CLK-1 and CLK-2 can be recorded as the initial moments of the clock signals. The electronic control device 201 can respectively determine how many reference time lengths have passed within the time length from the initial moment to the moment corresponding to each rising edge of the synchronous clock signal CLK-SYNC for the clock signals CLK-1 and CLK-2. The number of reference time lengths corresponding to the clock signal CLK-1 can be recorded as the first count value, and the number of reference time lengths corresponding to the clock signal CLK-2 can be recorded as the second count value.

[0047] As Figure 3A shown, at the moment ① corresponding to the first rising edge of CLK-SYNC, within the time length from the initial moment to the moment ① of the clock signal CLK-1, 0 reference time lengths have passed, and the first count value is recorded as 0; within the time length from the initial moment to the moment ① of the clock signal CLK-2, 0 reference time lengths have passed, and the second count value is recorded as 0. Similarly, at the moment ② corresponding to the second rising edge of CLK-SYNC, within the time length from the initial moment to the moment ② of the clock signal CLK-1, 0 reference time lengths have passed, and the first count value is recorded as 0; within the time length from the initial moment to the moment ② of the clock signal CLK-2, 1 reference time length has passed, and the second count value is recorded as 1.

[0048] As can be seen, at time ②, the first count value and the second count value are different. The electronic control device 201 can determine that the phase difference TD1 between the clock signals CLK-1 and CLK-2 is greater than the phase calibration accuracy set by the user, and it is necessary to adjust the input delay of the clock signal CLK-2 to reduce the phase difference TD1 between the clock signals CLK-2 and CLK-1. Since the input delay of the clock signal CLK-1 is greater than the input delay of the clock signal CLK-2, the electronic control device 201 can send an instruction to increase the input delay of the clock signal CLK-2 to the FPGA 205. After receiving this instruction, the FPGA 205 can increase the input time delay of the clock signal CLK-2. For example, the FPGA of Xilinx Corporation can achieve picosecond (ps)-level delay control. It can be understood that for an FPGA that does not have the function of adjusting the input clock time delay, the user can adjust the input time delay by adding a controller connected to the FPGA, and this application does not limit this.

[0049] Figure 3B FIG. shows a schematic diagram of another process 310 for calibrating the clock phase according to an embodiment of the present application.

[0050] As Figure 3B shown, the initial phase difference T12 between the synchronous clock signal CLK-SYNC and the clock signal CLK-1 is less than the initial phase difference T22 between the synchronous clock signal CLK-SYNC and the clock signal CLK-2. That is to say, the input delay of the clock signal CLK-1 is greater than the input delay of the signal CLK-2. The phase difference between the clock signal CLK-1 and the clock signal CLK-2 can be TD2.

[0051] At time ① corresponding to the first rising edge of CLK-SYNC, within the time length from the initial time to time ① of the clock signal CLK-1, 0 reference time lengths have passed, and the first count value is recorded as 0; within the time length from the initial time to time ① of the clock signal CLK-2, 0 reference time lengths have passed, and the second count value is recorded as 0. Similarly, at time ② corresponding to the second rising edge of CLK-SYNC, within the time length from the initial time to time ② of the clock signal CLK-1, 0 reference time lengths have passed, and the first count value is recorded as 0; within the time length from the initial time to time ② of the clock signal CLK-2, 0 reference time lengths have passed, and the second count value is recorded as 0. At time ③ corresponding to the third rising edge of CLK-SYNC, within the time length from the initial time to time ③ of the clock signal CLK-1, 1 reference time length has passed, and the first count value is recorded as 1; within the time length from the initial time to time ③ of the clock signal CLK-2, 1 reference time length has passed, and the second count value is recorded as 1. And so on, until at time N corresponding to the Nth rising edge of CLK-SYNC, within the time length from the initial time to time N of the clock signal CLK-1, n reference time lengths have passed, and the first count value is recorded as n; within the time length from the initial time to time N of the clock signal CLK-2, n reference time lengths have passed, and the second count value is recorded as n. That is to say, within the time length from time ① corresponding to the first rising edge of the synchronous clock signal CLK-SYNC to time N corresponding to the Nth rising edge, the first count value is always equal to the second count value.

[0052] Since the length of each cycle of the synchronous clock signal CLK-SYNC differs from the reference time length by a phase calibration accuracy, as time goes by, there is a periodic change rule for the phase difference between the synchronous clock signal CLK-SYNC and the clock signal CLK-1, and its change period is the quotient of the reference time length and the phase calibration accuracy. Therefore, the value of N here can be an integer less than or equal to the quotient of the reference time length and the phase calibration accuracy. As long as the first count value and the second count value are always equal within the time length corresponding to the first rising edge to the Nth rising edge. Then, the first count value and the second count value will enter the next cycle within the time length corresponding to the (N + 1)th rising edge to the 2Nth rising edge and will also always be equal.

[0053] In response to the first count value and the second count value always being equal, the electronic control device 201 can determine that the phase difference TD2 between the clock signals CLK-1 and CLK-2 is less than or equal to the phase calibration accuracy set by the user, meeting the requirements of the verification task, and there is no need to adjust the input delay of the clock signal CLK-2.

[0054] Figure 3CA schematic diagram showing another process 320 for calibrating a clock phase according to an embodiment of the present application is shown.

[0055] For multiple clock signals to be calibrated, such as clock signals CLK-1, CLK-2, and CLK-3, the electronic control device 201 may determine the clock signal CLK-1 with the largest input delay among these three clock signals, that is, the initial phase difference between the synchronous clock signal CLK-SYNC and the clock signal CLK-1 is less than the initial phase difference between the synchronous clock signal CLK-SYNC and the clock signal CLK-2, and is also less than the initial phase difference between the synchronous clock signal CLK-SYNC and the clock signal CLK-3.

[0056] Referring to the calibration method as Figure 3A or Figure 3B described, the electronic control device 201 may perform calibration for the clock signals CLK-1 and CLK-2, and CLK-1 and CLK-3 respectively. By adjusting the input delays of the clock signals CLK-2 and CLK-3, the initial phase differences between CLK-2 and CLK-1 and between CLK-3 and CLK-1 are continuously reduced to within the phase calibration accuracy.

[0057] In this way, the calibration system 200 can quickly and simply calibrate the clock signals of multiple FPGAs by determining the number of reference time lengths passed by the clock signals within a given time length. By using the method of the present application, the calibration system 200 can not only calibrate the clock signals of multiple FPGAs in the same verification platform, but also calibrate the clock signals of multiple cascaded FPGAs in different verification platforms.

[0058] Since the verification platform can execute different verification tasks, in these different verification tasks, the FPGA may be at different working frequencies. When the FPGA switches from executing one verification task to executing the next verification task, or when the verification platform is restarted, the calibration system 200 can calibrate the working clock of the FPGA to ensure that the working clock of the FPGA executing the current verification task is in a synchronous state.

[0059] An embodiment of the present application provides a method for calibrating the clock phases of multiple FPGAs.

[0060] Figure 4 A flowchart of an exemplary method 400 for calibrating the clock phases of multiple FPGAs according to an embodiment of the present application is shown, where the multiple FPGAs may include a first FPGA and a second FPGA. The method 400 may be executed by the calibration system 200 as Figure 2A shown. The method 400 may include the following steps.

[0061] In step 401, the calibration system 200 may obtain a first clock signal applied to the first FPGA (e.g., Figure 2A the FPGA 204) (e.g., Figure 2A the clock signal CLK-1) and a second clock signal applied to the second FPGA (e.g., Figure 2A the FPGA 205) (e.g., Figure 2A the clock signal CLK-2). Since both the first clock signal and the second clock signal are generated based on the same source clock signal (e.g., Figure 2A the source clock signal generated by the clock source 202), the periods of the first clock signal and the second clock signal are the same.

[0062] In step 402, the calibration system 200 may generate a synchronous clock signal (e.g., Figure 3A 、 3B or the synchronous clock signal CLK-SYNC in 3C) according to the first clock signal and the second clock signal. The initial phase difference between the synchronous clock signal and the first clock signal (e.g., Figure 3A the phase difference T11 in) is less than the initial phase difference between the synchronous clock signal and the second clock signal (e.g., Figure 3A the phase difference T21 in).

[0063] In some embodiments, the period of the synchronous clock signal may be a fixed period (e.g., 10 kHz). Alternatively, in some other embodiments, the period of the synchronous clock signal may also be a period associated with the period of the first clock signal. For example, the calibration system 200 may obtain the period of the synchronous clock signal based on a quotient of the period of the first clock signal and corresponding coefficients according to multiple coefficients preset in the calibration system 200.

[0064] In step 403, the calibration system 200 may receive the phase calibration accuracy set by the user. The user may determine the phase calibration accuracy according to the actual needs of the verification task.

[0065] In some embodiments, the minimum value of the phase calibration accuracy may be determined by the control accuracy (e.g., 20 ppm) of the electronic control device 201 in the calibration system 200 for generating the synchronous clock signal and the length control accuracy of multiple transmission lines (e.g., Figure 2A the transmission lines connecting the electronic control device 201 to the FPGAs 204 and 205, the transmission lines connecting the clock distribution device 203 to the FPGAs 204 and 205) in.

[0066] In step 404, the calibration system 200 may determine a reference time length according to the period of the synchronous clock signal and the phase calibration accuracy (e.g., Figure 3A 、3B , the reference time length in 3C).

[0067] In some embodiments, the reference time length may be the sum of the period of the synchronous clock signal (e.g., the period of the synchronous clock signal CLK_SYNC is 99999.5 ns) and the phase calibration accuracy (e.g., 0.5 ns) (e.g., 100000 ns).

[0068] In step 405, the calibration system 200 may respectively determine the number of reference time lengths passed by the first clock signal and the second clock signal within a given time length as a first count value and a second count value.

[0069] In some embodiments, the given time length may be the time duration from the initial moment to the moment corresponding to the Nth rising edge of the synchronous clock signal. Among them, the initial moment may be the starting time of the clock signal (e.g., Figure 3A the initial moments of CLK-1 and CLK-2 in

[0070] Respectively determining the number of reference time lengths passed by the first clock signal and the second clock signal within the given time length as the first count value and the second count value may further include: at the Nth rising edge of the synchronous clock signal, the first clock signal from the initial moment to the moment corresponding to the Nth rising edge (e.g., Figure 3A moments ①, ②, Figure 3B moments ①, ②, N) of the time duration passed by the reference time length is the first count value (e.g., Figure 3A the first count values are 0, 0, Figure 3B the first count values 0, 0, n); at the Nth rising edge of the synchronous clock signal, the second clock signal from the initial moment to the moment corresponding to the Nth rising edge (e.g., Figure 3A moments ①, ②, Figure 3B moments ①, ②, N) of the time duration passed by the reference time length is the second count value (e.g., Figure 3A the second count values are 0, 1, Figure 3B the second count values 0, 0, n). Among them, the value of N may be an integer less than or equal to the quotient of the reference time length and the phase calibration accuracy. The specific counting method may refer to Figure 3A or Figure 3B for description, which will not be elaborated here.

[0071] In step 406, the calibration system 200 may generate and send an instruction to modify the initial phase to the second FPGA based on the first count value and the second count value. In some embodiments, in response to the first count value (e.g., Figure 3Athe first count value (e.g., 0) at time instant ② in Figure 3A is inconsistent with the second count value (e.g., 1) at time instant ② in Figure 2A Figure 2A , the calibration system 200 may determine that the phase difference between the first clock signal and the second clock signal (e.g., Figure 3A the phase difference TD1 in

[0072] In some embodiments, within the time duration from the time instant ① corresponding to the first rising edge of the synchronous clock signal CLK - SYNC to the time instant N corresponding to the Nth rising edge, the first count value is always equal to the second count value. The calibration system 200 may determine that the phase difference between the first clock signal and the second clock signal (e.g., Figure 2B the phase difference TD2 in

[0073] is less than the phase calibration accuracy set by the user, and further determine that there is no need to adjust the second clock signal. Figure 2A In some embodiments, the plurality of FPGAs further includes a third FPGA (not shown in Figure 3C Figure 3C ). The method may further include: The calibration system 200 may obtain a third clock signal (e.g., Figure 3C the clock signal CLK - 3 in

[0074]

[0074] ) applied to the third FPGA, where the initial phase difference between the synchronous clock signal and the first clock signal is less than the initial phase difference between the synchronous clock signal and the third clock signal. That is, the input delay of the first clock signal is greater than the input delay of the third clock signal. The calibration system 200 may determine the number of reference time lengths passed by the third clock signal within a given time length as the third count value. The calibration system 200 may generate and send an instruction to modify the initial behavior to the third FPGA based on the first count value and the third count value. Wherein, the given length may be the time duration from the initial time instant of the third clock signal (e.g.,

[0075] the initial time instant of CLK - 3 in Figure 1The electronic control device 100. The electronic control device 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to execute method 400.

[0076] The embodiment of the present application further provides a system for calibrating the clock phases of multiple FPGAs. The system may be Figure 2A the calibration system 200. The calibration system 200 may include an electronic control device (e.g., Figure 2A the electronic control device 201 in Figure 2A ), which is connected to the first FPGA (e.g., Figure 2A the FPGA 204 in Figure 2A ), and the second FPGA (e.g., Figure 2A the FPGA 205 in Figure 2A ); a clock distribution device (e.g., Figure 2A the clock distribution device 203 in

[0077] ), configured to be connected to the first FPGA and the second FPGA, and generate and respectively send a first clock signal (e.g., Figure 2A the clock signal CLK-1 in Figure 2A or Figure 2B the source clock signal) to the first FPGA and the second FPGA based on a source clock signal; a plurality of transmission lines, wherein the plurality of transmission lines connecting the electronic control device to the first FPGA and the second FPGA are of equal length, and the plurality of transmission lines connecting the clock distribution device to the first FPGA and the second FPGA are of equal length; and a plurality of interfaces (e.g.,

[0078] the interfaces 2041, 2042, 2051, 2052 in

[0079] ), for connecting the plurality of transmission lines to the first FPGA and the second FPGA.

[0077] In some embodiments, the source clock signal received by the clock distribution device may multiplex the source clock signal generated by the clock source within the verification platform. In other embodiments, the calibration system 200 may further include a clock source (e.g., Figure 2A the clock source 202 in Figure 2A or Figure 2B ), for generating the source clock signal (e.g.,

[0078] the source clock signal in

[0079] ). The clock source may be a clock source independent of the verification platform.

[0078] The embodiment of the present application further provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores a set of instructions of a computer, and the set of instructions is used to cause the electronic control device to execute method 400 when being executed.

[0079] Some embodiments of the present application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the acts or steps recited in the claims may be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain implementations, multitasking and parallel processing are also possible or may be advantageous.

[0080] Those of ordinary skill in the art should understand that: The discussion of any embodiment above is only exemplary and is not intended to imply that the scope of the present application (including the claims) is limited to these examples; Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present application as described above, and they are not provided in detail for the sake of brevity.

[0081] Although the present application has been described in connection with specific embodiments of the present application, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0082] The present application is intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A method for calibrating the clock phases of multiple FPGAs, wherein, The multiple FPGAs include a first FPGA and a second FPGA, and the method includes: Obtaining a first clock signal applied to the first FPGA and a second clock signal applied to the second FPGA, wherein the first clock signal and the second clock signal have the same period; Generating a synchronous clock signal based on the first clock signal and the second clock signal, and an initial phase difference between the synchronous clock signal and the first clock signal is less than an initial phase difference between the synchronous clock signal and the second clock signal; Receiving a phase calibration accuracy set by a user; Determining a reference time length according to a period of the synchronous clock signal and the phase calibration accuracy; Determining, within a given time length, the number of reference time lengths passed by the first clock signal and the second clock signal as a first count value and a second count value respectively; and Generating and sending an instruction to modify an initial phase to the second FPGA based on the first count value and the second count value.

2. The method according to claim 1, wherein The period of the synchronous clock signal is a fixed period or a period associated with the period of the first clock signal.

3. The method according to claim 1, wherein, The given time length is a duration from an initial moment to a moment corresponding to an Nth rising edge of the synchronous clock signal, and determining, within the given time length, the number of reference time lengths passed by the first clock signal and the second clock signal as the first count value and the second count value respectively further includes: At the Nth rising edge of the synchronous clock signal, the number of reference time lengths passed by the first clock signal within a duration from the initial moment to the moment corresponding to the Nth rising edge is the first count value; At the Nth rising edge of the synchronous clock signal, the number of reference time lengths passed by the second clock signal within a duration from the initial moment to the moment corresponding to the Nth rising edge is the second count value, where N is an integer less than or equal to a quotient of the reference time length and the phase calibration accuracy.

4. The method according to claim 3, wherein, The reference time length is a sum of the period of the synchronous clock signal and the phase calibration accuracy.

5. The method according to claim 4, wherein, Generating and sending an instruction to modify an initial phase to the second FPGA based on the first count value and the second count value further includes: In response to the first count value and the second count value being inconsistent, generating and sending an instruction to increase an input delay of the second clock signal to the second FPGA.

6. The method according to claim 1, wherein, The multiple FPGAs further include a third FPGA, and the method further includes: Obtaining a third clock signal applied to the third FPGA, wherein the initial phase difference between the synchronous clock signal and the first clock signal is less than the initial phase difference between the synchronous clock signal and the third clock signal; Determining, within the given time length, the number of reference time lengths passed by the third clock signal as a third count value; and Generating and sending an instruction to modify an initial phase to the third FPGA based on the first count value and the third count value.

7. An electronic control device, including: A memory for storing a set of instructions; And At least one processor, configured to execute the set of instructions to cause the electronic control device to perform the method according to any one of claims 1 to 6.

8. A system for calibrating clock phases of multiple FPGAs, the multiple FPGAs including a first FPGA and a second FPGA, the system comprising: The electronic control device according to claim 7, the electronic control device being connected to the first FPGA and the second FPGA; A clock distribution device, configured to be connected to the first FPGA and the second FPGA, and generate and respectively send a first clock signal and a second clock signal to the first FPGA and the second FPGA based on a source clock signal; Multiple transmission lines, wherein the multiple transmission lines connecting the electronic control device to the first FPGA and the second FPGA are of equal length, and the multiple transmission lines connecting the clock distribution device to the first FPGA and the second FPGA are of equal length; And Multiple interfaces for connecting the multiple transmission lines to the first FPGA and the second FPGA.

9. The system according to claim 8, further comprising: A clock source for generating the source clock signal.

10. The system according to claim 8 or 9, further comprising: The minimum value of the phase calibration accuracy is determined by the control accuracy of the electronic control device for generating the synchronous clock signal and the length control accuracy of the multiple transmission lines.

11. A non-transitory computer-readable storage medium storing a set of instructions for an electronic device, the set of instructions, when executed, causing the electronic device to perform the method according to any one of claims 1 to 6.

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