power-on reset circuit

Abstract

The application discloses a power-on reset circuit, comprising: a feedback voltage dividing unit connected between a first power supply and a second power supply, one of the first power supply and the second power supply being a power voltage, the feedback voltage dividing unit being used for voltage dividing the power voltage to generate a first sampling voltage and a second sampling voltage; a comparison unit comprising a first transistor and a second transistor, one end of the first transistor and the second transistor being connected with the second power supply, a control end of the first transistor being connected with the first sampling voltage, the first transistor being used for generating a first current according to the first sampling voltage, a control end of the second transistor being connected with the second sampling voltage, the second transistor being used for generating a second current according to the second sampling voltage, the first current and the second current being compared at a comparison node; and a shaping unit connected with the comparison node, the shaping unit being used for shaping a voltage of the comparison node to output a reset signal, effectively solving the problem that a traditional power-on reset circuit is sensitive to temperature, and avoiding the occurrence of false triggering in a chip power-on process.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a power-on reset circuit. Background Technology

[0002] As chip integration becomes increasingly sophisticated, System-on-Chip (SoC) integrated circuit designs integrate more and more functions onto a single chip. The Power-On-Reset (POR) circuit is an essential component of an SoC. During the initial startup phase of the entire system, it is necessary to maintain the stability of the internal circuitry of the chip and prevent logic loop corruption during power supply voltage rise. The POR circuit provides an internal power-on reset signal to ensure normal system startup. During normal system operation, if the power supply voltage is too low, it can automatically reset. During the power supply voltage rise, the POR signal remains low until it reaches the normal operating voltage, at which point it quickly flips to high. At this point, the chip begins initialization. Before initialization is complete, the internal components ignore external signals (including data transmission), and only the reset pin utilizes the internal POR signal for initialization.

[0003] However, because the semiconductor devices in the existing power-on reset circuit are quite sensitive to temperature changes, the output signal of the power-on reset circuit changes with temperature, which can easily cause the IC chip to switch from the reset state to the working state, resulting in the IC chip failing to work properly. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a zero-temperature-drift power-on reset circuit, which effectively solves the problem of temperature sensitivity of traditional power-on reset circuits, avoids false triggering during chip power-on, and ensures that the chip can be effectively reset after power-on.

[0005] According to an embodiment of the present invention, a power-on reset circuit is provided, comprising: a feedback voltage divider unit connected between a first power supply and a second power supply, wherein one of the first power supply and the second power supply is a power supply voltage, the feedback voltage divider unit being used to divide the power supply voltage to generate a first sampling voltage and a second sampling voltage; a comparison unit including a first transistor and a second transistor, one end of the first transistor and the second transistor being connected to the second power supply, the control terminal of the first transistor being connected to the first sampling voltage and being used to generate a first current based on the first sampling voltage, the control terminal of the second transistor being connected to the second sampling voltage and being used to generate a second current based on the second sampling voltage, the first current and the second current being compared at a comparison node; and a shaping unit connected to the comparison node, used to shape the voltage of the comparison node to output a reset signal.

[0006] Optionally, the feedback voltage divider unit includes: a first resistor, a second resistor, and a third transistor connected sequentially between the first power supply and the second power supply. The end of the second resistor closer to the third transistor is used to output the first sampled voltage, and the end of the second resistor farther from the third transistor is used to output the second sampled voltage. The control terminal of the third transistor is connected to the second sampled voltage.

[0007] Optionally, the size ratio of the first transistor, the second transistor, and the third transistor is m:1:1, where m is an integer greater than 1.

[0008] Optionally, the first transistor, the second transistor, and the third transistor operate in the subthreshold region.

[0009] Optionally, the comparison unit further includes a current mirror structure for mirroring the second current to the branch where the first current is located, and the comparison node is located in the branch where the first current is located.

[0010] Optionally, the current mirror structure includes a fourth transistor and a fifth transistor, the sources of the fourth transistor and the fifth transistor are connected to the first power supply, the gates of the fourth transistor and the fifth transistor are connected to each other and connected to the drain of the fifth transistor, the drain of the fourth transistor is connected to the branch of the first current, and the drain of the fifth transistor is connected to the branch of the second current.

[0011] Optionally, the first transistor, the second transistor, and the third transistor are NMOS transistors or NPN transistors, the voltage of the first power supply is the power supply voltage, and the voltage of the second power supply is the ground voltage.

[0012] Optionally, the fourth transistor and the fifth transistor are PMOS transistors.

[0013] Optionally, the first transistor, the second transistor, and the third transistor are PMOS transistors or PNP transistors, the voltage of the first power supply is ground voltage, and the voltage of the second power supply is power supply voltage.

[0014] Optionally, the fourth transistor and the fifth transistor are NMOS transistors.

[0015] In summary, the power-on reset circuit of this invention utilizes a feedback voltage divider unit to divide the power supply voltage to generate a sampling voltage that follows the changes in the power supply voltage. Then, a comparison unit converts the sampling voltage into a current for comparison, thereby obtaining a reset signal. By operating the transistors in the feedback voltage divider unit and the comparison unit in the subthreshold region to set the flip-off voltage point of the reset signal, the flip-off voltage can be easily set to be independent of temperature changes, achieving a zero-temperature-drift power-on reset circuit. This effectively solves the problem of temperature sensitivity in traditional power-on reset circuits, avoids false triggering during chip power-on, and ensures that the chip can be effectively reset after power-on. Attached Figure Description

[0016] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0017] Figure 1 The circuit diagram of a traditional power-on reset circuit is shown.

[0018] Figure 2 The output waveforms of a conventional power-on reset circuit at different temperatures are shown.

[0019] Figure 3 A circuit diagram of a power-on reset circuit according to an embodiment of the present invention is shown.

[0020] Figure 4 The output waveforms of the power-on reset circuit according to an embodiment of the present invention are shown at different temperatures.

[0021] Figure 5 A circuit diagram of a power-on reset circuit according to another embodiment of the present invention is shown. Detailed Implementation

[0022] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0023] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0024] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0025] In this application, the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal. When the MOSFET is in the on state, current flows from the first terminal to the second terminal. The first terminal, second terminal, and control terminal of the PMOS transistor are the source, drain, and gate, respectively, and the first terminal, second terminal, and control terminal of the NMOS transistor are the drain, source, and gate, respectively.

[0026] Figure 1 A circuit diagram of a traditional power-on reset circuit is shown. (For example...) Figure 1 As shown, the power-on reset circuit 100 includes resistors R1 and R2, an NMOS transistor M1, and an inverter INV1. The first terminal of resistor R1 is connected to the power supply voltage VDD, and the second terminal is connected to the drain of the NMOS transistor M1. The first terminal of resistor R2 is connected to the power supply voltage VDD, and the second terminal is connected to the gate of the NMOS transistor M1. The source of the NMOS transistor M1 is connected to ground. The input terminal of the inverter INV1 is connected to the drain of the NMOS transistor M1, and its output terminal is used to output the reset signal POR. During the rise of the power supply voltage VDD, VDD pulls point A high through resistor R1. Inverted by the inverter INV1, the reset signal POR is low. Simultaneously, VDD charges the gate capacitance of the NMOS transistor M1 through resistor R2. When the gate voltage of the NMOS transistor M1 exceeds the transistor's turn-on threshold, the NMOS transistor M1 turns on, pulling point A low, and the reset signal POR flips to a high level.

[0027] Figure 2The output waveforms of a conventional power-on reset circuit at different temperatures are shown, specifically the waveform changes of the reset signal POR at 125°C, 27°C, and -40°C. Figure 2 As shown, since the conduction threshold of NMOS transistor M1 changes with temperature, the trigger voltage of the high-level output of the traditional power-on reset circuit 100 will also be different at different temperatures. In practical applications, this may cause the IC chip to be falsely triggered, resulting in the IC chip failing to work properly.

[0028] Figure 3 A circuit diagram of a power-on reset circuit according to an embodiment of the present invention is shown. Figure 3 As shown, the power-on reset circuit 200 includes a feedback voltage divider unit 210, a comparison unit 220, and a shaping unit 230. The feedback voltage divider unit 210 is connected between a first power supply 201 and a second power supply 202. The first power supply 201 is connected to the power supply voltage VDD, and the second power supply 202 is connected to the reference ground voltage GND. The feedback voltage divider unit 210 is used to divide the power supply voltage VDD to generate a first sampling voltage Vs1 and a second sampling voltage Vs2. Specifically, the feedback voltage divider unit 210 includes resistors R1 and R2 and an NMOS transistor M1. The first end of resistor R1 is connected to the first power supply 201 (i.e., power supply voltage VDD). The second end of resistor R1 is connected to the first end of resistor R2. The second end of resistor R2 is connected to the drain of NMOS transistor M1. The source of NMOS transistor M1 is connected to ground GND. The end of resistor R2 closer to NMOS transistor M1 is used to output the first sampling voltage Vs1. The end of resistor R2 further away from NMOS transistor M1 is used to output the second sampling voltage Vs2. The gate of NMOS transistor M1 is connected to the second sampling voltage Vs2.

[0029] Comparison unit 220 includes NMOS transistors M2 and M3, and PMOS transistors M4 and M5. The sources of PMOS transistors M4 and M5 are connected to the first power supply 201 (i.e., power supply voltage VDD), and their gates are connected to the drain of PMOS transistor M5, forming a current mirror structure. The drain of NMOS transistor M2 is connected to the drain of PMOS transistor M4, its gate is connected to the first sampling voltage Vs1, and its source is connected to ground (GND). The drain of NMOS transistor M3 is connected to the drain of PMOS transistor M5, its gate is connected to the second sampling voltage Vs2, and its source is connected to ground (GND).

[0030] In this embodiment, NMOS transistor M2 is used to generate a first current I1 based on a first sampling voltage Vs1, NMOS transistor M3 is used to generate a second current I2 based on a second sampling voltage Vs2, and a current mirror composed of PMOS transistors M4 and M5 is used to mirror the second current I2 to the branch where the first current I1 is located. The first current I1 and the second current I2 are compared at comparison node A.

[0031] In this embodiment, the shaping unit 230 is connected to the comparison node A and is used to shape the voltage of the comparison node A to output a reset signal POR. Further, the shaping unit 230 includes cascaded inverters INV1 and INV2. The input terminal of inverter INV1 is connected to the comparison node A, and its output terminal is connected to the input terminal of inverter INV2. The output terminal of inverter INV2 is used to output the reset signal POR.

[0032] In this embodiment, the size ratio of NMOS transistors M1, M2, and M3 is 1:m:1, where m is an integer greater than 1. This ratio is determined by the width-to-length ratio (W / L) of the transistors, or, in the case of different numbers of unit transistors, by the number of unit transistors. For example, the size ratio of NMOS transistors M1 and M2 is 1:m. In one case, each of NMOS transistors M1 and M2 may include the same number of transistors, but the width-to-length ratio (M / L) of NMOS transistor M2 is m times that of NMOS transistor M1, where m is an integer greater than 1. In another case, NMOS transistors M1 and M2 may include different numbers of unit transistors, each with the same width-to-length ratio, but the number of unit transistors in NMOS transistor M2 may be m times the number of unit transistors in NMOS transistor M1.

[0033] In this embodiment, NMOS transistors M1, M2, and M3 operate in the subthreshold region. The subthreshold state is an important operating state (mode) of a MOSFET, also known as the MOSFET subthreshold region. This is an operating state where the MOSFET's gate voltage Vgs is below the threshold voltage VT, and no conductive channel appears (Vgs ≤ VT), with the surface potential approximately equal to the Fermi potential (i.e., weak inversion at the surface). Even in this state, a small current still flows through the device; this current is called the subthreshold current. Although the subthreshold current is small, it is well controlled by the gate voltage. Therefore, MOSFETs in the subthreshold state are advantageous in low-voltage, low-power applications, and are particularly valued in large-scale integrated circuit applications such as logic switches and memories.

[0034] When the transistor operates in the subthreshold region, the relationship between the current through the MOSFET and the overdrive voltage is as follows:

[0035]

[0036] Among them, I D I is the current of the MOSFET in the subthreshold state. D0 Where n is a constant, W and L are the width and length of the MOSFET, respectively, Veff is the overdrive voltage of the MOSFET, and n is a constant. T Where is the voltage with a positive temperature coefficient, and T is the absolute temperature.

[0037] When the power supply voltage VDD is 0, the reset signal POR output by the power-on reset circuit 200 is low. As the power supply voltage VDD gradually rises, because the size ratio of NMOS transistor M2 is larger than that of NMOS transistor M3, NMOS transistor M2 has a stronger overcurrent capability than NMOS transistor M3. Therefore, comparison node A is low, and the reset signal POR is also low. When the power supply voltage VDD rises to... At this point, NMOS transistors M2 and M3 have the same overcurrent capability. The gate voltage of NMOS transistor M2 is lower than that of NMOS transistor M3, and comparator node A is in a critical state of transition. As the power supply voltage VDD continues to rise, the overcurrent capability of NMOS transistor M2 will fall below that of NMOS transistor M3. At this point, comparator node A flips to a high level, and the reset signal POR flips to a high level. At the POR transition point of the reset chip, transistors M1, M2, and M3 all operate in the subthreshold region. GS2 With a negative temperature coefficient, V T It has a positive temperature coefficient; by adjusting the three parameters m, R1, and R2, the voltage combination can be adjusted. The value is adjusted to zero temperature coefficient.

[0038] In summary, the output switching voltage of the power-on reset circuit 200 in this embodiment is:

[0039]

[0040] Among them, V GS2 V is the gate-source voltage of NMOS transistor M2, n is a constant, m is the size ratio between NMOS transistors M2 and M3, and V is the gate-source voltage of NMOS transistor M2. T This is a positive temperature coefficient voltage, where R1 and R2 are the resistance values ​​of resistors R1 and R2, and this switching voltage does not change with temperature.

[0041] In some other embodiments, the NMOS transistors M1, M2 and M3 in the power-on reset circuit 200 can also be implemented by NPN transistors, and the present invention does not limit this.

[0042] Figure 4 The output waveforms of the power-on reset circuit according to an embodiment of the present invention are shown at different temperatures. Figure 4 As shown, in this embodiment, the trigger voltage of the reset signal POR remains approximately unchanged at temperatures of 125°C, 27°C and -40°C, and is not affected by different temperature environments.

[0043] Figure 5 A circuit diagram of a power-on reset circuit according to another embodiment of the present invention is shown. Figure 5 As shown, the power-on reset circuit 300 includes a feedback voltage divider unit 310, a comparison unit 320, and a shaping unit 330. The feedback voltage divider unit 310 is connected between a first power supply 301 and a second power supply 302. The first power supply 301 is connected to the reference ground voltage GND, and the second power supply 302 is connected to the power supply voltage VDD. The feedback voltage divider unit 310 is used to divide the power supply voltage VDD to generate a first sampling voltage Vs1 and a second sampling voltage Vs2. Specifically, the feedback voltage divider unit 310 includes resistors R1 and R2 and a PMOS transistor M1. The first end of resistor R1 is connected to the first power supply 301 (i.e., reference ground GND). The second end of resistor R1 is connected to the first end of resistor R2. The second end of resistor R2 is connected to the drain of PMOS transistor M1. The source of PMOS transistor M1 is connected to the power supply voltage VDD. The end of resistor R2 closer to PMOS transistor M1 is used to output the first sampling voltage Vs1. The end of resistor R2 further away from PMOS transistor M1 is used to output the second sampling voltage Vs2. The gate of PMOS transistor M1 is connected to the second sampling voltage Vs2.

[0044] Comparison unit 220 includes PMOS transistors M2 and M3, and NMOS transistors M4 and M5. The sources of NMOS transistors M4 and M5 are connected to the first power supply 301 (i.e., power supply voltage VDD), and their gates are connected to the drain of NMOS transistor M5, forming a current mirror structure. The drain of PMOS transistor M2 is connected to the drain of NMOS transistor M4, its gate is connected to the first sampling voltage Vs1, and its source is connected to ground (GND). The drain of PMOS transistor M3 is connected to the drain of NMOS transistor M5, its gate is connected to the second sampling voltage Vs2, and its source is connected to ground (GND).

[0045] In this embodiment, PMOS transistor M2 is used to generate a first current I1 based on a first sampling voltage Vs1, PMOS transistor M3 is used to generate a second current I2 based on a second sampling voltage Vs2, and a current mirror composed of NMOS transistors M4 and M5 is used to mirror the second current I2 to the branch where the first current I1 is located. The first current I1 and the second current I2 are compared at comparison node A.

[0046] In this embodiment, the shaping unit 330 is connected to the comparison node A and is used to shape the voltage of the comparison node A to output a reset signal POR. Further, the shaping unit 330 includes a cascaded inverter INV1, the input of which is connected to the comparison node A, and its output is used to output the reset signal POR.

[0047] In this embodiment, the size ratio of PMOS transistors M1, M2, and M3 is 1:m:1, where m is an integer greater than 1. This ratio is determined by the width-to-length ratio (W / L) of the transistors, or, in the case of different numbers of unit transistors, by the number of unit transistors. For example, if the size ratio of PMOS transistors M1 and M2 is 1:m, in one case, each of PMOS transistors M1 and M2 may include the same number of transistors, but the width-to-length ratio (M / L) of PMOS transistor M2 is m times that of PMOS transistor M1, where m is an integer greater than 1. In another case, PMOS transistors M1 and M2 may include different numbers of unit transistors, each with the same width-to-length ratio, but the number of unit transistors in PMOS transistor M2 may be m times the number of unit transistors in PMOS transistor M1.

[0048] Similarly, in this embodiment, PMOS transistors M1, M2 and M3 also operate in the subthreshold region. The subthreshold region of the transistors has been described in the above embodiments and will not be repeated here.

[0049] In some other embodiments, the PMOS transistors M1, M2 and M3 in the power-on reset circuit 300 can also be implemented by PNP transistors, and the present invention does not limit this.

[0050] In summary, the power-on reset circuit of this invention utilizes a feedback voltage divider unit to divide the power supply voltage to generate a sampling voltage that follows the changes in the power supply voltage. Then, a comparison unit converts the sampling voltage into a current for comparison, thereby obtaining a reset signal. By operating the transistors in the feedback voltage divider unit and the comparison unit in the subthreshold region to set the flip-off voltage point of the reset signal, the flip-off voltage can be easily set to be independent of temperature changes, achieving a zero-temperature-drift power-on reset circuit. This effectively solves the problem of temperature sensitivity in traditional power-on reset circuits, avoids false triggering during chip power-on, and ensures that the chip can be effectively reset after power-on.

[0051] It should be noted that although devices are described herein as N-channel or P-channel devices, or N-type or P-type doped regions, those skilled in the art will understand that complementary devices are also possible according to the present invention. Those skilled in the art will understand that conductivity type refers to the mechanism by which conductivity occurs, such as conduction through holes or electrons; therefore, conductivity type relates to doping type, such as P-type or N-type, rather than doping concentration. Those skilled in the art will understand that the terms “during,” “when,” and “when…” used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately at the start of a startup action, but rather that there may be one or more small but reasonable delays between the startup action and the reaction action initiated by it, such as various propagation delays. The terms “approximately” or “substantially” used herein mean that an element value has a parameter expected to be close to the declared value or location. However, as is well known in the art, there are always small deviations that make it difficult for the value or location to be strictly the declared value. It has been properly determined in the art that a deviation of at least 10 percent (10%) (or at least 20 percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive or negative logic is used.

[0052] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0053] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A power-on reset circuit, characterized in that, include: A feedback voltage divider unit is connected between a first power supply and a second power supply, one of which is a power supply voltage. The feedback voltage divider unit is used to divide the power supply voltage to generate a first sampling voltage and a second sampling voltage. The feedback voltage divider unit includes: a first resistor, a second resistor, and a third transistor connected sequentially between the first power supply and the second power supply. The end of the second resistor closer to the third transistor is used to output the first sampling voltage, and the end of the second resistor farther from the third transistor is used to output the second sampling voltage. The control terminal of the third transistor is connected to the second sampling voltage. The comparison unit includes a first transistor and a second transistor, the size ratio of the first transistor, the second transistor and the third transistor is m:1:1, where m is an integer greater than 1, and the first transistor, the second transistor and the third transistor operate in the subthreshold region. One end of the first transistor and the second transistor is connected to the second power supply. The control terminal of the first transistor is connected to the first sampling voltage and is used to generate a first current based on the first sampling voltage. The control terminal of the second transistor is connected to the second sampling voltage and is used to generate a second current based on the second sampling voltage. The comparison unit also includes a current mirror structure for mirroring the second current to the branch where the first current is located, and the comparison node is located in the branch where the first current is located. The first current and the second current are compared at the comparison node. as well as A shaping unit, connected to the comparison node, is used to shape the voltage of the comparison node to output a reset signal.

2. The power-on reset circuit according to claim 1, wherein, The current mirror structure includes a fourth transistor and a fifth transistor. The sources of the fourth and fifth transistors are connected to the first power supply. The gates of the fourth transistor and the fifth transistor are connected to each other, and the gates are also connected to the drain of the fifth transistor. The drain of the fourth transistor is connected to the branch of the first current, and the drain of the fifth transistor is connected to the branch of the second current.

3. The power-on reset circuit according to claim 2, wherein, The first transistor, the second transistor, and the third transistor are NMOS transistors or NPN transistors, the voltage of the first power supply is the power supply voltage, and the voltage of the second power supply is the ground voltage.

4. The power-on reset circuit according to claim 3, wherein, The fourth and fifth transistors are PMOS transistors.

5. The power-on reset circuit according to claim 2, wherein, The first transistor, the second transistor, and the third transistor are PMOS transistors or PNP transistors, the voltage of the first power supply is the ground voltage, and the voltage of the second power supply is the power supply voltage.

6. The power-on reset circuit according to claim 5, wherein, The fourth and fifth transistors are NMOS transistors.

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