A control method and system for embedded storage chip

Abstract

The present invention provides a control method and system for an embedded memory chip. The control method includes the following steps: obtaining input operation instructions and determining the type of the operation instructions to select different memory chips; and a control system for the embedded memory chip includes an EMMC module, a SOC module, a data bus, and an LPDDR module. By using an EMMC chip and an LPDDR chip to store operation codes and data, respectively, the present invention can effectively improve the performance of the embedded chip.

Description

Technical Field

[0001] The present invention relates to the field of chip control, and more particularly to a control method and system for an embedded memory chip. Background Art

[0002] With the continuous iteration of electronic products and the continuous enhancement of their functions, the requirements for chips are constantly increasing, which is generally reflected in the two aspects of high performance and low power consumption. However, due to technical aspects, the two cannot often be taken into account at the same time, but a balance needs to be made between the two.

[0003] Embedded memory chips are a type of memory chip that integrates various storage functions. The development of embedded chips is one of the important factors restricting the further development of embedded systems. The present invention aims to further improve the performance of embedded memory chips. Summary of the Invention

[0004] In order to further improve the performance of embedded memory chips, the present invention provides a control method for embedded memory chips, comprising the following steps:

[0005] S1: Configure the operation code register inside the EMMC chip and store the operation code of the operating system into the operation code register;

[0006] S2: Obtain the input operation instruction and determine the type of the operation instruction according to the operation instruction, which includes task scheduling instruction and data processing instruction;

[0007] S3: When the operation instruction is a task scheduling instruction, the SOC chip directly obtains the operation code from the code register inside the EMMC chip through the data bus according to the memory address inside the operation instruction;

[0008] S4: When the operation instruction is a data processing instruction, a data temporary register is configured inside the LPDDR chip. According to the memory address inside the operation instruction, the SOC chip directly obtains the operation code from the code register inside the EMMC chip through the data bus, processes the input data, and performs read / write operations on the data in the data temporary register.

[0009] As a preferred aspect, the invention further comprises the following steps:

[0010] T1: Configure weight registers in the EMMC chip;

[0011] T2: Monitor the input operation instructions. Whenever an operation code is obtained, match it in the weight register according to the memory address of the corresponding operation code. If the match fails, enter T3; if the match succeeds, enter T4;

[0012] T3: Store the memory address of the operation code, the number of bytes occupied by the corresponding operation code, and the weight value Wn in the weight register, where n=1, 2, 3...N, where N is the maximum number of operation codes; let Wn=1;

[0013] T4: Set the weight value corresponding to the operation code Wn=Wn+1;

[0014] T5: Arrange all weight values ​​Wn from large to small using the bubble sort method, and select the memory addresses of the operation codes corresponding to the first five weight values ​​Wn;

[0015] T6: Map the memory addresses of the operation codes corresponding to the first five weight values ​​Wn to the memory addresses corresponding to the LPDDR chip, and copy the operation codes in the operation code register inside the EMMC chip to the LPDDR chip according to the memory addresses and the number of bytes occupied by the corresponding operation codes;

[0016] T7: When the operation instruction is a task scheduling instruction, the SOC chip directly obtains the operation code from the LPDDR chip through the data bus according to the memory address inside the operation instruction.

[0017] As a preferred aspect, the method further comprises the steps of:

[0018] A1: When the LPDDR chip is powered off, all internal data is cleared.

[0019] A2: When the LPDDR chip is powered on again, the memory addresses corresponding to the first five weight values ​​Wn in the weight register are searched, and then the operation codes in the operation code register inside the EMMC chip are copied to the LPDDR chip according to the memory addresses and the number of bytes occupied by the corresponding operation codes.

[0020] As a preferred aspect, the method further comprises the steps of:

[0021] B1: Let k = 1;

[0022] B2: Calculate the size q of the space inside the LPDDR chip to store the operation code;

[0023] B3: Determine whether "q≤Q / 3" holds true, where Q is the total size of the internal storage space of the LPDDR chip. If "q≤Q / 3" holds true, set k=1; if "q≤Q / 3" does not hold true, proceed to B4;

[0024] B4: Arrange the five operation codes in the LPDDR chip in descending order according to byte size, select the first operation code, and delete it from the LPDDR chip;

[0025] B5: Select the (5+k)th operation code from the operation codes arranged in descending order by weight, map the memory address corresponding to the selected operation code to the memory address corresponding to the LPDDR chip, and copy the operation code in the operation code register inside the EMMC chip to the LPDDR chip based on the memory address and the number of bytes occupied by the corresponding operation code. Set k=k+1 and return to B2.

[0026] A control system for an embedded memory chip, comprising:

[0027] An EMMC module is used to carry an operation code register, and the operation code register is used to store an operation code;

[0028] The SOC module is used to obtain input operation instructions, classify the operation instructions, obtain operation codes and process data;

[0029] Data bus, used to transmit data;

[0030] The LPDDR module is used to carry a data temporary storage register, and the data temporary storage register is used to store data.

[0031] As a preferred aspect, the EMMC module is further used to carry a weight register, which is used to store the memory address of the operation code, the number of bytes occupied by the corresponding operation code, and the weight value:

[0032] The SOC module is further used to monitor input operation instructions and update the weight register;

[0033] The LPDDR module is further configured to store the first five operation codes arranged in descending order of weight.

[0034] As a preferred aspect, the SOC module is further used to calculate the size of the space for storing operation codes inside the LPDDR chip and update the operation codes stored inside the LPDDR chip.

[0035] As a preferred aspect, the EMMC module and the LPDDR module are vertically mounted on the SOC module.

[0036] The present invention has the following advantages:

[0037] 1. The present invention can effectively improve the performance of embedded chips by using EMMC chips and LPDDR chips to store operation codes and data respectively.

[0038] 2. The present invention copies the five commonly used operation codes into the LPDDR chip, allowing the SOC chip to obtain them from the LPDDR chip. By utilizing the high-speed transmission performance of the LPDDR chip, the commonly used operation codes can be quickly responded to, further improving the performance of the embedded memory chip.

[0039] 3. The present invention reloads the operation code of the LPDDR chip each time the power is turned on, thereby avoiding recalculating the weight of the operation code each time the power is turned on.

[0040] 4. In the present invention, when the size of the space for storing operation codes in the LPDDR chip exceeds 1 / 3 of the internal storage space of the LPDDR chip, the operation code that occupies the largest storage space in the LPDDR chip will be deleted, and the operation code that is used frequently and occupies the smallest storage space will be selected in order, so as to prevent the efficiency of data processing from being affected by the excessive storage space of the operation codes in the LPDDR chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is a flow chart of a control method for an embedded memory chip used in the present invention.

[0042] Figure 2 This is a flow chart of copying common operation codes to the LPDDR chip according to the present invention.

[0043] Figure 3 Schematic diagram of the flow of detecting the size of the internal storage space for operation codes according to the present invention.

[0044] Figure 4 The figure is a schematic structural diagram of a control system using an embedded memory chip according to the present invention. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0046] Example 1

[0047] The present invention provides a control method for an embedded memory chip, such as Figure 1 As shown, the following steps are included:

[0048] S1: Configure the operation code register inside the EMMC chip and store the operation code of the operating system into the operation code register;

[0049] S2: Obtain the input operation instruction, and determine the type of the operation instruction according to the operation instruction. The types include task scheduling instruction and data processing instruction. The operation instruction determines the type of the operation instruction by the data of the first bit. The data of the first bit is divided into 0 and 1. When the data of the first bit is 0, the operation instruction is a task scheduling instruction. The task scheduling instruction does not process the data but is only used to execute the corresponding function; when the data of the first bit is 1, the operation instruction is a data processing instruction. The data processing instruction is used to process data and needs to receive data;

[0050] S3: When the operation instruction is a task scheduling instruction, the SOC chip directly obtains the operation code from the code register inside the EMMC chip through the data bus according to the memory address inside the operation instruction, and the transmission method adopts ADAM;

[0051] S4: When the operation instruction is a data processing instruction, a data temporary register is configured inside the LPDDR chip. According to the memory address inside the operation instruction, the SOC chip directly obtains the operation code from the code register inside the EMMC chip through the data bus, processes the input data, and performs read / write operations on the data in the data temporary register.

[0052] EMMC chips (Embedded Multimedia Cards) are non-volatile memory that uses high-performance flash memory, offering high efficiency in reading and storing operation codes. LPDDR chips are synchronous dynamic random access memory (SDRAM) that are volatile and clear data when power is lost. Using LPDDR chips to store data allows for high-speed data read and write operations, while also clearing data when the LPDDR chip is powered off, eliminating any residual data. This is particularly effective in embedded systems that perform only a single operation. Using EMMC chips and LPDDR chips to store operation codes and data, respectively, can effectively improve the performance of embedded chips.

[0053] like Figure 2 As shown, the following steps are also included:

[0054] T1: Configure the weight register in the EMMC chip. The weight register is used to find the most commonly used operation code.

[0055] T2: Monitor the input operation instructions. Whenever an operation code is obtained, a match is performed in the weight register according to the memory address of the corresponding operation code. This match is one by one. If the match fails, enter T3; if the match succeeds, enter T4;

[0056] T3: Store the memory address of the operation code, the number of bytes occupied by the corresponding operation code, and the weight value Wn in the weight register, where n = 1, 2, 3...N, where N is the maximum number of operation codes; let Wn = 1, Wn is used to calculate the frequency of operation code use. A larger Wn indicates that the corresponding operation code is used more frequently.

[0057] T4: Set the weight value corresponding to the operation code Wn=Wn+1;

[0058] T5: Arrange all weight values ​​Wn from large to small using the bubble sort method, and select the memory addresses of the operation codes corresponding to the first five weight values ​​Wn;

[0059] T6: Map the memory addresses of the operation codes corresponding to the first five weight values ​​Wn to the memory addresses corresponding to the LPDDR chip, and copy the operation codes in the operation code register inside the EMMC chip to the LPDDR chip according to the memory addresses and the number of bytes occupied by the corresponding operation codes;

[0060] T7: When the operation instruction is a task scheduling instruction, the SOC chip directly obtains the operation code from the LPDDR chip through the data bus according to the memory address inside the operation instruction.

[0061] The present invention copies five commonly used operation codes into the LPDDR chip, allowing the SOC chip to obtain them from the LPDDR chip. By utilizing the high-speed transmission performance of the LPDDR chip, a fast response effect of commonly used operation codes is achieved, further improving the performance of the embedded memory chip.

[0062] As a preferred aspect, the method further comprises the steps of:

[0063] A1: When the LPDDR chip is powered off, all internal data is cleared.

[0064] A2: When the LPDDR chip is powered on again, the memory addresses corresponding to the first five weight values ​​Wn in the weight register are searched, and then the operation codes in the operation code register inside the EMMC chip are copied to the LPDDR chip according to the memory addresses and the number of bytes occupied by the corresponding operation codes.

[0065] The present invention reloads the operation code of the LPDDR chip each time the power is turned on, thereby avoiding recalculating the weight of the operation code each time the power is turned on.

[0066] like Figure 3 As shown, the following steps are also included:

[0067] B1: Let k = 1;

[0068] B2: Calculate the size q of the space inside the LPDDR chip to store the operation code;

[0069] B3: Determine whether "q≤Q / 3" holds true, where Q is the total size of the LPDDR chip's internal storage space. Determine whether the size of the LPDDR chip's internal storage space for operation codes exceeds 1 / 3 of the LPDDR chip's internal storage space. If "q≤Q / 3" holds true, set k=1. If "q≤Q / 3" does not hold true, proceed to B4.

[0070] B4: Arrange the five operation codes in the LPDDR chip in descending order according to byte size, select the first operation code, and delete it from the LPDDR chip;

[0071] B5: Select the (5+k)th operation code from the operation codes arranged in descending order by weight, map the memory address corresponding to the selected operation code to the memory address corresponding to the LPDDR chip, and copy the operation code in the operation code register inside the EMMC chip to the LPDDR chip based on the memory address and the number of bytes occupied by the corresponding operation code. Set k=k+1 and return to B2.

[0072] In the present invention, when the size of the space for storing operation codes within the LPDDR chip exceeds 1 / 3 of the internal storage space of the LPDDR chip, the operation code that occupies the most storage space within the LPDDR chip will be deleted, and the operation code that is used frequently and occupies the least storage space will be selected in order. This prevents the LPDDR chip from having too much space for storing operation codes, which affects data processing efficiency.

[0073] Example 2

[0074] A control system for an embedded memory chip, such as Figure 4 As shown, including:

[0075] An EMMC module, configured as an EMMC chip, is used to carry an operation code register, wherein the operation code register is used to store an operation code;

[0076] The SOC module is configured as a SOC chip and is used to obtain input operation instructions, classify the operation instructions, obtain operation codes and process data;

[0077] Data bus, used to transmit data;

[0078] The LPDDR module is configured as an LPDDR chip and is used to carry a data temporary storage register, and the data temporary storage register is used to store data.

[0079] The EMMC module and the LPDDR module are vertically mounted on the SOC module

[0080] As a preferred aspect, the EMMC module is further used to carry a weight register, which is used to store the memory address of the operation code, the number of bytes occupied by the corresponding operation code, and the weight value:

[0081] The SOC module is further used to monitor input operation instructions and update the weight register;

[0082] The LPDDR module is further configured to store the first five operation codes arranged in descending order of weight.

[0083] As a preferred aspect, the SOC module is further used to calculate the size of the space for storing operation codes inside the LPDDR chip and update the operation codes stored inside the LPDDR chip.

[0084] It should be understood that those skilled in the art may make improvements or modifications based on the above description, and all such improvements and modifications shall fall within the scope of protection of the appended claims. Any portion of this specification not described in detail is prior art known to those skilled in the art.

Claims

1. A control method for an embedded memory chip, characterized in that: The steps include: S1: Configure the operation code register inside the EMMC chip and store the operation code of the operating system into the operation code register; S2: Obtain an input operation instruction and determine the type of the operation instruction based on the operation instruction. The types include task scheduling instructions and data processing instructions. The task scheduling instructions do not process data but are only used to execute corresponding functions. The data processing instructions are used to process data and need to receive data. S3: When the operation instruction is a task scheduling instruction, the SOC chip directly obtains the operation code from the code register inside the EMMC chip through the data bus according to the memory address inside the operation instruction; S4: When the operation instruction is a data processing instruction, a data temporary register is configured inside the LPDDR chip. According to the memory address inside the operation instruction, the SOC chip directly obtains the operation code from the code register inside the EMMC chip through the data bus, processes the input data, and performs read / write operations on the data in the data temporary register.

2. The control method of an embedded memory chip according to claim 1, characterized in that: The following steps are also included: T1: Configure weight registers in the EMMC chip; T2: Monitor the input operation instructions. Whenever an operation code is obtained, match it in the weight register according to the memory address of the corresponding operation code. If the match fails, enter T3; if the match succeeds, enter T4; T3: Store the memory address of the operation code, the number of bytes occupied by the corresponding operation code, and the weight value Wn in the weight register, where n=1, 2, 3...N, where N is the maximum number of operation codes; Let Wn=1; T4: Set the weight value corresponding to the operation code Wn=Wn+1; T5: Arrange all weight values ​​Wn from large to small using the bubble sort method, and select the memory addresses of the operation codes corresponding to the first five weight values ​​Wn; T6: Map the memory addresses of the operation codes corresponding to the first five weight values ​​Wn to the memory addresses corresponding to the LPDDR chip, and copy the operation codes in the operation code register inside the EMMC chip to the LPDDR chip according to the memory addresses and the number of bytes occupied by the corresponding operation codes; T7: When the operation instruction is a task scheduling instruction, the SOC chip directly obtains the operation code from the LPDDR chip through the data bus according to the memory address inside the operation instruction.

3. The control method of an embedded memory chip according to claim 2, characterized in that: The following steps are also included: A1: When the LPDDR chip is powered off, all internal data is cleared. A2: When the LPDDR chip is powered on again, the memory addresses corresponding to the first five weight values ​​Wn in the weight register are searched, and then the operation codes in the operation code register inside the EMMC chip are copied to the LPDDR chip according to the memory addresses and the number of bytes occupied by the corresponding operation codes.

4. The control method of an embedded memory chip according to claim 3, characterized in that: The following steps are also included: B1: Let k = 1; B2: Calculate the size q of the space inside the LPDDR chip to store the operation code; B3: Determine whether "q≤Q / 3" holds true, where Q is the total internal storage space of the LPDDR chip. If "q≤Q / 3" holds true, set k=1; if "q≤Q / 3" does not hold true, proceed to B4. B4: Arrange the five operation codes in the LPDDR chip in descending order according to byte size, select the first operation code, and delete it from the LPDDR chip; B5: Select the (5+k)th operation code from the operation codes arranged in descending order by weight, map the memory address corresponding to the selected operation code to the memory address corresponding to the LPDDR chip, and copy the operation code in the operation code register inside the EMMC chip to the LPDDR chip based on the memory address and the number of bytes occupied by the corresponding operation code. Set k=k+1 and return to B2.

5. A control system for an embedded memory chip using the control method for an embedded memory chip according to any one of claims 1 to 4, characterized in that: include: An EMMC module is configured to carry an operation code register, wherein the operation code register is configured to store an operation code; The SOC module is used to obtain input operation instructions, classify the operation instructions, obtain operation codes and process data; Data bus, used to transmit data; The LPDDR module is used to carry a data temporary storage register, and the data temporary storage register is used to store data.

6. The control system of an embedded memory chip according to claim 5, characterized in that: The EMMC module is also used to carry a weight register, which is used to store the memory address of the operation code, the number of bytes occupied by the corresponding operation code and the weight value: the SOC module is also used to monitor the input operation instructions and update the weight register; the LPDDR module is also used to store the first five operation codes arranged from large to small according to weight.

7. The control system of an embedded memory chip according to claim 6, characterized in that: The SOC module is also used to calculate the size of the space for storing operation codes inside the LPDDR chip and update the operation codes stored inside the LPDDR chip.

8. The control system of an embedded memory chip according to claim 7, characterized in that: The EMMC module and the LPDDR module are vertically mounted on the SOC module.

Images