A flash interface protection control circuit

Abstract

This invention discloses a Flash interface protection control circuit, relating to the field of interface circuit technology. It includes a read / write control module for controlling the read and write operations of the Flash interface circuit; an interface sampling module for sampling signal voltage values; a signal holding module for signal holding and output; a fault judgment module for judging the degree of signal change through a subtraction circuit; an intelligent control module for receiving signals and controlling the module; a bias current control module for generating bias current and having it copied and transmitted by a current mirror module; and a protection module for providing ground protection for the Flash interface circuit. This Flash interface protection control circuit samples and delays the signal voltage values ​​input to the Flash interface circuit, allowing the fault judgment module to judge the degree of signal change through a subtraction circuit. The intelligent control module receives this information and, when the signal change is significant, provides ground protection to the Flash interface circuit, stopping the read / write operations of the Flash interface circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of interface circuit, in particular to a Flash interface protection control circuit. BACKGROUND

[0002] Flash as a storage medium has been widely used, in the current embedded system application, it is an indispensable device, because of the variety of Flash chip, in order to help the program to read the manufacturer ID and device ID of Flash, determine the size of Flash, obtain the physical characteristics of Flash, most of the Flash chip uses Flash interface to read the information of Flash chip, but the existing Flash interface lacks the protection circuit of interface, when the transmission signal exceeds or is lower than the signal value that the Flash interface can transmit, the Flash interface will not work normally, even damage the Flash interface, will directly lead to the data error of Flash chip, therefore, an urgent need for a Flash interface protection control circuit. SUMMARY

[0003] The embodiment of the present application provides a Flash interface protection control circuit to solve the problems in the background art.

[0004] According to the first aspect of the embodiment of the present application, a Flash interface protection control circuit is provided, which comprises: an interface sampling module, a signal holding module, a fault judgment module, an intelligent control module, a bias current control module, a current mirror module, a read-write control module and a protection module.

[0005] The read-write control module is configured to control the read-write operation of the Flash interface circuit through the power tube circuit.

[0006] The interface sampling module is connected with the read-write control module, configured to sample and output a sampling signal by means of a resistance dividing circuit on the signal value voltage input into the Flash interface circuit.

[0007] The signal holding module is connected with the interface sampling module and the intelligent control module, configured to perform holding processing on the sampling signal by means of a sample-and-hold circuit and output a holding signal.

[0008] The fault judgment module is connected with the interface sampling module and the signal holding module, configured to perform subtraction processing on the holding signal and the sampling signal by means of a subtraction circuit and output a first control signal and a second control signal, and configured to output an overvoltage signal and an undervoltage signal by means of the first control signal and the second control signal to trigger a double triode circuit.

[0009] The intelligent control module is connected with the fault judgment module and the read-write control module, is used for receiving the overvoltage signal and the undervoltage signal and outputting a protection signal to control the working state of the protection module, is used for outputting a read-write control signal and controlling the read-write work of the read-write control module, is used for outputting a third control signal and controlling the working state of the bias current control module, and is used for outputting a fourth control signal and controlling the sample-keeping and keeping output of the signal keeping module.

[0010] The bias current control module is connected with the intelligent control module, is used for receiving the third control signal and controlling the working state of the bias current circuit, and is used for generating a bias current through the bias current circuit and adjusting the bias current value.

[0011] The current mirror module is connected with the bias current control module and the read-write control module, is used for copying the bias current output by the bias current control module through a current mirror circuit and transmitting the bias current to the read-write control module.

[0012] The protection module is connected with the intelligent control module and the read-write control module, is used for receiving the protection signal and performing ground protection on the Flash interface circuit through a discharge circuit.

[0013] According to another aspect of the embodiment of the application, the Flash interface protection control circuit further comprises an alarm module.

[0014] The alarm module is used for receiving the protection signal and performing audible and visual alarm through an audible and visual alarm circuit.

[0015] The alarm module is connected with the intelligent control module.

[0016] Compared with the prior art, the Flash interface protection control circuit of the application samples the signal voltage value of the input Flash interface circuit through an interface sampling module, keeps the delayed signal through a signal keeping module, performs subtraction processing with a fault judgment module, knows the change degree of the sample signal at this time, and uses a dual triode circuit as a protection threshold limit. When the dual triode circuit is turned on, it indicates that the sample signal voltage value is too high or too low at this time, so that the intelligent control module receives and protects the Flash interface circuit through the protection module, stops the read-write work of the Flash interface circuit in the read-write control module, avoids data read-write errors and damage of the Flash interface circuit, and performs fault alarm through the alarm module, thereby improving the safety factor of the Flash interface circuit. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0018] Figure 1 A principle block diagram of a Flash interface protection control circuit is provided for the embodiments of the present application.

[0019] Figure 2 A first circuit diagram of a Flash interface protection control circuit is provided for the embodiments of the present application.

[0020] Figure 3 A second circuit diagram of a Flash interface protection control circuit is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative effort belong to the scope of protection of the present application.

[0022] Embodiment 1, please refer to Figure 1 A Flash interface protection control circuit includes: an interface sampling module 1, a signal holding module 2, a fault judgment module 3, an intelligent control module 4, a bias current control module 5, a current mirror module 6, a read-write control module 7, and a protection module 8.

[0023] Specifically, the read-write control module 7 is configured to control the read-write operation of the Flash interface circuit through a power tube circuit.

[0024] The interface sampling module 1 is connected with the read-write control module 7 and is configured to sample and output a sampling signal by sampling the signal value voltage input into the Flash interface circuit through a resistance voltage dividing circuit.

[0025] The signal holding module 2 is connected with the interface sampling module 1 and the intelligent control module 4 and is configured to hold and output a holding signal by holding the sampling signal through a sample-and-hold circuit.

[0026] The fault judgment module 3 is connected with the interface sampling module 1 and the signal holding module 2, and is used for subtracting the holding signal and the sampling signal through a subtraction circuit and outputting a first control signal and a second control signal, and is used for triggering a double-triode circuit through the first control signal and the second control signal to output an overvoltage signal and an undervoltage signal, respectively.

[0027] The intelligent control module 4 is connected with the fault judgment module 3 and the read-write control module 7, and is used for receiving the overvoltage signal and the undervoltage signal and outputting a protection signal to control the working state of the protection module 8, outputting a read-write control signal to control the read-write work of the read-write control module 7, outputting a third control signal to control the working state of the bias current control module 5, and outputting a fourth control signal to control the sampling holding and holding output of the signal holding module 2.

[0028] The bias current control module 5 is connected with the intelligent control module 4, and is used for receiving the third control signal and controlling the working state of a bias current circuit, and is used for generating a bias current through the bias current circuit and adjusting the bias current value.

[0029] The current mirror module 6 is connected with the bias current control module 5 and the read-write control module 7, and is used for copying the bias current output by the bias current control module 5 through a current mirror circuit and transmitting the bias current to the read-write control module 7.

[0030] The protection module 8 is connected with the intelligent control module 4 and the read-write control module 7, and is used for receiving the protection signal and protecting the Flash interface circuit to ground through a discharge circuit.

[0031] Further, the Flash interface protection control circuit further comprises an alarm module 9.

[0032] Specifically, the alarm module 9 is used for receiving the protection signal and performing audible and light alarm through an audible and light alarm circuit.

[0033] The alarm module 9 is connected with the intelligent control module 4.

[0034] In a specific embodiment, the interface sampling module 1 can use a resistor voltage divider circuit to sample the signal voltage value of the input read / write control module 7; the signal holding module 2 can use a sample-and-hold circuit, whose sampling output is controlled by the intelligent control module 4; the fault judgment module 3 can use a subtraction circuit and a dual transistor circuit, where the subtraction circuit performs subtraction processing on the sample-and-hold signal and the signal sampled in real time by the interface sampling module 1 to determine the degree of signal change, and the dual transistor circuit determines whether the voltage value is high or low; the intelligent control module 4 can use, but is not limited to, microcontrollers such as single-chip microcomputers and DSPs, integrating many components such as arithmetic units, controllers, memory, and input / output devices to realize signal processing. The system includes functions such as data storage and module control; the bias current control module 5 can use a bias current circuit to generate and adjust the bias current value; the current mirror module 6 can use a current mirror circuit to copy and transmit the input bias current; the read / write control module 7 can use a power transistor circuit and a Flash interface circuit, with the power transistor circuit controlling the read / write operation of the Flash interface circuit, and the Flash interface used to control the read / write operation of the Flash chip; the protection module 8 can use a bleeder circuit to protect the signal input to the Flash interface circuit to ground; the alarm module 9 can use an audible and visual alarm circuit to realize fault alarm, controlled by the intelligent control module 4, which will not be described in detail here.

[0035] Example 2, based on Example 1, please refer to... Figure 2 and Figure 3 The read / write control module 7 includes a Flash interface; the interface sampling module 1 includes a first resistor R1 and a second resistor R2.

[0036] Specifically, the second IO terminal of the Flash interface is connected to the first terminal of the second resistor R2, the signal holding module 2, and the fault judgment module 3 through the first resistor R1, and the second terminal of the second resistor R2 is connected to the ground terminal.

[0037] In a specific embodiment, the first resistor R1 and the second resistor R2 form a resistor voltage divider circuit to detect the signal voltage value of the input Flash interface.

[0038] Furthermore, the signal holding module 2 includes a first operational amplifier OP1, a first control transistor M1, a first diode D1, a first capacitor C1, a second operational amplifier OP2, a second capacitor C2, and a second control transistor M2; the intelligent control module 4 includes a first controller U1;

[0039] Specifically, the non-inverting terminal of the first operational amplifier OP1 is connected to the first end of the second resistor R2, the inverting terminal of the first operational amplifier OP1 is connected to the output terminal of the first operational amplifier OP1 and the drain of the first control tube M1, the source of the first control tube M1 is connected to one end of the first capacitor C1 and the non-inverting terminal of the second operational amplifier OP2, the other end of the first capacitor C1 is grounded, the gate of the first control tube M1 is connected to the anode of the second diode, the cathode of the second diode is connected to the cathode of the first diode D1 and the first IO end of the first controller U1, the anode of the first diode D1 is connected to the gate of the second control tube M2, the drain of the second control tube M2 is connected to the inverting terminal of the second operational amplifier OP2 and the output terminal of the second operational amplifier OP2 through the second capacitor C2, the source of the second control tube M2 and the fault judgment module 3.

[0040] In specific embodiments, the first operational amplifier OP1 and the second operational amplifier OP2 can be selected as LF398 operational amplifiers, the first control tube M1 and the second control tube M2 can be selected as junction field effect tubes, the first capacitor C1 is a signal holding capacitor, and the first controller U1 can be selected as, but is not limited to, an ST89C52 single-chip microcomputer.

[0041] Further, the fault judgment module 3 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a third operational amplifier OP3, a sixth resistor R6;

[0042] Specifically, one end of the third resistor R3 is connected to the output terminal of the second operational amplifier OP2, the inverting terminal of the third operational amplifier OP3 is connected to the other end of the third resistor R3 and the output terminal of the third operational amplifier OP3 through the sixth resistor R6, the non-inverting terminal of the third operational amplifier OP3 is connected to one end of the fourth resistor R4 and the ground terminal through the fifth resistor R5, and the other end of the fourth resistor R4 is connected to the first end of the second resistor R2.

[0043] In specific embodiments, the third operational amplifier OP3 can be selected as an OP07 operational amplifier, and the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 form a subtraction circuit to perform subtraction processing on the sample holding signal and the real-time collected signal.

[0044] Further, the fault judgment module 3 further includes a seventh resistor R7, an eighth resistor R8, a first switch tube VT1, a second switch tube VT2, a ninth resistor R9, a tenth resistor R10, and a first power supply VCC1.

[0045] Specifically, one end of the seventh resistor R7 is connected to one end of the eighth resistor R8 and the output terminal of the third operational amplifier OP3, the other end of the seventh resistor R7 is connected to the base of the first switch tube VT1, the other end of the eighth resistor R8 is connected to the base of the second switch tube VT2, the collector of the first switch tube VT1 and the emitter of the second switch tube VT2 are both connected to the first power supply VCC1, the emitter of the first switch tube VT1 is connected to the second IO terminal of the first controller U1 and connected to the ground terminal through the ninth resistor R9, and the collector of the second switch tube VT2 is connected to the third IO terminal of the first controller U1 and connected to the ground terminal through the tenth resistor R10.

[0046] In specific embodiments, the first switch tube VT1 can be selected as an NPN type triode, and the second switch tube VT2 can be selected as a PNP type triode, which is turned on when the base voltage of the first switch tube VT1 and the base voltage of the second switch tube VT2 reach saturation. The first switch tube VT1 is used to detect whether the real-time detection signal exceeds the sample and hold signal, and the second switch tube VT2 is used to detect whether the real-time detection signal is lower than the sample and hold signal.

[0047] Further, the bias current control module 5 includes a first power supply VCC1, a first power tube Q1, a second power tube Q2, a fourth operational amplifier OP4, a first potentiometer RP1, a reference threshold, and a third power tube Q3.

[0048] Specifically, the first power supply VCC1 is connected to the drain of the second power tube Q2 and the source of the third power tube Q3, the gate of the second power tube Q2 is connected to the fourth IO terminal of the first controller U1, the source of the second power tube Q2 is connected to the drain of the third power tube Q3 and the drain of the first power tube Q1, the source of the first power tube Q1 is connected to the inverting terminal of the fourth operational amplifier OP4 and one end of the first potentiometer RP1, the other end and the wiper of the first potentiometer RP1 are both connected to the ground terminal, the non-inverting terminal of the fourth operational amplifier OP4 is connected to the reference threshold, and the gate of the third power tube Q3 is connected to the current mirror module 6.

[0049] In specific embodiments, the first power tube Q1 and the second power tube Q2 can both be selected as N-channel enhancement mode MOS tubes, the second power tube Q2 is controlled by the first controller U1 to control the transmission of the bias current, the first power tube Q1 is controlled by the fourth operational amplifier OP4 to adjust the input bias current value in cooperation with the first potentiometer RP1; the third power tube Q3 can be selected as a P-channel enhancement mode MOS tube, which is used to transmit the bias current to the current mirror module 6; and the fourth operational amplifier OP4 can be selected as an OP07 operational amplifier.

[0050] Further, the current mirror module 6 includes a fourth power tube Q4, a fifth power tube Q5, and a sixth power tube Q6.

[0051] Specifically, the gate of the fourth power tube Q4 is connected with the gates of the third power tube Q3, the fifth power tube Q5 and the sixth power tube Q6, the sources of the fourth power tube Q4, the fifth power tube Q5 and the sixth power tube Q6 are all connected with the source of the third power tube Q3, and the drains of the fourth power tube Q4, the fifth power tube Q5 and the sixth power tube Q6 are connected with the read-write control module 7.

[0052] In specific embodiments, the fourth power tube Q4, the fifth power tube Q5 and the sixth power tube Q6 can all be P-channel enhancement-mode MOS tubes, which are used to copy the bias current transmitted by the third power tube Q3.

[0053] Further, the read-write control module 7 further comprises a seventh power tube Q7, an eighth power tube Q8 and a ninth power tube Q9.

[0054] Specifically, the source of the seventh power tube Q7 is connected with the sources of the eighth power tube Q8 and the ninth power tube Q9 and the first IO end of the Flash interface, the drains of the seventh power tube Q7, the eighth power tube Q8 and the ninth power tube Q9 are respectively connected with the drains of the fourth power tube Q4, the fifth power tube Q5 and the sixth power tube Q6, and the gates of the seventh power tube Q7, the eighth power tube Q8 and the ninth power tube Q9 are respectively connected with the fifth IO end, the sixth IO end and the seventh IO end of the first controller U1.

[0055] In specific embodiments, the seventh power tube Q7, the eighth power tube Q8 and the ninth power tube Q9 can all be N-channel enhancement-mode MOS tubes, which are respectively controlled by the fifth IO end, the sixth IO end and the seventh IO end of the first controller U1, and respectively realize the amplitude pulse signal of the write data "1", the amplitude pulse signal of the write data "0" and the amplitude pulse signal of the read resistance state of the Flash interface.

[0056] It should be noted that, since the three control pulses input to the seventh power tube Q7, the eighth power tube Q8 and the ninth power tube Q9 from the fifth IO end, the sixth IO end and the seventh IO end of the first controller U1 only have one signal valid at the same time, the fifth IO end, the sixth IO end and the seventh IO end of the first controller U1 will only have one output control pulse at a time.

[0057] Further, the protection module 8 comprises a tenth power tube Q10.

[0058] Specifically, the drain of the tenth power tube Q10 is connected with the source of the seventh power tube Q7, the source of the tenth power tube Q10 is grounded, and the gate of the tenth power tube Q10 is connected with the eighth IO end of the first controller U1.

[0059] In specific embodiments, the tenth power tube Q10 described above can be an N-channel enhancement mode MOS tube, used for grounding discharge of the seventh power tube Q7, the eighth power tube Q8, and the ninth power tube Q9, and stopping the read-write control signal of the Flash interface to the Flash chip.

[0060] The Flash interface protection control circuit of the present application samples the data voltage value input to the Flash interface by the first resistor R1 and the second resistor R2, and isolates and transmits by the first operational amplifier OP1, controls the conduction of the first control tube M1 and the second control tube M2 by the first controller U1, so that the first capacitor C1 starts signal holding processing, and after the first control tube M1 and the second control tube M2 are disconnected, the second operational amplifier OP2 will hold the output sampled signal, at the same time, the in-phase terminal of the third operational amplifier OP3 performs real-time signal sampling, so that the real-time sampled signal and the sampled and held signal are subjected to subtraction processing, to know the change of the input data voltage value at this time, at the same time, the fourth IO of the first controller U1 controls the conduction of the second power tube Q2, controls the working of the bias current control module 5, adjusts the conduction degree of the first power tube Q1 by the first potentiometer RP1 to provide appropriate bias current, and transmits by the fourth power tube Q4, the fifth power tube Q5, and the sixth power tube Q6, controls the seventh power tube Q7, the eighth power tube Q8, and the ninth power tube Q9 to transmit the amplitude pulse signal of writing data "1", the amplitude pulse signal of writing data "0", and the amplitude pulse signal of reading resistance state to the Flash interface by the first controller U1, and to the Flash chip by the Flash interface, to realize the read-write control of the Flash chip, if the data voltage value after subtraction processing is large and the voltage value change is large, the first switch tube VT1 will be turned on, if the data voltage value is small and the voltage value change is large, the second switch tube VT2 will be turned on, and the first controller U1 will know the data voltage value input to the Flash interface at this time, the first controller U1 will directly control the conduction of the tenth power tube Q10 to disconnect the data information input to the Flash interface, and protect the Flash interface.

[0061] It is apparent for those skilled in the art that the present application is not limited to the details of the foregoing exemplary embodiments, and can be implemented in other concrete forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all aspects as illustrative and not restrictive, and the scope of the present application is defined by the appended claims rather than the foregoing description, and it is intended to encompass all changes falling within the meaning and range of equivalents of the claims. Any reference signs in the claims should not be considered as limiting the claims involved.

[0062] Furthermore, it should be understood that although the specification is described in terms of embodiments, not every embodiment includes every feature or implementation described herein. The specification can include implicit combinations of explicitly mentioned features and / or implicit combinations of implicitly mentioned features. Such combinations are also expressly included within the scope of the specification and an embodiment.

Claims

1. A Flash interface protection control circuit, characterized in that, the Flash interface protection control circuit comprises an interface sampling module, a signal holding module, a fault judgment module, an intelligent control module, a bias current control module, a current mirror module, a read-write control module, and a protection module; the read-write control module is configured to control the read-write operation of the Flash interface circuit through a power tube circuit; the interface sampling module is connected to the read-write control module and is configured to sample the signal value voltage input to the Flash interface circuit through a resistance voltage dividing circuit and output a sampling signal; the signal holding module is connected to the interface sampling module and the intelligent control module and is configured to perform holding processing on the sampling signal through a sample-and-hold circuit and output a holding signal; the fault judgment module is connected to the interface sampling module and the signal holding module and is configured to perform subtraction processing on the holding signal and the sampling signal through a subtraction circuit and output a first control signal and a second control signal, and configured to trigger a dual triode circuit to output an overvoltage signal and an undervoltage signal through the first control signal and the second control signal, respectively; the intelligent control module is connected to the fault judgment module and the read-write control module and is configured to receive the overvoltage signal and the undervoltage signal and output a protection signal to control the working state of the protection module, output a read-write control signal to control the read-write operation of the read-write control module, output a third control signal to control the working state of the bias current control module, and output a fourth control signal to control the sample-and-hold and holding output of the signal holding module; the bias current control module is connected to the intelligent control module and is configured to receive the third control signal and control the working of a bias current circuit, and configured to generate a bias current through the bias current circuit and adjust the bias current value; the current mirror module is connected to the bias current control module and the read-write control module and is configured to copy the bias current output by the bias current control module through a current mirror circuit and transmit the bias current to the read-write control module; the protection module is connected to the intelligent control module and the read-write control module and is configured to receive the protection signal and perform ground protection on the Flash interface circuit through a bleeder circuit.

2. The flash interface protection control circuit according to claim 1, wherein, The Flash interface protection control circuit further comprises an alarm module; the alarm module is configured to receive the protection signal and perform audible and visual alarm through an audible and visual alarm circuit; the alarm module is connected to the intelligent control module.

3. The flash interface protection control circuit of claim 1, wherein, The read-write control module comprises a Flash interface; the interface sampling module comprises a first resistor and a second resistor; the second IO terminal of the Flash interface is connected to the first terminal of the second resistor, the signal holding circuit, and the fault judgment module through the first resistor, and the second terminal of the second resistor is connected to a ground terminal.

4. The flash interface protection control circuit of claim 3, wherein, The signal holding circuit comprises a first operational amplifier, a first control tube, a first diode, a first capacitor, a second operational amplifier, a second capacitor, and a second control tube; and the intelligent control module comprises a first controller. The noninverting terminal of the first operational amplifier is connected to the first end of the second resistor, the inverting terminal of the first operational amplifier is connected to the output terminal of the first operational amplifier and the drain of the first control transistor, the source of the first control transistor is connected to the one end of the first capacitor and the noninverting terminal of the second operational amplifier, the other end of the first capacitor is connected to the ground, the gate of the first control transistor is connected to the anode of the second diode, the cathode of the second diode is connected to the cathode of the first diode and the first IO terminal of the first controller, the anode of the first diode is connected to the gate of the second control transistor, the drain of the second control transistor is connected to the inverting terminal of the second operational amplifier and the output terminal of the second operational amplifier through the second capacitor, the source of the second control transistor is connected to the fault judgment module.

5. The Flash interface protection control circuit of claim 4, wherein, The fault judgment module comprises a third resistor, a fourth resistor, a fifth resistor, a third operational amplifier, a sixth resistor; The one end of the third resistor is connected to the output terminal of the second operational amplifier, the inverting terminal of the third operational amplifier is connected to the other end of the third resistor and the output terminal of the third operational amplifier through the sixth resistor, the noninverting terminal of the third operational amplifier is connected to the one end of the fourth resistor and the ground through the fifth resistor, the other end of the fourth resistor is connected to the first end of the second resistor.

6. The Flash interface protection control circuit of claim 5, wherein, The fault judgment module further comprises a seventh resistor, an eighth resistor, a first switch transistor, a second switch transistor, a ninth resistor, a tenth resistor, a second power supply; The one end of the seventh resistor is connected to the one end of the eighth resistor and the output terminal of the third operational amplifier, the other end of the seventh resistor is connected to the base of the first switch transistor, the other end of the eighth resistor is connected to the base of the second switch transistor, the collector of the first switch transistor and the emitter of the second switch transistor are both connected to the second power supply, the emitter of the first switch transistor is connected to the second IO terminal of the first controller and the ground through the ninth resistor, the collector of the second switch transistor is connected to the third IO terminal of the first controller and the ground through the tenth resistor.

7. The Flash interface protection control circuit of claim 4, wherein, The bias current control module comprises a first power supply, a first power transistor, a second power transistor, a fourth operational amplifier, a first potentiometer, a reference threshold, a third power transistor; The first power supply is connected to the drain of the second power transistor and the source of the third power transistor, the gate of the second power transistor is connected to the fourth IO terminal of the first controller, the source of the second power transistor is connected to the drain of the third power transistor and the drain of the first power transistor, the source of the first power transistor is connected to the inverting terminal of the fourth operational amplifier and the one end of the first potentiometer, the other end of the first potentiometer and the wiper are both connected to the ground, the noninverting terminal of the fourth operational amplifier is connected to the reference threshold, the gate of the third power transistor is connected to the current mirror module.

8. The Flash interface protection control circuit of claim 7, wherein, The current mirror module comprises a fourth power transistor, a fifth power transistor, a sixth power transistor; The gate of the fourth power transistor is connected to the gate of the third power transistor, the gate of the fifth power transistor and the gate of the sixth power transistor, the source of the fourth power transistor, the source of the fifth power transistor and the source of the sixth power transistor are all connected to the source of the third power transistor, the drain of the fourth power transistor, the drain of the fifth power transistor and the drain of the sixth power transistor are connected to the read-write control module.

9. The Flash interface protection control circuit of claim 8, wherein, The read-write control module further comprises a seventh power transistor, an eighth power transistor, a ninth power transistor; The source of the seventh power tube is connected with the source of the eighth power tube, the source of the ninth power tube and the first IO end of the Flash interface, the drain of the seventh power tube, the drain of the eighth power tube and the drain of the ninth power tube are respectively connected with the drain of the fourth power tube, the drain of the fifth power tube and the drain of the sixth power tube, the gate of the seventh power tube, the gate of the eighth power tube and the gate of the ninth power tube are respectively connected with the fifth IO end, the sixth IO end and the seventh IO end of the first controller.

10. The Flash interface protection control circuit of claim 9, wherein, The protection module comprises a tenth power tube; The drain of the tenth power tube is connected with the source of the seventh power tube, the source of the tenth power tube is grounded, and the gate of the tenth power tube is connected with the eighth IO end of the first controller.

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