Memory device and method of operation thereof

Abstract

Embodiments of the present application provide a memory device and a method of operating the same. The memory device includes a static random access memory including two cross-coupled inverters and an access transistor having a gate connected to a word line. The memory device further includes one or more logic gates electrically coupled to the static random access memory, and a non-volatile memory electrically coupled to the static random access memory and configured to store data and be read using the static random access memory. Wherein the non-volatile memory is connected on one side to the access transistor and on another side to the two cross-coupled inverters.

Description

Technical Field

[0001] Embodiments of this application relate to memory devices and methods of operating the same. Background Technology

[0002] Typically, compute-in-memory (CIM) systems store information in random access memory (RAM), such as static random access memory (SRAM), and perform computations at the memory device level. In CIM systems, accessing data from RAM is much faster than accessing it from other memory devices, allowing for faster data analysis. This enables faster reporting and decision-making in business and machine learning applications.

[0003] SRAM has an array of memory cells including transistors connected between an upper reference potential and a lower reference potential, such that one of the two storage nodes stores the information to be stored, while the other storage node stores complementary information. One SRAM memory cell arrangement includes six transistors, where each bit of information is stored on four transistors forming two cross-coupled inverters. Two additional transistors are connected to the memory cell word line to control access to the two cross-coupled inverters during read and write operations by selectively connecting the memory cell to the bit line BL and the complementary bit line or inverted bit line BLB. Because SRAM is volatile, data is lost when SRAM is powered off. Summary of the Invention

[0004] According to one aspect of an embodiment of this application, a memory device is provided, comprising: a static random access memory (SRAM) including two cross-coupled inverters and an access transistor having a gate connected to a word line; one or more logic gates electrically coupled to the SRAM; and a non-volatile memory electrically coupled to the SRAM and configured to store data and be read from the SRAM, wherein the non-volatile memory is connected to the access transistor on one side and to the two cross-coupled inverters on the other side.

[0005] According to another aspect of the embodiments of this application, a memory device is provided, comprising: a static random access memory cell including a cross-coupled first inverter and a second inverter, and a first access transistor and a second access transistor configured to selectively connect the cross-coupled first inverter and the second inverter to a first bit line and a second bit line; a non-volatile memory connected in series between the first inverter and the first access transistor; and logic circuitry having a first input connected between the second inverter and the second access transistor and a second input configured to receive an external input signal.

[0006] According to another aspect of the embodiments of this application, a method of operating a memory device is provided, the method comprising: operating in each of the following modes in the memory device: a static random access memory (SRAM) mode, a non-volatile memory (NRAM) mode, and a compute-in-memory mode; operating in the SRAM mode to write data to and read data from the SRAM; operating in the NRAM mode to set, reset, and retrieve data from the NRAM, the NRAM being electrically connected to two cross-coupled inverters in the SRAM and one of two transistors controlling access to the two cross-coupled inverters; and operating in the compute-in-memory mode to perform one or more logical functions on data from the SRAM using logic gates electrically connected to the SRAM. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. Furthermore, the drawings are examples illustrating embodiments of this disclosure and are not intended to be limiting.

[0008] Figure 1 This is a block diagram schematically illustrating a memory device according to some embodiments.

[0009] Figure 2 This is a schematic block diagram illustrating an NVMSRAMCIM cell according to some embodiments.

[0010] Figure 3 This is a schematic diagram illustrating, according to some embodiments, an NVM SRAM CIM cell comprising a six-transistor SRAM and an NVM integrated (or connected) into the six-transistor SRAM.

[0011] Figure 4 This is a schematic diagram illustrating an NVM SRAM CIM cell according to some embodiments, including an RRAM for storing data and a logic gate configured to perform a logic AND function for an input signal IN and a data signal D (using an inverted data signal DB).

[0012] Figure 5 This is a schematic diagram illustrating an AND gate configured to provide the logic AND function of an input signal IN and a data signal D according to some embodiments.

[0013] Figure 6This is a schematic diagram illustrating NAND gates and inverters configured to provide the logic AND function of input signal IN and data signal D according to some embodiments.

[0014] Figure 7 The diagram schematically illustrates an OR gate configured to provide the logic OR function for input signal IN and data signal D according to some embodiments.

[0015] Figure 8 This is a schematic diagram illustrating NOR gates and inverters configured to provide the logic OR function for input signal IN and data signal D according to some embodiments.

[0016] Figure 9 This is a schematic diagram illustrating an inverter and a NAND gate configured to provide an input signal IN and a data signal D (using an inverted data signal DB) according to some embodiments, performing a logic OR function.

[0017] Figure 10 This is a diagram schematically illustrating two example truth tables of CIM logic gates operating in CIM mode according to some embodiments.

[0018] Figure 11 This is a schematic diagram illustrating a table depicting SRAM read operations in one of the NVM SRAMCIM cells operating in SRAM mode, according to some embodiments.

[0019] Figure 12 This is a schematic diagram illustrating a table depicting SRAM write operations in one of the NVM SRAMCIM cells operating in SRAM mode, according to some embodiments.

[0020] Figure 13 This is a schematic diagram illustrating a table according to some embodiments depicting write operations including a set operation (write logic 1) and a reset operation (write logic 0) for RRAM.

[0021] Figure 14 This is a diagram schematically illustrating a table depicting call operations from stored data in RRAM according to some embodiments.

[0022] Figure 15 This is an illustrative representation according to some embodiments. Figure 4 The timing diagrams for the three operating modes of the NVM SRAM CIM cell are shown in the figure.

[0023] Figure 16 This is a diagram schematically illustrating a method of operating a memory device according to some embodiments. Detailed Implementation

[0024] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0025] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0026] In some CIM systems, SRAM CIM cells include SRAM electrically connected to the CIM logic gates. SRAM is a volatile memory, so the data in the SRAM is lost when the SRAM CIM cell is powered off. To retrieve data, the SRAM CIM cell retrieves data from remote memory, such as a separate memory array or another computer. Retrieving data from remote memory consumes a significant amount of power.

[0027] Disclosed embodiments include non-volatile memory (NVM) integrated into an SRAM CIM cell. The resulting NVM SRAM CIM cell is configured to store data in the NVM and retrieve data from the NVM within the NVM SRAM CIM cell. Storing data in the NVM, rather than in SRAM or a remote memory cell, reduces standby power consumption for data storage when the NVM SRAM CIM cell is completely powered off and supports data retention during power outages. Retrieving data from the NVM reduces power consumption for data retrieval because the data is not transferred from a remote memory cell. Furthermore, using data stored in SRAM for CIM operations improves the performance of CIM logic operations, where the NVM SRAM CIM cell performs logic operations on data from SRAM to achieve high-speed, digital-based CIM functionality without the need for complex sensing and readout schemes. Additionally, including the NVM SRAM CIM cell in an integrated circuit reduces area overhead, where the SRAM is combined with back-end memory technology, and less area is used for data retrieval and data transfer circuitry. In some embodiments, the NVM SRAM CIM cell includes a six-transistor SRAM and an NVM, such as resistive random access memory (RRAM).

[0028] In the disclosed embodiments, the NVM SRAM CIM cell includes three basic building blocks. One part of the NVM SRAM CIM cell is SRAM, such as a six-transistor SRAM. Another part of the NVM SRAM CIM cell is an NVM configured to store data. The third part of the NVM SRAM CIM cell includes logic gates for performing CIM operations. In some embodiments, the NVM is RRAM. In other embodiments, the NVM is magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and / or phase-change random access memory (PCRAM).

[0029] Furthermore, in the disclosed embodiments, the NVM SRAM CIM cell is configured to operate in SRAM mode, NVM mode, and CIM mode. In SRAM mode, data is written to and read from the SRAM within the NVM SRAM CIM cell. In NVM mode, the NVM can be set (i.e., written to 1), reset (i.e., written to 0), and data can be retrieved from the NVM using the SRAM. In CIM mode, logic gates receive one or more input signals and data from the SRAM to compute the CIM output.

[0030] Figure 1This is a schematic block diagram illustrating a memory device 20 according to some embodiments. The memory device 20 includes a memory array 22, which includes a plurality of memory cells 24 arranged in rows and columns. Each row has a corresponding first word line WL and a corresponding second word line WLB. Figure 1 (Not shown in the diagram), and each column has a corresponding bit line BL and a corresponding complementary bit line or inverted bit line BLB. Each of the plurality of memory cells 24 is electrically coupled to the first word line WL and the second word line WLB of the row of memory cell 24 and the corresponding bit line BL and inverted bit line BLB of the column of memory cell 24. The bit line BL and the inverted bit line BLB are electrically connected to an input / output (I / O) block 26, which is configured to read data signals from the plurality of memory cells 24 and to provide data signals to the plurality of memory cells 24.

[0031] The plurality of memory cells 24 are NVM SRAM CIM cells. Each of the NVM SRAM CIM cells includes an SRAM (such as a six-transistor SRAM), an NVM configured to store data, and a CIM logic gate for performing CIM operations. The NVM is integrated into the SRAM, and the SRAM is electrically connected to the CIM logic gate. The CIM logic gate of each of the plurality of memory cells 24 includes an input 28 for receiving input signals and an output 30 for providing CIM outputs from CIM operations.

[0032] The resulting NVM SRAM CIM cell is configured to operate in three modes: SRAM mode, NVM mode, and CIM mode. In SRAM mode, data is written to and read from the SRAM. In NVM mode, the NVM can be set (i.e., written to 1), reset (i.e., written to 0), and data can be retrieved from the NVM using the SRAM. In CIM mode, the logic gate receives one or more input signals and data from the SRAM at input 28 and determines the CIM output provided at output 30.

[0033] The memory control circuit or controller 32 is electrically connected to the memory array 22 and the I / O block 26 and is configured to control the operation of the memory device 20. The controller 32 receives signals such as clock signals, command signals, and address signals for accessing and controlling the operation of the memory device 20, including the operation of multiple memory cells 24 (i.e., NVM SRAMCIM cells) in the memory array 22. For example, address signals can be received and decoded into row and column addresses for accessing the memory cells 24 of the memory array 22. Furthermore, the controller 32 is configured to control the application of signals to the first word line WL, the second word line WLB, the bit line BL, the inverted bit line BLB, to apply input signals at input 28, and to apply signals to the power supply lines of the memory cells 24 and the memory device 20.

[0034] In some embodiments, controller 32 includes one or more processors. In some embodiments, controller 32 includes one or more processors and memory configured to store code executed by the one or more processors to perform the functions of memory device 20. In some embodiments, controller 32 includes hardware (such as logic) configured to receive addresses and commands and perform the functions of memory device 20. In some embodiments, controller includes hardware and / or firmware and / or software executed by the hardware for performing the functions of memory device 20.

[0035] Figure 2 This is a schematic block diagram illustrating an NVM SRAM CIM cell 100 according to some embodiments. The NVM SRAM CIM cell 100 is configured for use in a memory device, such as... Figure 1 The memory device 20. In some embodiments, the NVMSRAM CIM cell 100 is similar to the memory cell 24.

[0036] The NVM SRAM CIM cell 100 includes an SRAM 102, an NVM 104, and a CIM logic gate 106. The NVM 104 is integrated (or connected) into the SRAM 102, and the SRAM 102 is electrically connected to the CIM logic gate 106 via a communication path 108. The SRAM 102 is electrically connected to bit lines BL 110 and complementary or inverted bit lines BLB 112, such as the bit lines BL and inverted bit lines BLB of memory device 20. Furthermore, the SRAM 102 is electrically coupled to word lines, such as the first word line WL and the second word line WLB of memory device 20. In some embodiments, the SRAM 102 is a six-transistor SRAM. In other embodiments, the SRAM 102 is a different type of SRAM, such as an SRAM having more or fewer than six transistors.

[0037] NVM 104 is integrated (or connected) to SRAM 102 and configured to store data. In some embodiments, NVM 104 is RRAM. In some embodiments, NVM 104 is MRAM. In some embodiments, NVM 104 is FRAM. In some embodiments, NVM 104 is PCRAM.

[0038] CIM logic gate 106 is used to perform CIM operations. CIM logic gate 106 includes an input 114 for receiving input signals and an output 116 for providing CIM outputs. One or more logic gates 106 are configured to perform one or more logic functions, such as AND, OR, NOT, NAND, NOR, XOR, XNOR, and buffer functions.

[0039] The resulting NVM SRAM CIM cell 100 is configured to operate in three modes: SRAM mode, NVM mode, and CIM mode. In SRAM mode, data is written to and read from SRAM 102. In NVM mode, NVM 104 can be set (i.e., written to 1), reset (i.e., written to 0), and data can be retrieved from NVM 104 using SRAM 102. In CIM mode, logic gate 106 receives one or more input signals at input 114 and data from SRAM 102, and determines the CIM output provided at output 116.

[0040] Figure 3 This is a schematic diagram illustrating an NVM SRAM CIM cell 130 according to some embodiments, comprising a six-transistor SRAM 132 and an NVM 134 integrated (or connected) to the six-transistor SRAM 132. The NVM SRAM CIM cell 130 includes SRAM 132, NVM 134, and CIM logic gate 136. The NVM SRAM CIM cell 130 is configured for use in a memory device, such as... Figure 1 The memory device 20. In some embodiments, the NVM SRAM CIM cell 130 is similar to the memory cell 24 (e.g., Figure 1 (As shown). In some embodiments, the NVM SRAM CIM cell 130 is similar to Figure 2 NVM SRAM CIM cell 100.

[0041] NVM 134 is integrated (or connected) into SRAM 132, and SRAM 132 is electrically connected to CIM logic gate 136 via communication path 138. SRAM 132 is electrically connected to bit line BL 140 and complementary bit line or inverted bit line BLB 142, which may be similar to bit line BL and inverted bit line BLB of memory device 20. Furthermore, SRAM 132 is electrically coupled to first word line 144 and second word line WLB 146, which may be similar to first word line WL and second word line WLB of memory device 20. Additionally, SRAM 132 is configured to receive a first power supply voltage VDD1 148 and a second power supply voltage VDD2 150.

[0042] The six-transistor SRAM 132 includes four transistors 152, 154, 156, and 158, which form two cross-coupled inverters 160 and 162 configured to store one bit of information, and two access control NMOS transistors 164 and 166 controlling access to the two cross-coupled inverters 160 and 162.

[0043] The first inverter 160 includes a first PMOS transistor 152 and a first NMOS transistor 154. One drain / source region of the first PMOS transistor 152 is electrically connected to receive a first power supply voltage VDD1 148, and the other drain / source region of the first PMOS transistor 152 is electrically connected to the drain / source region of the first NMOS transistor 154, the gates of transistors 156 and 158, and one side of NVM 134. The other drain / source region of the first NMOS transistor 154 is electrically connected to a reference 168, such as ground.

[0044] The second inverter 162 includes a second PMOS transistor 156 and a second NMOS transistor 158. One drain / source region of the second PMOS transistor 156 is electrically connected to receive a second power supply voltage VDD2 150, and the other drain / source region of the second PMOS transistor 156 is electrically connected to the drain / source region of the second NMOS transistor 158, the gates of the first PMOS transistor 152 and the first NMOS transistor 154, and the drain / source region of the access control NMOS transistor 166. The other drain / source region of the second NMOS transistor 158 is electrically connected to a reference 168, such as ground.

[0045] Access control NMOS transistors 164 and 166 are connected to control access to two cross-coupled inverters 160 and 162 by selectively connecting the NVM SRAM CIM cell 130 to bit line BL 140 and bit line BLB 142. One drain / source region of the first access control NMOS transistor 164 is electrically connected to one side of NVM 134, and the other drain / source region of the first access control NMOS transistor 164 is electrically connected to bit line BL 140. The gate of the first access control NMOS transistor 164 is electrically connected to word line WL 144. Furthermore, one drain / source region of the second access control NMOS transistor 166 is electrically connected to the drain / source regions of the second PMOS transistor 156, the second NMOS transistor 158, and the gates of the first PMOS transistor 152 and the first NMOS transistor 154. The other drain / source region of the second access control NMOS transistor 166 is electrically connected to the inverted bit line BLB 142. The gate of the second access control NMOS transistor 166 is electrically connected to the second word line WLB 146.

[0046] Controllers, such as controller 32 (e.g.) Figure 1 As shown, signals are provided to the first word line WL 144 and the second word line WLB 146 to control access to two cross-coupled inverters 160 and 162 by selectively connecting the NVM SRAM CIM cell 130 to the bit line BL 140 and the inverted bit line BLB 142.

[0047] NVM 134 is connected to SRAM 132 and configured to store data. In some embodiments, NVM 134 is RRAM. In some embodiments, NVM 134 is MRAM. In some embodiments, NVM 134 is FRAM. In some embodiments, NVM 134 is PCRAM.

[0048] CIM logic gate 136 is used to perform CIM operations. CIM logic gate 136 includes an input 170 for receiving the input signal IN and an output 172 for providing the CIM output OUT. CIM logic gate 136 is configured to perform one or more logic functions, such as AND, OR, NOT, NAND, NOR, XOR, XNOR, and buffer functions.

[0049] The resulting NVM SRAM CIM cell 130 is configured to operate in three modes: SRAM mode, NVM mode, and CIM mode. In SRAM mode, data is written to and read from the six-transistor SRAM 132. In NVM mode, NVM 134 can be set (i.e., written to 1), reset (i.e., written to 0), and data can be retrieved from NVM 134 using SRAM 132. In CIM mode, logic gate 136 receives one or more input signals IN at input 170 and data from SRAM 132 to determine the CIM output OUT provided at output 172.

[0050] Figure 4 This diagram schematically illustrates an NVM SRAM CIM cell 200 according to some embodiments. The NVM SRAM CIM cell 200 includes an RRAM 202 for storing data and logic gates 204 and 206 configured to perform a logical AND function on an input signal IN and a data signal D (using an inverted data signal DB). The NVM SRAM CIM cell 200 is similar to the NVM SRAM CIM cell 130, except that the NVM 134 is designated as the RRAM 202 and the logic gate 136 is designated as an inverter 204 and a NOR gate 206 configured to perform an AND function on the logical input signal IN and the data signal D (using an inverted data signal DB).

[0051] Each of the NVM SRAM CIM cells 130 and 200 includes information about Figure 3 The six transistor SRAM 132 described includes a first PMOS transistor 152, a first NMOS transistor 154, a second PMOS transistor 156, a second NMOS transistor 158, a first access control NMOS transistor 164, and a second access control NMOS transistor 166 connected to bit line BL 140, inverted bit line BLB 142, first word line WL 144, second word line WLB 146, first power supply voltage VDD 1148, and second power supply voltage VDD 2 150, which will not be described further here.

[0052] RRAM 202 is electrically connected on one side to the drain / source region of the first access control NMOS transistor 164, and on the other side to the drain / source region of the first PMOS transistor 152, the drain / source region of the first NMOS transistor 154, and the gates of the second PMOS transistor 156 and the second NMOS transistor 158.

[0053] The input of inverter 204 is configured to receive the input signal IN at input 170, and the output of inverter 204 is electrically connected to one input of NOR gate 206. The other input of NOR gate 206 is connected to the drain / source regions of the second access control NMOS transistor 166, the drain / source regions of the second PMOS transistor 156, the drain / source regions of the second NMOS transistor 158, and the gates of the first PMOS transistor 152 and the first NMOS transistor 154 to receive the inverted data signal DB. In this configuration, inverter 204 and NOR gate 206 perform a logical AND function between the input signal IN and the data signal D (using the inverted data signal DB) to provide CIM output OUT at output 172.

[0054] Figure 5 and Figure 6 This is a diagram schematically illustrating other logic gate configurations that provide the logic AND function for input signal IN and data signal D according to some embodiments.

[0055] Figure 5 This is a schematic diagram illustrating an AND gate 210 configured to provide a logic AND function for an input signal IN and a data signal D according to some embodiments. The AND gate 210 can be used in memory cells, such as memory cell 24 (e.g., memory cell 24). Figure 1 (as shown) Figure 2 NVM SRAM CIM cell 100 and Figure 3 The NVM SRAM CIM cell 130. In some embodiments, AND gate 210 can be used to replace Figure 4 The NVM SRAM CIM cell 200 uses an inverter 204 and a NOR gate 206 to provide the logic AND function for the input signal IN and the data signal D.

[0056] One input of AND gate 210 is electrically connected to one side of an NVM (such as NVM 104, NVM 134, and RRAM 202), the drain / source region of the first PMOS transistor 152, the drain / source region of the first NMOS transistor 154, and the gates of the second PMOS transistor 156 and the second NMOS transistor 158 to receive the data signal D. The other input of AND gate 210 is electrically connected to receive the input signal IN at input 170. In this configuration, AND gate 210 is configured to perform a logical AND function between the input signal IN and the data signal D, and provides a CIM output OUT at output 172.

[0057] Figure 6This is a schematic diagram illustrating a NAND gate 220 and an inverter 222 configured to provide the logic AND function of an input signal IN and a data signal D according to some embodiments. The NAND gate 220 and inverter 222 can be used in memory cells, such as memory cell 24 (e.g., memory cell 24). Figure 1 (as shown) Figure 2 NVM SRAM CIM cell 100 and Figure 3 The NVM SRAM CIM cell 130. In some embodiments, the NAND gate 220 and inverter 222 can be used to replace Figure 4 The NVM SRAM CIM cell 200 uses an inverter 204 and a NOR gate 206 to provide the logic AND function for the input signal IN and the data signal D.

[0058] One input of NAND gate 220 is electrically connected to one side of an NVM (such as NVM 104, NVM 134, and RRAM 202), the drain / source region of the first PMOS transistor 152, the drain / source region of the first NMOS transistor 154, and the gates of the second PMOS transistor 156 and the second NMOS transistor 158 to receive the data signal D. The other input of NAND gate 220 is electrically connected to receive the input signal IN at input 170. The output of NAND gate 220 is electrically connected to the input of inverter 222, and the output of the inverter is output 172. In this configuration, NAND gate 220 and inverter 222 are configured to perform a logical AND function of the input signal IN and the data signal D, and provide CIM output OUT at output 172.

[0059] Figures 7-9 This is a schematic diagram illustrating a logic gate configuration that provides a logic OR function for an input signal IN and a data signal D according to some embodiments.

[0060] Figure 7 This is a schematic diagram illustrating an OR gate 230 configured to provide a logic OR function for an input signal IN and a data signal D according to some embodiments. The OR gate 230 can be used in a memory cell, such as memory cell 24 (e.g., memory cell 24). Figure 1 (as shown) Figure 2 NVM SRAM CIM cell 100 and Figure 3 The NVM SRAM CIM cell 130. In some embodiments, the OR gate 230 can be used to replace Figure 4 The NVM SRAM CIM cell 200 includes an inverter 204 and an OR gate 206, and provides a logic OR function for the input signal IN and the data signal D.

[0061] One input of OR gate 230 is electrically connected to one side of an NVM (such as NVM 104, NVM 134, and RRAM 202), the drain / source region of the first PMOS transistor 152, the drain / source region of the first NMOS transistor 154, and the gates of the second PMOS transistor 156 and the second NMOS transistor 158 to receive the data signal D. The other input of OR gate 230 is electrically connected to receive the input signal IN at input 170. In this configuration, OR gate 230 is configured to perform a logic OR function between the input signal IN and the data signal D, and provides a CIM output OUT at output 172.

[0062] Figure 8 This is a schematic diagram illustrating a NOR gate 240 and an inverter 242 configured to provide a logic OR function for an input signal IN and a data signal D according to some embodiments. The NOR gate 240 and inverter 242 can be used in memory cells, such as memory cell 24 (e.g., memory cell 24). Figure 1 (as shown) Figure 2 NVM SRAM CIM cell 100 and Figure 3 The NVM SRAM CIM cell 130. In some embodiments, the NOR gate 240 and inverter 242 can be used instead of Figure 4 The NVM SRAM CIM cell 200 includes an inverter 204 and an OR gate 206, and provides a logic OR function for the input signal IN and the data signal D.

[0063] One input of NOR gate 240 is electrically connected to one side of an NVM (such as NVM 104, NVM 134, and RRAM 202), the drain / source region of the first PMOS transistor 152, the drain / source region of the first NMOS transistor 154, and the gates of the second PMOS transistor 156 and the second NMOS transistor 158 to receive the data signal D. The other input of NOR gate 240 is electrically connected to receive the input signal IN at input 170. The output of NOR gate 240 is electrically connected to the input of inverter 242, and the output of inverter 242 is output 172. In this configuration, NOR gate 240 and inverter 242 are configured to perform a logic OR function on the input signal IN and the data signal D, and provide CIM output OUT at output 172.

[0064] Figure 9 This is a schematic diagram illustrating an inverter 250 and a NAND gate 252 configured to provide a logic OR function for an input signal IN and a data signal D (using an inverted data signal DB) according to some embodiments. The inverter 250 and NAND gate 252 can be used in memory cells, such as memory cell 24 (e.g., memory cell 24). Figure 1 (as shown) Figure 2NVM SRAM CIM cell 100 and Figure 3 The NVM SRAM CIM cell 130. In some embodiments, the inverter 250 and NAND gate 252 can be used instead of Figure 4 The NVM SRAM CIM cell 200 includes an inverter 204 and a OR gate 206, and provides a logic OR function for the input signal IN and the data signal D (using the inverted data signal DB).

[0065] The input of inverter 250 is configured to receive the input signal IN at input 170, and the output of inverter 250 is electrically connected to one input of NAND gate 252. The other input of NAND gate 252 is connected to the drain / source regions of the second access control NMOS transistor 166, the drain / source regions of the second PMOS transistor 156, the drain / source regions of the second NMOS transistor 158, and the gates of the first PMOS transistor 152 and the first NMOS transistor 154 to receive the inverted data signal DB. In this configuration, inverter 250 and NAND gate 252 perform a logic OR function on the input signal IN and the data signal D (using the inverted data signal DB) to provide CIM output OUT at output 172.

[0066] Figures 4-9 This includes CIM logic gates for performing logical AND or logical OR functions. In other embodiments, CIM logic gates, such as CIM logic gate 106 (… Figure 2 (as shown) and CIM logic gate 136 ( Figure 3 As shown, it can be configured to perform one or more logical functions, including AND, OR, NOT, NAND, NOR, XOR, XNOR and / or buffer functions.

[0067] As described above, each of the memory cells 24 and each of the NVM SRAM CIM cells 100, 130, and 200 are configured to operate in three modes, including SRAM mode, NVM mode, and CIM mode. In CIM mode, logic gates, such as CIM logic gate 106 ( Figure 2 (as shown) and CIM logic gate 136 ( Figure 3 As shown, the input signal IN at input terminal 170 and the input from SRAM 132 are received to determine the CIM output OUT provided at output 172. In some embodiments, the data from SRAM 132 are weights used in a convolutional neural network (CNN).

[0068] Figure 10This is a schematic diagram illustrating two example truth tables 260 for CIM logic gates operating in CIM mode according to some embodiments. Truth table 260 includes a truth table 262 for a logical AND function and a truth table 264 for a logical OR function. Of course, other truth tables can be developed for other logical functions performed by the logic gates.

[0069] The truth table 262 for the AND function and the truth table 264 for the OR function each include columns for the input signal IN, the data signal D, and the output signal OUT. The input signal IN and the data signal D include four binary combinations: 00, 01, 10, and 11. Additionally, in CIM mode, the bit line BL, the inverted bit line BLB, the first word line WL, and the second word line WLB are all set to 0 volts (V).

[0070] If the input signal IN is 0 or the data signal D is 0 (the inverted data signal DB is 1), or if the input signal IN is 0 and the data signal D is 0 (the inverted data signal DB is 1), then the output signal OUT of the logic AND function is 0. The output signal OUT of the logic AND function is 1 only when the input signal IN is 1 and the data signal D is 1 (the inverted data signal DB is 0).

[0071] If the input signal IN is 1 or the data signal D is 1 (the inverted data signal DB is 0), or if the input signal IN is 1 and the data signal D is 1 (the inverted data signal DB is 0), then the logic OR function output signal OUT is 1. The logic OR function output signal OUT is 0 only when the input signal IN is 0 and the data signal D is 0 (the inverted data signal DB is 1).

[0072] Therefore, in CIM mode, the logic gate receives the input signal IN at input 170 and data from SRAM 132, and determines the CIM output OUT provided at output 172. Furthermore, each of the memory cells 24 and each of the NVM SRAM CIM cells 100, 130, and 200 can operate in both SRAM and NVM modes. In SRAM mode, data from the NVM SRAM CIM cells (such as each memory cell 24) is processed. Figure 1 (as shown) Figure 2 SRAM CIM cell 100 Figure 3 NVMSRAM CIM cell 130 and Figure 4 The NVM SRAM CIM cell 200 reads data from SRAMs (such as SRAM 102 and SRAM 132) and writes data to NVM SRAM CIM cells (such as each memory cell 24). Figure 1 (as shown) Figure 2 SRAM CIM cell 100 Figure 3 NVM SRAM CIM cell 130 and Figure 4 The SRAMs (such as SRAM 102 and SRAM 132) in the NVM SRAM CIM cell 200.

[0073] Figure 11 This is a diagram of Table 300 schematically illustrating read operations of SRAM 132 in one of the NVM SRAMCIM cells operating in SRAM mode, according to some embodiments. In SRAM mode, data can be read from and written to SRAM 132 regardless of the NVM (such as NVM 104, NVM 134, and RRAM 202).

[0074] During a read operation of SRAM 132, bit line BL 140 and the inverted bit line BLB 142 are pre-charged to a high voltage level 1, such as VDD. Then, the first word line WL 144 and the second word line WLB 146 are set to a high voltage level 1 to bias the first access control NMOS transistor 164 and the second access control NMOS transistor 166. This discharges either bit line BL 140 or the inverted bit line BLB 142 through SRAM 132, creating a voltage difference between bit line BL 140 and the inverted bit line BLB 142 that can be read by a sensing circuit.

[0075] Table 300 depicts reads 0 302 and 1 304. During read 0 302, bit line BL 140 and the inverted bit line BLB 142 are pre-charged to a high voltage level of 1. Then, the first word line WL 144 and the second word line WLB 146 are set to a high voltage level of 1, which biases the first access control NMOS transistor 164 and the second access control NMOS transistor 166. With the data signal D at a low voltage level of 0 and the inverted data signal DB at a high voltage level of 1, bit line BL 140 is discharged to a low voltage level of 0 through the first access control NMOS transistor 164, NVM, and the first NMOS transistor 154, while the inverted bit line BLB 142 remains at a high voltage level of 1. The voltage difference between bit line BL 140 at a low voltage level of 0 and the inverted bit line BLB 142 at a high voltage level of 1 is read by a sensing circuit.

[0076] During the read operation 1304, bit lines BL 140 and BLB 142 are pre-charged to a high voltage level of 1. Then, the first word line WL 144 and the second word line WLB 146 are set to a high voltage level of 1, which biases the first access control NMOS transistor 164 and the second access control NMOS transistor 166. When the data signal D is at a high voltage level of 1 and the inverted data signal DB is at a low voltage level of 0, bit line BL 140 remains at a high voltage level of 1, and bit line BLB 142 discharges to a low voltage level of 0 through the second access control NMOS transistor 166 and the second NMOS transistor 158. The voltage difference between bit line BL 140 at a high voltage level of 1 and the inverted bit line BLB 142 at a low voltage level of 0 is read by a sensing circuit.

[0077] Figure 12 This is a diagram schematically illustrating Table 310, which depicts the write operations of SRAM 132 in one of the NVM SRAMCIM cells operating in SRAM mode according to some embodiments.

[0078] In a write operation of SRAM132, one of bit line BL 140 and bit line BLB 142 is discharged to a low voltage level 0, such as ground, and the other of bit line BL 140 and inverted bit line BLB 142 is set to a high voltage level 1, such as VDD. Then, the first word line WL 144 and the second word line WLB 146 are set to a high voltage level 1 to bias the first access control NMOS transistor 164 and the second access control NMOS transistor 166. This discharges the corresponding one of the data signal D and the inverted data signal DB to a low voltage level 0, and sets or charges the other of the data signal D and the inverted data signal DB to a high voltage level 1, writing data into SRAM 132.

[0079] Table 310 describes writing 0 312 to SRAM 132, where the data signal D of SRAM 132 is set to 0, and writing 1 314 to SRAM 132, where the data signal D of SRAM 132 is set to 1. In writing 0 312, bit line BL 140 is discharged to a low voltage level 0, such as ground, and inverted bit line BLB 142 is set to a high voltage level 1, such as VDD. Then, the first word line WL 144 and the second word line WLB 146 are set to a high voltage level 1 to bias the first access control NMOS transistor 164 and the second access control NMOS transistor 166. This discharges the data signal D to a low voltage level 0 through the first access control NMOS transistor 164 and sets or charges the inverted data signal DB to a high voltage level 1 through the second access control NMOS transistor 166, writing 0 to SRAM 132.

[0080] In write 1314, bit line BL 140 is set or charged to a high voltage level 1, such as VDD, and bit line BLB 142 is discharged to a low voltage level 0, such as ground. Then, the first word line WL 144 and the second word line WLB 146 are set to a high voltage level 1 to bias the first access control NMOS transistor 164 and the second access control NMOS transistor 166. This sets or charges the data signal D to a high voltage level 1 via the first access control NMOS transistor 164 and discharges the inverted data signal DB to a low voltage level 0 via the second access control NMOS transistor 166, writing 1 to SRAM 132.

[0081] Therefore, in SRAM mode, from NVM SRAM CIM cells (such as memory cell 24) Figure 1 (as shown) Figure 2 NVM SRAM CIM cell 100 Figure 3 NVM SRAM CIM cell 130 and Figure 4 The NVM SRAM CIM cell 200 reads data from the SRAM (such as SRAM 102 and SRAM 132) in each of the NVM SRAM CIM cells 200, and writes data to the NVM SRAM CIM cells (such as memory cell 24). Figure 1 (as shown) Figure 2 NVM SRAM CIM cell 100 Figure 3 NVM SRAM CIM cell 130 and Figure 4 The SRAM (such as SRAM 102 and SRAM 132) in each of the NVM SRAM CIM cells 200.

[0082] Each of memory cell 24 and each of NVM SRAM CIM cells 100, 130, and 200 also operates in NVM mode. In NVM mode, during write operations including set operations (write logic 1) and reset operations (write logic 0), data is stored in a memory such as RRAM 202. Figure 4 In the NVM (as shown), SRAM 132 is used to call data during the call operation.

[0083] Figure 13 The diagram illustrates, according to some embodiments, a table 320 depicting write operations including a set operation (write logic 1) 322 and a reset operation (write logic 0) 324 for RRAM 202.

[0084] In the setup operation (write logic 1) 322 of RRAM 202, bit line BL 140 and bit line BLB 142 are discharged to a low voltage level. In some embodiments, bit line BL 140 and the reverse bit line BLB 142 are discharged to a low voltage level 0, such as ground. In some embodiments, bit line BL 140 and the reverse bit line BLB 142 are discharged to a low voltage level, such as about 0.8V or 0.9V.

[0085] In the setup operation (write logic 1), the first power supply voltage VDD1 148 is adjusted to a high-level setup voltage VSET, such as 2V, and the second power supply voltage VDD2 150 is adjusted to a power supply voltage, such as approximately 0.9V. The first word line WL 144 is then adjusted to a high word line voltage VWWL, such as 2V, and the second word line WBL 146 is adjusted to a power supply voltage level PWR, such as 1.2V. This biases the first access control NMOS transistor 164 and the second access control NMOS transistor 166. The inverted data signal DB is pulled to a low-level voltage, such as 0.2V to 0.3V, which biases the first PMOS transistor 152, and the data signal D is pulled to a high-level voltage, such as 1.8V, which biases the second NMOS transistor 158. RRAM202 conducts current from the high-voltage data signal D through RRAM202 to the low-voltage level on bit line data signal BLD and bit line BL140, which sets RRAM202 to a low-resistance state, i.e., a logic 1 state.

[0086] In the reset operation (write logic 0) 324 of RRAM 202, bit line BL 140 is charged to the reset voltage VRESET, which is a high voltage level, such as 1.6V, and bit line BLB 142 is charged to a high voltage level VDD, such as 0.9V. First power supply voltage VDD1148 and second power supply voltage VDD2 150 are adjusted to power supply voltages, such as approximately 0.9V. Then, first word line WL 144 is adjusted to a high word line voltage VWWL, such as 2V, and second word line WBL 146 is adjusted to power supply voltage level PWR, such as 1.2V. This bias turns on the first access control NMOS transistor 164 and the second access control NMOS transistor 166. The inverted data signal DB becomes a higher voltage level, which biases on the first NMOS transistor 154, and the data signal D becomes a lower voltage level, which biases on the second PMOS transistor 156. RRAM 202 conducts current from the high-voltage bit line BL 140 to the low-voltage data signal D, which resets RRAM 202 to a high-resistance state, i.e., logic 0.

[0087] Figure 14This is a schematic diagram illustrating Table 330, which depicts call operations from stored data in RRAM 202 according to some embodiments. The call operations of RRAM 202 include an initialization step 332 and a call step 334.

[0088] In initialization step 332, the data signal D is written to a low voltage level 0, and the inverted data signal DB is written to a high voltage level 1. Bit line BL 140 discharges to a low voltage level, such as ground, and bit line BLB 142 charges to a high voltage level, such as 0.9V. Next, the first word line WL 144 and the second word line WLB 146 are adjusted to a high voltage level VDD, such as 1.2V, which biases the first access control NMOS transistor 164 and the second access control NMOS transistor 166 to conduct. The data signal D is set to a low voltage level 0 and the inverted data signal DB is set to a high voltage level 1.

[0089] In step 334, bit line BL 140 is charged to a high voltage level VDD, such as 0.9V, and bit line BLB 142 is discharged to a low voltage level, such as ground. Then, the first word line WL 144 is adjusted to a high voltage level, such as 1.2V, and the second word line WLB 146 is adjusted to a low voltage level, such as ground. This biases the first access control NMOS transistor 164 on and biases the second access control NMOS transistor 166 off. If RRAM 202 is set to a low-resistance state (logic 1 state), the high-voltage bit line BL 140 pulls the data signal D to a high voltage level through the first access control NMOS transistor 164 and the low-resistance RRAM 202 to invoke data 1. If RRAM 202 is reset to a high-resistance state (logic 0 state), the data signal D remains at a low voltage level 0, and the inverted data signal DB remains at a high voltage level. In some embodiments, during step 334, the inverted bit line BLB 142 is charged to a high voltage level VDD, such as 0.9V.

[0090] Figure 15 This is an illustrative representation according to some embodiments. Figure 4 The timing diagram 400 shows the three operating modes of the NVM SRAM CIM cell 200. The NVM SRAM CIM cell 200 includes RRAM 202, inverter 204, and NOR gate 206 logic gates, which perform a logical AND function between the input signal IN and the data signal D (using the inverted data signal DB).

[0091] The NVM SRAM CIM cell 200 has three operating modes: SRAM mode, NVM mode, and CIM mode. SRAM mode operation includes the first four columns of timing diagram 400: SRAM Write 1 column 402, SRAM Read 1 column 404, SRAM Write 0 column 406, and SRAM Read 0 column 408. NVM mode operation includes the next four columns: RRAM Set column 410, RRAM Reset column 412, and RRAM Call column: RRAM Initialization column 414 and RRAM Call column 416. CIM mode operation includes CIM column 418.

[0092] Timing diagram 400 includes rows for twelve different signals, including row 420 for first word line WL (144), row 422 for second word line WLB (146), row 424 for bit line BL (140), row 426 for bit line BLB (142), row 428 for bit line data signal BLD (on one side of RRAM 202), row 430 for data signal D (on the other side of RRAM 202), row 432 for inverted data signal DB, row 434 for current flowing through the row of RRAM 202, row 436 for first power supply voltage VDD1 (148), row 438 for second power supply voltage VDD2 (150), row 440 for input signal IN at input 170, and row 442 for output signal OUT at output 172.

[0093] In timing diagram 400, the low resistance state of RRAM 202 is logic 1, and the high resistance state of RRAM 202 is logic 0. In this example, the low resistance state of RRAM 202 is a resistance of 1000 ohms, and the high resistance state of RRAM 202 is a resistance of 30,000 ohms.

[0094] When writing logic 1 into SRAM 132, as shown in SRAM Write 1 column 402, the first power supply voltage VDD1 148 and the second power supply voltage VDD2 150 are set to a high voltage level, such as 0.9V. Bit line BL 140 is set or charged to a high voltage level 1, such as 0.9V, and the inverted bit line BLB 142 is discharged to a low voltage level 0, such as ground. Then, the first word line WL 144 and the second word line WLB 146 are set to a high voltage level 1, such as 1.2V, to bias the first access control NMOS transistor 164 and the second access control NMOS transistor 166. This sets or charges the data signal D to a high voltage level 1, such as 0.9V, via the first access control NMOS transistor 164 and RRAM 202, where the current iRRAM flowing through RRAM 202 is very small, and discharges the inverted data signal DB to a low voltage level 0, such as ground, via the second access control NMOS transistor 166, writing 1 into SRAM 132.

[0095] In the read logic 1 from SRAM 132, as shown in SRAM Read 1 column 404, the first power supply voltage VDD1 148 and the second power supply VDD2 150 are set to a high voltage level, such as 0.9V. Bit line BL 140 and inverted bit line BLB 142 are precharged to a high voltage level 1, such as 0.9V, and then the first word line WL 144 and the second word line WLB 146 are set to a high voltage level 1, such as 1.2V, which biases the first access control NMOS transistor 164 and the second access control NMOS transistor 166 to conduct. If the data signal D is at a high voltage level 1, such as 0.9V, and the inverted data signal DB is at a low voltage level 0, such as ground (0V), then bit line BL 140 remains at a high voltage level 1, such as 0.9V, almost no current iRRAM flows through RRAM 202, and the inverted bit line BLB 142 is discharged to a low voltage level 0, such as ground, via the second access control NMOS transistor 166 and the second NMOS transistor 158. The voltage difference between bit line BL 140 at a high voltage level 1 (such as 0.9V) and inverted bit line BLB 142 at a low voltage level 0 (such as ground) is read by the sensing circuit.

[0096] When writing logic 0 into SRAM 132, as shown in SRAM Write 0 column 406, the first power supply voltage VDD1 148 and the second power supply voltage VDD2 150 are set to a high voltage level, such as 0.9V. Bit line BL 140 is discharged to a low voltage level 0, such as ground, and the inverted bit line BLB 142 is set to a high voltage level 1, such as 0.9V. Then, the first word line WL 144 and the second word line WLB 146 are set to a high voltage level 1, such as 0.9V, to bias the first access control NMOS transistor 164 and the second access control NMOS transistor 166. This discharges the bit line data signal BLD and the data signal D to a low voltage level 0, such as ground, via the first access control NMOS transistor 164 and RRAM 202, and the current iRRAM flows through RRAM 202, and sets or charges the inverted data signal DB to a high voltage level 1, such as 0.9V, via the second access control NMOS transistor 166, writing 0 into SRAM 132.

[0097] In the read logic 0 from SRAM 132, as shown in SRAM Read 0 column 408, the first power supply voltage VDD1 148 and the second power supply VDD2 150 are set to a high voltage level, such as 0.9V. Bit line BL 140 and inverted bit line BLB 142 are precharged to a high voltage level 1, such as 0.9V, and the first word line WL 144 and the second word line WLB 146 are set to a high voltage level 1, such as 1.2V, which biases the first access control NMOS transistor 164 and the second access control NMOS transistor 166 to conduct. If the data signal D is at a low voltage level 0, such as ground, and the inverted data signal DB is at a high voltage level 1, such as 0.9V, then bit line BL 140 discharges to a low voltage level 0, such as ground, through the first access control NMOS transistor 164, RRAM 202 (current iRRAM flows through RRAM 202), and the first NMOS transistor 154, and the inverted bit line BLB 142 remains at a high voltage level 1, such as 0.9V. The voltage difference between bit line BL 140 at a low voltage level 0 (such as ground) and inverted bit line BLB 142 at a high voltage level 1 (such as 0.9V) is read by the sensing circuit.

[0098] As previously mentioned, NVM mode operation includes the following four columns: RRAM setup column 410, RRAM reset column 412, RRAM initialization column 414, and RRAM call column 416.

[0099] In the setup operation (write logic 1) of RRAM 202, as shown in RRAM setup column 410, bit lines BL 140 and BLB 142 are stabilized to voltage levels such as approximately 0.8V or 0.9V. The first power supply voltage VDD1 148 is adjusted to a high voltage level setup voltage VSET, such as 2V, and the second power supply voltage VDD2 150 is adjusted to a power supply voltage, such as approximately 0.9V. Then, the first word line WL 144 is adjusted to a high word line voltage VWWL, such as 2V, and the second word line WBL 146 is adjusted to a power supply voltage level PWR, such as 1.2V. This biases and turns on the first access control NMOS transistor 164 and the second access control NMOS transistor 166. The inverted data signal DB is pulled to a low voltage level, such as 0.2V to 0.3V, which biases and turns on the first PMOS transistor 152, and the data signal D is pulled to a high voltage level, such as 1.8V when RRAM 202 is in a high-resistance state and 1.6V when RRAM 202 is in a low-resistance state, which biases and turns on the second NMOS transistor 158. RRAM 202 conducts a current iRRAM of approximately 40 microamps (µA) when RRAM 202 is in a high-resistance state and approximately 100 microamps (µA) when RRAM 202 is in a low-resistance state, and the bit line data signal BLD is set to approximately 0.9V when RRAM 202 is in a high-resistance state and approximately 1.4V when RRAM 202 is in a low-resistance state. RRAM 202 conducts current iRRAM from the high-voltage data signal D through RRAM 202 to the low-voltage level on bit line data signal BLD and bit line BL 140, which sets RRAM 202 to a low-resistance state, i.e., a logic 1 state.

[0100] In the reset operation (write logic 0) of RRAM 202, as shown in RRAM reset column 412, the first power supply voltage VDD1 148 and the second power supply voltage VDD2 150 are set to a high voltage level, such as 0.9V. Bit line BL 140 is charged to the reset voltage VRESET, which is a high voltage level, such as 1.6V, and the inverted bit line BLB 142 is charged to a high voltage level 1, such as 0.7V, when RRAM 202 is in a low resistance state, and to 0.9V when RRAM 202 is in a high resistance state. The first power supply voltage VDD1 148 and the second power supply voltage VDD2 150 are adjusted to the power supply voltage, such as approximately 0.9V. Then, the first word line WL 144 is adjusted to the high word line voltage VWWL, such as 2V, and the second word line WBL 146 is adjusted to the power supply voltage level PWR, such as 1.2V. This bias turns on the first access control NMOS transistor 164 and the second access control NMOS transistor 166. The inverted data signal DB reaches a higher voltage level, such as from 0.3V when RRAM 202 is in a low-resistance state to 0.9V when RRAM 202 is in a high-resistance state, which biases on the first NMOS transistor 154. The data signal D becomes a lower voltage level, such as from 1.4V when RRAM 202 is in a low-resistance state to 0.3V when RRAM 202 is in a high-resistance state, which biases on the second PMOS transistor 156. RRAM 202 conducts a current iRRAM of approximately -40 microamps (µA), and the bit line data signal BLD is set to approximately 1.3V. RRAM 202 conducts the current iRRAM from the high-voltage bit line BL 140 to the lower-voltage data signal D, which resets RRAM 202 to a high-resistance state, i.e., logic 0.

[0101] The call mode operation for retrieving stored data from RRAM 202 includes initialization step 332 described in RRAM initialization column 414 and call step 334 described in RRAM call column 416.

[0102] In initialization step 332, as shown in RRAM initialization column 414, the first power supply voltage VDD1 148 and the second power supply VDD2 150 are set to a high voltage level, such as 0.9V. The data signal D is written to a low voltage level 0, such as ground, and the inverted data signal DB is written to a high voltage level 1, such as 0.9V. Bit line BL 140 is set to a voltage level such as 0.6V to 0.8V, and the inverted bit line BLB 142 is charged to a high voltage level, such as 0.9V. Next, the first word line WL 144 and the second word line WLB 146 are adjusted to a high voltage level VDD, such as 1.2V, which biases the first access control NMOS transistor 164 and the second access control NMOS transistor 166 to conduct. The data signal D is set to a low voltage level 0, such as ground, and the inverted data signal DB is set to a high voltage level 1, such as 0.9V.

[0103] In step 334, as shown in RRAM call column 416, the first power supply voltage VDD1 148 and the second power supply voltage VDD2 150 are set to a high voltage level, such as 0.9V. Bit line BL 140 is charged to a high voltage level 1, such as 0.9V, and the inverted bit line BLB 142 can be charged to a high voltage level 1, such as 0.9V. Then, the first word line WL 144 is adjusted to a high voltage level, such as 1.2V, and the second word line WLB 146 is adjusted to a low voltage level, such as ground. This biases the first access control NMOS transistor 164 on and biases the second access control NMOS transistor 166 off. If RRAM 202 is in a low-resistance state (logic 1 state), the data signal D is pulled to a high voltage level 1, such as 0.9V, and the high-voltage bit line BL140 invokes data 1 via the first access control NMOS transistor 164 and the low-resistance RRAM 202, while pulling the inverted data signal DB to a low voltage level, such as ground. If RRAM 202 is in a high-resistance state (logic 0 state), the data signal D remains at a low voltage level 0, such as ground, and the inverted data signal DB remains at a high voltage level, such as 0.9V. In some embodiments, in invocation step 334, the inverted bit line BLB 142 is discharged to a low voltage level, such as ground.

[0104] The CIM mode operation of the NVM SRAM CIM cell 200 is shown in CIM column 418. The first power supply voltage VDD1 148 and the second power supply voltage VDD2 150 are set to a high voltage level, such as 0.9V. The input of inverter 204 is configured to receive the input signal IN at input 170, and the output of inverter 204 is electrically connected to one input of NOR gate 206. The other input of NOR gate 206 is connected to the inverted data signal DB of SRAM 132. In this configuration, inverter 204 and NOR gate 206 perform a logical AND function of the input signal IN and the data signal D (using the inverted data signal DB) to provide the CIM output OUT at output 172. In this example, the input signal IN is set to a high voltage level, such as 0.9V, and the output signal OUT is the inversion of the inverted data signal DB, i.e., the output signal OUT follows the data signal D.

[0105] Figure 16 This is a diagram schematically illustrating a method of operating a memory device, such as memory device 20, according to some embodiments. At 500, the method includes operation in each of the SRAM mode, NVM mode, and CIM mode in the memory device.

[0106] At 502, the method includes operating in SRAM mode to write data to and read data from SRAMs (such as SRAM 102 and SRAM 132). In some embodiments, operating in SRAM mode includes pre-charging bit line BL (such as bit line BL 140) and bit line BLB (such as bit line BLB 142) to a high voltage and turning on two transistors, such as first and second access control transistors 164 and 166, to read data from the SRAM. In some embodiments, operating in SRAM mode includes discharging one of bit line BL (such as bit line BL 140) or bit line BLB (such as bit line BLB 142) to a low voltage and pre-charging the other of bit line BL or bit line BLB to a high voltage, and turning on two transistors, such as first and second access control transistors 164 and 166, to write data to the SRAM.

[0107] At 504, the method includes operating in NVM mode to set, reset, and recall data from an NVM such as NVM 104, NVM 134, and RRAM 202. In some embodiments, the NVM is electrically connected to two cross-coupled inverters (such as two cross-coupled inverters 160 and 162) and electrically connected to one of two transistors (such as one of first and second access control transistors 164 and 166) that control access to the two cross-coupled inverters in the SRAM.

[0108] In some embodiments, operation in NVM mode includes discharging bit line BL (such as bit line BL 140) and bit line BLB (such as bit line BLB 142) to a low voltage, setting a supply voltage (such as one of supply voltages VDD1 148 and VDD2 150) to a set voltage VSET, and then turning on two transistors (such as first and second access control transistors 164 and 166) to set the NVM to a first state, such as a low-resistance state of RRAM. In some embodiments, operation in NVM mode includes charging one of bit line BL (such as bit line BL 140) and bit line BLB (such as bit line BLB 142) to a reset voltage VRESET, charging the other of bit line BL and bit line BLB 142 to a high voltage, and turning on these two transistors (such as first and second access control transistors 164 and 166) to reset the NVM to a second state, such as a high-resistance state of RRAM.

[0109] Furthermore, in some embodiments, operation in NVM mode includes discharging one of the bit lines BL (such as bit line BL 140) or BLB (such as bit line BLB 142) to a low voltage, charging the other of the bit lines BL or BLB to a high voltage, and turning on two transistors (such as first and second access control transistors 164 and 166) to initialize the call operation. Then, one of the bit lines BL or BLB is charged to a high voltage and one of the two transistors (such as first and second access control transistors 164 and 166) is turned on to determine the state of NVM.

[0110] At 506, the method includes operating in CIM mode to perform one or more logical functions on data from SRAM. The logical functions are performed on the data using logic gates (such as logic gates 106 and 136) electrically connected to the SRAM. In some embodiments, operating in CIM mode includes receiving an input signal IN and data from the SRAM at a logic gate and performing one or more logical functions on the input signal IN and the data.

[0111] Therefore, the disclosed embodiments include an NVM SRAM CIM cell, which includes an SRAM such as a six-transistor SRAM, an NVM configured to store data, and logic gates for performing CIM operations. The resulting NVM SRAM CIM cell is configured to store and retrieve data from the NVM. Storing data in the NVM, rather than in the SRAM or remote memory cell, reduces standby power consumption for data storage when the NVM SRAM CIM cell is completely powered off, and supports data retention during power outages. Retrieving data from the NVM reduces power consumption for data retrieval because the data is not transferred from a remote memory cell. Furthermore, using data stored in the SRAM for CIM operations improves the performance of CIM logic operations, where the NVM SRAM CIM cell uses data from the SRAM for high-speed CIM functions without the need for complex sensing and readout schemes.

[0112] The NVM SRAM CIM cell is configured to operate in three modes: SRAM mode, NVM mode, and CIM mode. In SRAM mode, data is written to and read from SRAM. In NVM mode, NVM can be set (i.e., written to 1), reset (i.e., written to 0), and data can be retrieved from NVM using SRAM. In CIM mode, logic gates receive one or more input signals and data from SRAM to compute the CIM output.

[0113] Furthermore, NVM SRAM CIM cells reduce area overhead, where the SRAM cells, combined with NVM back-end memory technology, allow data to be stored in NVM without area loss. In some embodiments, the memory device can be fabricated using a three-dimensional structure, which reduces the area used in the integrated circuit. In some embodiments, NVM can be replaced by gain cells such as transistors.

[0114] According to some embodiments, the memory device includes a static random access memory (SRAM) comprising two cross-coupled inverters and access transistors having gates connected to word lines. The memory device further includes one or more logic gates electrically coupled to the SRAM, and a non-volatile memory electrically coupled to the SRAM and configured to store data and be read using the SRAM, wherein the non-volatile memory is connected to the access transistors on one side and to the two cross-coupled inverters on the other side.

[0115] In some embodiments, the static random access memory (SRAM) includes a six-transistor SRAM, the six-transistor SRAM including four transistors forming the two cross-coupled inverters and two transistors including the access transistors for controlling access to the two cross-coupled inverters.

[0116] In some embodiments, the one or more logic gates are configured to perform logical operations using data from the static random access memory.

[0117] In some embodiments, the one or more logic gates are configured to receive an input signal and perform the logical operation on the input signal and the data from the static random access memory.

[0118] In some embodiments, the non-volatile memory includes resistive random access memory.

[0119] In some embodiments, the non-volatile memory includes one or more of resistive random access memory, magnetoresistive random access memory, ferroelectric random access memory, and / or phase-change random access memory.

[0120] In some embodiments, the one or more logic gates are configured to perform one or more logic functions among AND, OR, NOT, NAND, NOR, XOR, XNOR, and buffer functions.

[0121] In some embodiments, the memory device is configured to operate in three modes, including static random access memory mode, non-volatile memory mode, and in-memory computation mode.

[0122] In some embodiments, the static random access memory is configured to be written to and read from in the static random access memory mode.

[0123] In some embodiments, the non-volatile memory is configured to be set, reset, and invoked using the static random access memory in the non-volatile memory mode.

[0124] According to a further embodiment, a memory device includes a static random access memory (SRAM) cell comprising a cross-coupled first inverter and a second inverter, a first access transistor and a second access transistor configured to selectively connect the cross-coupled first inverter and the second inverter to a first bit line and a second bit line, a non-volatile memory connected in series between the first inverter and the first access transistor, and logic circuitry having a first input connected between the second inverter and the second access transistor and a second input configured to receive an external input signal.

[0125] In some embodiments, the memory device includes one or more logic gates electrically coupled to the static random access memory, wherein the one or more logic gates are configured to perform logical operations using data from the static random access memory.

[0126] In some embodiments, the memory device is configured to operate in a static random access memory mode, a non-volatile memory mode, and a compute-in-memory mode.

[0127] In some embodiments, the static random access memory is configured to be written to and read from in the static random access memory mode.

[0128] In some embodiments, the non-volatile memory is configured to be set, reset, and invoked using the static random access memory in the non-volatile memory mode.

[0129] According to a further disclosed aspect, a method of operating a memory device includes operating in each of the following modes: a static random access memory (SRAM) mode, a non-volatile memory (NRAM) mode, and a compute-in-memory mode. The method further includes: operating in the SRAM mode to write data to and read data from the SRAM; operating in the NRAM mode to set, reset, and retrieve data from the NRAM, the NRAM being electrically connected to two cross-coupled inverters in the SRAM and one of two transistors controlling access to the two cross-coupled inverters; and operating in the compute-in-memory mode to perform one or more logical functions on data from the SRAM using logic gates electrically connected to the SRAM.

[0130] In some embodiments, operation in the static random access memory mode includes: precharging the bit line and the inverted bit line to a high voltage and turning on the two transistors to read data from the static random access memory; and discharging the bit line or the inverted bit line to a low voltage and turning on the two transistors to write data into the static random access memory.

[0131] In some embodiments, operating in the non-volatile memory mode includes: discharging the bit line and the inverted bit line to a low voltage and turning on the two transistors to set the non-volatile memory to a first state; and charging the bit line and the inverted bit line to a high voltage and turning on the two transistors to reset the non-volatile memory to a second state.

[0132] In some embodiments, operating in the non-volatile memory mode includes: discharging one of the bit lines or the inverted bit lines to a low voltage and charging the other of the bit lines or the inverted bit lines to a high voltage and turning on the two transistors to initialize a call operation; and charging one of the bit lines or the inverted bit lines to the high voltage and turning on one of the two transistors to determine the state of the non-volatile memory.

[0133] In some embodiments, operating in the computation mode in the memory includes: receiving an input signal at the logic gate; receiving the data from the static random access memory at the logic gate; and performing one or more logic functions on the input signal and the data.

[0134] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A memory device, comprising: A static random access memory includes two cross-coupled inverters and two access transistors having gates connected to word lines and controlling access to the two inverters; One or more logic gates are electrically coupled to the static random access memory; as well as A non-volatile memory, electrically coupled to the static random access memory and configured to store data and be read using the static random access memory, wherein the non-volatile memory is connected to the access transistor on one side and to the two cross-coupled inverters on the other side; Specifically, one of the bit lines or the inverted bit lines is discharged to a low voltage while the other of the bit lines or the inverted bit lines is charged to a high voltage and the two access transistors are turned on to initiate a data retrieval operation from the non-volatile memory. One of the bit lines or the inverted bit lines is charged to the high voltage and one of the two access transistors is turned on to determine the state of the non-volatile memory.

2. The memory device according to claim 1, wherein, The static random access memory (SRAM) includes a six-transistor SRAM, comprising four transistors forming the two cross-coupled inverters and two transistors controlling access to the two cross-coupled inverters, the two transistors including the access transistors.

3. The memory device according to claim 2, wherein, The one or more logic gates are configured to perform logical operations using data from the static random access memory.

4. The memory device according to claim 3, wherein, The one or more logic gates are configured to receive an input signal and perform the logic operation on the input signal and the data from the static random access memory.

5. The memory device according to claim 1, wherein, The non-volatile memory includes resistive random access memory.

6. The memory device according to claim 1, wherein, The non-volatile memory includes one or more of resistive random access memory, magnetoresistive random access memory, ferroelectric random access memory, and / or phase change random access memory.

7. The memory device according to claim 1, wherein, The one or more logic gates are configured to perform one or more logic functions among AND, OR, NOT, NAND, NOR, XOR, XNOR, and buffer functions.

8. The memory device according to claim 1, wherein, The memory device is configured to operate in three modes, including static random access memory mode, non-volatile memory mode, and in-memory computation mode.

9. The memory device according to claim 8, wherein, The static random access memory is configured to be written to and read from in the static random access memory mode.

10. The memory device according to claim 8, wherein, The non-volatile memory is configured to be set, reset, and invoked using the static random access memory in the non-volatile memory mode.

11. A memory device, comprising: A static random access memory cell includes a cross-coupled first inverter and a second inverter, and a first access transistor and a second access transistor configured to selectively connect the cross-coupled first inverter and the second inverter to a first bit line and a second bit line. A non-volatile memory, connected in series between the first inverter and the first access transistor, is configured to store data and to retrieve data from the non-volatile memory using the static random access memory cells. as well as A logic circuit having a first input connected between the second inverter and the second access transistor and a second input configured to receive an external input signal; Specifically, one of the bit lines or the inverted bit lines is discharged to a low voltage, while the other of the bit lines or the inverted bit lines is charged to a high voltage, and the first access transistor and the second access transistor are turned on to initialize the call operation. One of the bit lines or the inverted bit lines is charged to the high voltage and one of the first access transistor and the second access transistor is turned on to determine the state of the non-volatile memory.

12. The memory device of claim 11, comprising one or more logic gates electrically coupled to the static random access memory, wherein, The one or more logic gates are configured to perform logical operations using data from the static random access memory.

13. The memory device according to claim 11, wherein, The memory device is configured to operate in static random access memory mode, non-volatile memory mode, and in-memory computing mode.

14. The memory device according to claim 13, wherein, The static random access memory is configured to be written to and read from in the static random access memory mode.

15. The memory device according to claim 13, wherein, The non-volatile memory is configured to be set, reset, and invoked using the static random access memory in the non-volatile memory mode.

16. A method of operating a memory device, the method comprising: Operates in each of the following modes in memory devices: static random access memory mode, non-volatile memory mode, and in-memory computing mode; Operate in the static random access memory mode to write data to and read data from the static random access memory; Operating in the non-volatile memory mode to set, reset, and retrieve data from the non-volatile memory, the non-volatile memory being electrically connected to two cross-coupled inverters in the static random access memory and one of two transistors controlling access to the two cross-coupled inverters; as well as Operating in computation mode within the memory to perform one or more logical functions on data from the static random access memory using logic gates electrically connected to the static random access memory; The operation in the non-volatile memory mode includes: Discharge one of the bit line or the inverted bit line to a low voltage and charge the other of the bit line or the inverted bit line to a high voltage and turn on both transistors to initialize the call operation; and One of the bit lines or the inverted bit lines is charged to the high voltage and one of the two transistors is turned on to determine the state of the non-volatile memory.

17. The method of claim 16, wherein, Operation in the static random access memory mode includes: The bit line and the inverted bit line are pre-charged to a high voltage and the two transistors are turned on to read data from the static random access memory; and Discharge the bit line or the reverse bit line to a low voltage and turn on the two transistors to write data into the static random access memory.

18. The method of claim 16, wherein, Operation in the non-volatile memory mode includes: Discharge the bit line and the inverted bit line to a low voltage and turn on the two transistors to set the non-volatile memory to a first state; and The bit line and the inverted bit line are charged to a high voltage and the two transistors are turned on to reset the non-volatile memory to a second state.

19. The method of claim 16, wherein, The non-volatile memory includes resistive random access memory.

20. The method of claim 16, wherein, Operation in the computation mode within the memory includes: The input signal is received at the logic gate; The data from the static random access memory is received at the logic gate; and Perform one or more logical functions on the input signal and the data.

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