Memory circuit and method of operation thereof

Abstract

A memory circuit includes a global control circuit, a first local control circuit, and a first set of word line post-decoder circuitry coupled to a first set of memory cells configured to store a first set of data. The global control circuit is configured to generate a first set of global predecoder signals, a second set of global predecoder signals, and a first set of local address signals. The first local control circuit includes a first set of repeater circuitry and a first clock predecoder circuitry. The first set of repeater circuitry is configured to generate a first and second set of local predecoder signals in response to a corresponding first and second set of global predecoder signals. The first clock predecoder circuitry is configured to generate a first and second set of clock signals in response to the first set of local address signals and a first clock signal. Embodiments of the present application also provide methods of operating a memory circuit.

Description

Technical Field

[0001] Embodiments of this application relate to memory circuits and methods of operation thereof. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has developed a wide variety of digital devices to solve problems in many different fields. Some of these digital devices, such as memory macros, are configured to store data. As ICs become smaller and more complex, the resistance of the wires within these digital devices also changes, affecting the operating voltage of these devices and the overall performance of the IC. Summary of the Invention

[0003] According to one aspect of an embodiment of this application, a memory circuit is provided, comprising: a global control circuit configured to generate a first set of global pre-decoder signals, a second set of global pre-decoder signals, and a first set of local address signals in response to a memory address signal and a first clock signal; a first local control circuit coupled to the global control circuit, the first local control circuit comprising: a first set of repeater circuits configured to generate the first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and to generate the second set of local pre-decoder signals in response to the second set of global pre-decoder signals; a first clock pre-decoder circuit coupled to the global control circuit and configured to generate the first set of clock signals and the second set of clock signals in response to the first set of local address signals and the first clock signal; a first set of word-line decoder circuits coupled to the first clock pre-decoder circuit and the first set of repeater circuits and configured to generate the first set of word-line signals in response to the first set of clock signals, the first set of local pre-decoder signals, and the second set of local pre-decoder signals; and a first set of memory cells coupled to the first set of word-line decoder circuits and configured to store a first set of data in response to at least the first set of word-line signals.

[0004] According to another aspect of the embodiments of this application, a memory circuit is provided, comprising: a global control circuit configured to generate a first set of global pre-decoder signals, a second set of global pre-decoder signals, and a first set of local address signals in response to a memory address signal and a first clock signal; a first local control circuit coupled to the global control circuit, the first local control circuit comprising: a first clock pre-decoder circuit coupled to the global control circuit and configured to generate a first set of clock signals and a second set of clock signals in response to the first set of local address signals and the first clock signal; and a first word line driver circuit, the first word line driver circuit comprising: The first set of repeater circuits is configured to generate a first set of local pre-decoder signals in response to a first set of global pre-decoder signals, and to generate a second set of local pre-decoder signals in response to a second set of global pre-decoder signals; and a first set of word-line post-decoder circuits are coupled to the first clock pre-decoder circuit and the first set of repeater circuits, and are configured to generate a first set of word-line signals in response to the first set of clock signals, the first set of local pre-decoder signals and the second set of local pre-decoder signals; and a first set of memory cells are coupled to the first set of word-line post-decoder circuits, and are configured to store a first set of data in response to at least the first set of word-line signals.

[0005] According to another aspect of the embodiments of this application, a method for operating a memory circuit is provided, the method comprising: generating a first set of global pre-decoder signals, a second set of global pre-decoder signals, and a first set of local address signals by a global control circuit in response to a memory address signal and a first clock signal; generating a first set of clock signals and a second set of clock signals by a first clock pre-decoder circuit in response to the first set of local address signals and the first clock signal, the first clock pre-decoder circuit being coupled to the global control circuit; generating a first set of local pre-decoder signals by a first set of repeater circuits in response to the first set of global pre-decoder signals, and generating a second set of local pre-decoder signals in response to the second set of global pre-decoder signals; generating a first set of word line signals by a first set of word line decoder circuits in response to the first set of clock signals, the first set of local pre-decoder signals, and the second set of local pre-decoder signals, the first set of word line decoder circuits being coupled to the first clock pre-decoder circuit and the first set of repeater circuits; and storing a first set of data in a first set of memory cells in response to at least the first set of word line signals, the first set of memory cells being coupled to the first set of word line decoder circuits. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a block diagram of a memory circuit according to some embodiments.

[0008] Figure 2A This is a circuit diagram of a memory circuit according to some embodiments.

[0009] Figure 2B This is a simplification for ease of explanation. Figure 2A The circuit diagram of part of the memory circuit.

[0010] Figure 3 This is a circuit diagram of a memory circuit according to some embodiments.

[0011] Figure 4 This is a circuit diagram of a memory circuit according to some embodiments.

[0012] Figure 5 This is a circuit diagram of a memory circuit according to some embodiments.

[0013] Figure 6 This is a circuit diagram of a memory circuit according to some embodiments.

[0014] Figure 7 This is a circuit diagram of a circuit according to some embodiments.

[0015] Figure 8 This is a circuit diagram of a circuit according to some embodiments.

[0016] Figure 9A This is a circuit diagram of a pre-decoder circuit according to some embodiments.

[0017] Figure 9B This is a circuit diagram of a pre-decoder circuit according to some embodiments.

[0018] Figure 10 This is a circuit diagram of an address latch circuit according to some embodiments.

[0019] Figure 11 This is a circuit diagram of a clock pre-decoder circuit according to some embodiments.

[0020] Figure 12 This is a circuit diagram of a post-word line decoder circuit group according to some embodiments.

[0021] Figure 13 According to some embodiments Figure 1 and Figures 2A-2B Circuit diagram of the memory cells that can be used in the system.

[0022] Figure 14 This is a flowchart of a method for operating circuits according to some embodiments. Detailed Implementation

[0023] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components, materials, values, steps, arrangements, etc., are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. Other components, materials, values, steps, arrangements, etc., are contemplated. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0024] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0025] According to some embodiments, the memory circuitry includes a global control circuitry configured to generate a first set of global pre-decoder signals, a second set of global pre-decoder signals, and a first set of local address signals in response to a memory address signal and a first clock signal.

[0026] In some embodiments, the memory circuitry further includes a first local control circuit coupled to the global control circuitry. In some embodiments, the first local control circuitry includes a first set of repeater circuits configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and to generate a second set of local pre-decoder signals in response to the second set of global pre-decoder signals.

[0027] In some embodiments, by repeating or creating local variations of the first set of global predecoder signals or the second set of global predecoder signals, corresponding first set of local predecoder signals or second set of local predecoder signals are generated. Compared with other methods, the drive strength of the first set of local predecoder signals or second set of local predecoder signals from each set of repeater circuits is increased, thereby resulting in timing improvements in the address setting time of the memory circuit of the present invention compared with other methods.

[0028] Figure 1 This is a block diagram of a memory circuit 100 according to some embodiments.

[0029] For illustrative purposes, Figure 1 The design has been simplified. In some embodiments, the memory circuitry 100 includes, in addition to Figure 1 Various elements other than those described herein or arranged in other ways to perform the operations discussed below.

[0030] The memory circuit 100 is an IC that includes memory partitions 102A-102D, a global control circuit 100GC, and a global input / output (GIO) circuit 100BL.

[0031] Each memory partition 102A-102D includes memory banks 110U and 110L adjacent to word line (WL) driver circuitry 110AC and local control circuitry 110LC. Each memory bank 110U and 110L includes memory cell array 110AR and local input / output (LIO) circuitry 110BS.

[0032] Memory partitions, such as memory partitions 102A-102D, are portions of memory circuitry 100. A memory partition includes subgroups of memory devices. Figure 1 (Not shown in the image) and adjacent circuitry of a subgroup configured to selectively access the memory device for programming and read operations. Figure 1 In the illustrated embodiment, the memory circuit 100 comprises a total of four partitions. In some embodiments, the memory circuit 100 comprises a total number of partitions greater than or less than four.

[0033] GIO circuit 100BL is a circuit configured to control access to one or more electrical paths (e.g., bit lines) of each memory device in each memory bank 110U or 110L of each memory partition 102A-102D, for example, by generating one or more bit line signals. In some embodiments, GIO circuit 100BL includes global bit line driver circuitry. In some embodiments, GIO circuit 100BL is coupled to each memory bank 110U and 110L via corresponding global bit lines (not shown).

[0034] The global control circuit 100GC is configured, for example, to control some or all programming and read operations on each memory partition 102A-102D by generating and / or outputting one or more control signals and / or enable signals. In some embodiments, circuit 100F includes clock generation / gating circuitry (such as...). Figure 2A (as shown) and address latches and pre-decoder circuits (as shown) Figure 2A (As shown).

[0035] In some embodiments, the clock generation / gating circuitry is configured to respond to an external clock signal (e.g., Figure 2ACLK in the chip and chip enable signals (e.g.) Figure 2A The CE in the memory circuit 100 generates an internal clock signal (e.g., ...). Figure 2A In some embodiments, the address latch and pre-decoder circuitry are configured to respond to an address signal (e.g., ICLK). Figure 2A The memory address signal (ADR) generates an address signal group (e.g., Figure 2A LADR[0:10] in the first group of global pre-decoder signals PREDEC1_GLOBAL (e.g., LADR[0:10]) Figure 2A (as shown) and the second group of global pre-decoder signals PREDEC2_GLOBAL (as shown) Figure 2A (As shown).

[0036] In some embodiments, the global control circuit 100GC includes one or more analog circuits configured to interface with memory partitions 102A-102D, enabling data to be programmed in one or more memory devices, and / or using data received from one or more memory devices in one or more circuit operations. In some embodiments, the global control circuit 100GC includes one or more global address decoder or pre-decoder circuits configured to output one or more address signals to the WL driver circuit 110AC of each memory partition 102A-102D.

[0037] Each WL driver circuit 110AC is configured to generate a word line signal on the corresponding word line WL. In some embodiments, each WL driver circuit 110AC is configured to output the word line signal on the corresponding word line WL to adjacent memory banks 110U and 110L of the corresponding memory partitions 102A-102D.

[0038] Each local control circuit 110LC is an electronic circuit configured to receive one or more address signals. Each local control circuit 110LC is configured to generate a signal corresponding to an adjacent subgroup of memory devices identified by the one or more address signals. In some embodiments, the adjacent subgroups of memory devices correspond to columns of memory devices. In some embodiments, each local control circuit 110LC is configured to generate each signal as a complementary signal pair. In some embodiments, each local control circuit 110LC is configured to output a signal to a corresponding word line driver circuit within the adjacent WL driver circuit 110AC of the corresponding memory partitions 102A-102D. In some embodiments, the local control circuit 110DC includes a volume decoder circuit.

[0039] Each LIO circuit 110BS is configured, for example, to selectively access one or more bit lines of an adjacent subgroup of memory devices coupled to the corresponding memory cell array 110AR, in response to one or more BL control signals. Figure 2A (as shown in the diagram). In some embodiments, adjacent subgroups of the memory device correspond to rows of the memory device. In some embodiments, the LIO circuit 110BS includes a bit line selection circuit.

[0040] Each memory bank 110U and 110L includes a corresponding memory cell array 110AR, which includes memory cells or memory devices 112 configured to be accessed in programming and reading operations of adjacent LIO circuits 110BS and adjacent WL driver circuits 110AC.

[0041] Each memory cell array 110AR includes an array of memory devices 112 having N rows and M columns, where M and N are positive integers. The cell rows in the memory cell array 102 are arranged along a first direction X. The cell columns in the memory cell array 102 are arranged along a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. In some embodiments, each memory cell array 110AR is divided into an upper region and a lower region (e.g., ...). Figure 2A (As shown).

[0042] Memory device 112 is shown in memory banks 110U and 110L of memory partition 102A. For ease of illustration, memory device 112 is not shown in memory banks 110U and 110L of memory partitions 102B, 102C and 102D.

[0043] Memory device 112 is an electrical, electromechanical, electromagnetic, or other device configured to store bit data represented by logical states. At least one logical state of memory device 112 can be programmed in a write operation and detected in a read operation. In some embodiments, the logical state corresponds to the voltage level of a charge stored in a given memory device 112. In some embodiments, the logical state corresponds to a physical property of a component of a given memory device 112, such as voltage, current, resistance, or magnetic direction.

[0044] In some embodiments, memory device 112 includes one or more single-port (SP) static random access memory (SRAM) cells. In some embodiments, memory device 112 includes one or more dual-port (DP) SRAM cells. In some embodiments, memory device 112 includes one or more multi-port SRAM cells. Different types of memory cells in memory device 112 are contemplated within the scope of this disclosure. In some embodiments, memory device 112 includes one or more dynamic random access memory (DRAM) cells. In some embodiments, memory device 112 includes one or more one-time programmable (OTP) memory devices, such as electronic fuse or antifuse devices, flash memory devices, random access memory (RAM) devices, resistive RAM devices, ferroelectric RAM devices, magnetoresistive RAM devices, erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, etc. In some embodiments, memory device 112 is an OTP memory device including one or more OTP memory cells.

[0045] Other configurations of the memory circuit 100 are within the scope of this disclosure.

[0046] Figure 2A This is a circuit diagram of a memory circuit 200 according to some embodiments.

[0047] Figure 2B This is a simplification for ease of explanation. Figure 2A The circuit diagram shows a portion 200B of the memory circuit 200. For example, portion 200B of the memory circuit 200 shows a clock gating circuit 202, an address latch and pre-decoder circuit 204, a clock pre-decoder circuit group 220, a repeater circuit group 230, word-line post-decoder circuit groups 240, 242, 244 and 246, wires 260, 262 and 264, and wire groups 250 and 252.

[0048] Memory circuit 200 is Figure 1 The embodiments of memory circuit 100 are described below, and therefore similar detailed descriptions are omitted. For example, the WL driver circuits 212a and 212b of memory circuit 200 are embodiments of word line driver circuit 110AC, and the local control circuit 214a of memory circuit 200 is an embodiment of local control circuit 110LC.

[0049] The memory circuit 200 includes memory partitions 102A-102D, a global control circuit 201, and a GIO circuit 100BL.

[0050] Each memory partition 102A-102D includes memory banks 110U and 110L adjacent to WL driver circuitry 212 and local control circuitry 214a. Each memory bank 110U and 110L includes memory cell array 210 and LIO circuitry 110BS.

[0051] and Figure 1 Compared to the memory circuit 100, the global control circuit 201 is an embodiment of the global control circuit 100GC, each memory cell array 210 is an embodiment of the memory cell array 110AR, each local control circuit 214a is an embodiment of the local control circuit 110LC, and each of the WL driver circuits 212 is an embodiment of the WL driver circuit 110AC, and thus similar detailed descriptions are omitted.

[0052] and Figure 1 Compared to each memory cell array 110AR, each memory cell array 210 is divided into an upper region of memory cell 210a and a lower region of memory cell 210b, and therefore a similar detailed description is omitted.

[0053] and Figure 1 Compared to each WL driver circuit 110AC, each WL driver circuit 212 is divided into WL driver circuit 212a and WL driver circuit 212b, and therefore similar detailed descriptions are omitted.

[0054] The global control circuit 201 includes a clock gating circuit 202 and an address latch and pre-decoder circuit 204.

[0055] The clock gating circuit 202 is configured to generate a clock signal ICLK in response to a clock signal CLK and a chip enable signal CE. In some embodiments, the clock signal ICLK is referred to as an "internal clock signal" because the clock signal ICLK is generated within or inside the memory circuit 200. In some embodiments, the clock signal CLK is referred to as an "external clock signal" because the clock signal CLK is generated outside or outside the memory circuit 200.

[0056] In some embodiments, if the chip enable signal CE is logic "1", the clock gating circuit 202 is enabled and configured to transmit the clock signal CLK, and the clock signal ICLK is equal to the clock signal CLK. In some embodiments, if the chip enable signal CE is logic "0", the clock gating circuit 202 is disabled and configured not to transmit the clock signal CLK, and the clock signal ICLK is equal to logic "0". Other logic values ​​for the chip enable signal CE of the clock gating circuit 202 are also within the scope of this disclosure.

[0057] Clock gating circuit 202 is coupled to clock pre-decoder circuits 220a, 220b, 220c, and 220d (collectively referred to as "clock pre-decoder circuit group 220") and address latch and pre-decoder circuit 204. Clock gating circuit 202 is configured to output clock signal ICLK to clock pre-decoder circuit group 220 and address latch and pre-decoder circuit 204.

[0058] The address latch and pre-decoder circuit 204 is configured to generate address signal group LADR[0:10], global pre-decoder signal group PREDEC1_GLOBAL, and global pre-decoder signal group PREDEC2_GLOBAL in response to the memory address signal ADR.

[0059] In some embodiments, the memory address signal ADR and the address signal group LADR[0:10] comprise 11 bits (e.g., written as [0:10]). In some embodiments, the address signal group LADR[0:10] is divided into a first group of address signals LADR[0:4], a second group of address signals LADR[5:7], and a third group of address signals LADR[8:10].

[0060] In some embodiments, the first set of address signals LADR[0:4] comprises 5 bits, and these 5 bits are located at bit positions 0:4 in the address signal group LADR[0:10]. In some embodiments, the second set of address signals LADR[5:7] comprises 3 bits, and these 3 bits are located at bit positions 5:7 in the address signal group LADR[0:10]. In some embodiments, the third set of address signals LADR[8:10] comprises 3 bits, and these 3 bits are located at bit positions 8:10 in the address signal group LADR[0:10].

[0061] In some embodiments, at least one of the global predecoder signal groups PREDEC1_GLOBAL or PREDEC2_GLOBAL includes 8 bits, and these 8 bits are located at bit positions 0:7 in the corresponding global predecoder signal group PREDEC1_GLOBAL[0:7] or global predecoder signal group PREDEC2_GLOBAL[0:7].

[0062] The number or position of other bits used for at least one of the memory address signals ADR, address signal group LADR[0:10], first group address signals LADR[0:4], second group address signals LADR[5:7], third group address signals LADR[8:10], global predecoder signal group PREDEC1_GLOBAL, or global predecoder signal group PREDEC2_GLOBAL are all within the scope of this disclosure.

[0063] The address latch and pre-decoder circuit 204 is coupled to the clock pre-decoder circuit group 220 via wire 244. The address latch and pre-decoder circuit 204 is configured to output a first set of address signals LADR[0:4] to the clock pre-decoder circuit group 220 via wire 244.

[0064] Address latch and pre-decoder circuit 204 is coupled to repeater circuit groups 230a, 230b, 230c, and 230d via wires 260 and 262. Address latch and pre-decoder circuit 204 is configured to output the global pre-decoder signal group PREDEC1_GLOBAL to repeater circuit groups 230a, 230b, 230c, and 230d via wire 260. Address latch and pre-decoder circuit 204 is configured to output the global pre-decoder signal group PREDEC2_GLOBAL to repeater circuit groups 230a, 230b, 230c, and 230d via wire 262.

[0065] In some embodiments, wire 260 is referred to as a first global predecoder line, and wire 262 is referred to as a second global predecoder line. In some embodiments, at least one of wires 260 or 262 extends in a second direction Y through each of the memory partitions 102A-102D of the memory circuit 200.

[0066] Local control circuit 214a in memory partition 102A includes clock pre-decoder circuit 220d and repeater circuit group 230d. Local control circuit 214a in memory partition 102B includes clock pre-decoder circuit 220c and repeater circuit group 230c. Local control circuit 214a in memory partition 102C includes clock pre-decoder circuit 220b and repeater circuit group 230b. Local control circuit 214a in memory partition 102D includes clock pre-decoder circuit 220a and repeater circuit group 230a.

[0067] Each clock predecoder circuit 220a, 220b, 220c, or 220d in the clock predecoder circuit group 220 is configured to receive a first set of address signals LADR[0:4] and a clock signal ICLK. Each clock predecoder circuit 220a, 220b, 220c, or 220d in the clock predecoder circuit group 220 is configured to generate a clock signal group ICKD_TOP[0:3] and a clock signal group ICKD_BOT[0:3] in response to the first set of address signals LADR[0:4] and the clock signal ICLK.

[0068] In some embodiments, at least one of the clock signal groups ICKD_TOP[0:3] or ICKD_BOT[0:3] includes 4 bits, and these 4 bits are located at bit positions 0:3 in the corresponding clock signal group ICKD_TOP[0:3] or clock signal group ICKD_BOT[0:3].

[0069] The number or position of other bits used in at least one of the clock signal groups ICKD_TOP[0:3] or ICKD_BOT[0:3] is within the scope of this disclosure.

[0070] The clock pre-decoder circuit 220a is further coupled to word-line post-decoder circuit groups 240a and 240b. The clock pre-decoder circuit 220a is configured to output the clock signal group ICKD_TOP[0:3] to the word-line post-decoder circuit group 240a and the clock signal group ICKD_BOT to the word-line post-decoder circuit group 240b.

[0071] The clock pre-decoder circuit 220b is further coupled to word-line post-decoder circuit groups 242a and 242b. The clock pre-decoder circuit 220b is configured to output the clock signal group ICKD_TOP[0:3] to the word-line post-decoder circuit group 242a and the clock signal group ICKD_BOT to the word-line post-decoder circuit group 242b.

[0072] The clock pre-decoder circuit 220c is further coupled to word-line post-decoder circuit groups 244a and 244b. The clock pre-decoder circuit 220c is configured to output the clock signal group ICKD_TOP[0:3] to the word-line post-decoder circuit group 244a and the clock signal group ICKD_BOT to the word-line post-decoder circuit group 244b.

[0073] The clock pre-decoder circuit 220d is further coupled to word-line post-decoder circuit groups 246a and 246b. The clock pre-decoder circuit 220d is configured to output the clock signal group ICKD_TOP[0:3] to the word-line post-decoder circuit group 246a and the clock signal group ICKD_BOT to the word-line post-decoder circuit group 246b.

[0074] Each of the repeater circuit groups 230a, 230b, 230c or 230d is configured to generate a local predecoder signal group PREDEC1_LOCAL in response to the global predecoder signal group PREDEC1_GLOBAL, and to generate a local predecoder signal group PREDEC2_LOCAL in response to the global predecoder signal group PREDEC2_GLOBAL.

[0075] In some embodiments, at least one of the repeater circuit groups 230a, 230b, 230c, or 230d is a corresponding buffer circuit group or a corresponding inverter group (e.g., ...). Figure 3 (As shown).

[0076] In some embodiments, at least one of the local predecoder signal groups PREDEC1_LOCAL or PREDEC2_LOCAL includes 8 bits, and the 8 bits are located at bit positions 0:7 in the corresponding local predecoder signal group PREDEC1_LOCAL[0:7] or local predecoder signal group PREDEC2_LOCAL[0:7].

[0077] The number or position of other bits used for at least one of the local predecoder signal groups PREDEC1_LOCAL or PREDEC2_LOCAL is within the scope of this disclosure.

[0078] Repeater circuit group 230a is further coupled to word-line post-decoder circuit groups 240a and 240b via wires 250a and 252a. Repeater circuit group 230a is configured to supply power to each of the output local pre-decoder signal groups PREDEC1_LOCAL and PREDEC2_LOCAL in word-line post-decoder circuit groups 240a and 240b via the respective wires 250a and 252a.

[0079] Repeater circuit group 230b is further coupled to word-line post-decoder circuit groups 242a and 242b via wires 250b and 252b. Repeater circuit group 230b is configured to supply power to each of the output local pre-decoder signal groups PREDEC1_LOCAL and PREDEC2_LOCAL in word-line post-decoder circuit groups 242a and 242b via corresponding wires 250b and 252b.

[0080] Repeater circuit group 230c is further coupled to word-line post-decoder circuit groups 244a and 244b via wires 250c and 252c. Repeater circuit group 230c is configured to supply power to each output local pre-decoder signal group PREDEC1_LOCAL and local pre-decoder signal group PREDEC2_LOCAL in word-line post-decoder circuit groups 244a and 244b via corresponding wires 250c and 252c.

[0081] Repeater circuit group 230d is further coupled to word-line post-decoder circuit groups 246a and 246b via wires 250d and 252d. Repeater circuit group 230d is configured to supply power to each output local pre-decoder signal group PREDEC1_LOCAL and local pre-decoder signal group PREDEC2_LOCAL in word-line post-decoder circuit groups 246a and 246b via corresponding wires 250d and 252d.

[0082] In some embodiments, at least one of wires 250a, 250b, 250c, or 250d in wire group 250 is referred to as a first local pre-decoder line, and at least one of wires 252a, 252b, 252c, or 252d in wire group 252 is referred to as a second local pre-decoder line. In some embodiments, at least one of wires 250a, 250b, 250c, or 250d extends along a second direction Y within a corresponding memory partition 102A, 102B, 102C, or 102D of memory circuit 200. In some embodiments, at least one of wires 252a, 252b, 252c, or 252d extends along a second direction Y within a corresponding memory partition 102A, 102B, 102C, or 102D of memory circuit 200.

[0083] In some embodiments, each of the repeater circuit groups 230a, 230b, 230c or 230d is configured to repeat or create a local variant of the global predecoder signal group PREDEC1_GLOBAL or the global predecoder signal group PREDEC2_GLOBAL (e.g., the local predecoder signal group PREDEC1_LOCAL or the local predecoder signal group PREDEC2_LOCAL).

[0084] In some embodiments, by repeating or creating local variations of the global predecoder signal group PREDEC1_GLOBAL or the global predecoder signal group PREDEC2_GLOBAL, a corresponding local predecoder signal group PREDEC1_LOCAL or a local predecoder signal group PREDEC2_LOCAL is generated. This increases the drive strength of the local predecoder signal group PREDEC1_LOCAL or the local predecoder signal group PREDEC2_LOCAL from each of the repeater circuit groups 230a, 230b, 230c or 230d compared to other methods, resulting in a timing improvement in at least the address setting time of the memory circuit 200.

[0085] The WL driver circuit 212a in memory partition 102A includes a post-word-line decoder circuit 246a. The WL driver circuit 212b in memory partition 102A includes a post-word-line decoder circuit group 246b. The WL driver circuit 212a in memory partition 102B includes a post-word-line decoder circuit group 244a. The WL driver circuit 212b in memory partition 102B includes a post-word-line decoder circuit group 244b. The WL driver circuit 212a in memory partition 102C includes a post-word-line decoder circuit group 242a. The WL driver circuit 212b in memory partition 102C includes a post-word-line decoder circuit group 242b. The WL driver circuit 212a in memory partition 102D includes a post-word-line decoder circuit group 240a. The WL driver circuit 212b in memory partition 102D includes a post-word-line decoder circuit group 240b.

[0086] The word line decoder circuit group 240a or 240b is configured to receive one of the local pre-decoder signal groups PREDEC1_LOCAL, PREDEC2_LOCAL, and the corresponding clock signal group ICKD_TOP[0:3] or ICKD_BOT[0:3]. The word line decoder circuit group 240a or 240b is configured to generate the word line signal group WL' in response to one of the local pre-decoder signal groups PREDEC1_LOCAL, PREDEC2_LOCAL, and the corresponding clock signal group ICKD_TOP[0:3] or ICKD_BOT[0:3].

[0087] Word line decoder circuit groups 240a and 240b are configured to output word line signal groups WL' on the corresponding word line WL. Word line decoder circuit groups 240a and 240b are further coupled to corresponding memory cell arrays 210a or 210b via word lines WL. At least one of the memory cell arrays 210a or 210b is configured to store a corresponding first set of data or a second set of data, at least in response to the word line signal group WL'.

[0088] The word line decoder circuit group 242a or 242b is configured to receive one of the local pre-decoder signal groups PREDEC1_LOCAL, PREDEC2_LOCAL, and the corresponding clock signal group ICKD_TOP[0:3] or ICKD_BOT[0:3]. The word line decoder circuit group 242a or 242b is configured to generate the word line signal group WL' in response to one of the local pre-decoder signal groups PREDEC1_LOCAL, PREDEC2_LOCAL, and the corresponding clock signal group ICKD_TOP[0:3] or ICKD_BOT[0:3].

[0089] Post-word-line decoder circuit groups 242a and 242b are configured to output word-line signal groups WL' on the corresponding word lines WL. Post-word-line decoder circuit groups 242a and 242b are further coupled to corresponding memory cell arrays 210a or 210b via word lines WL. At least one of the memory cell arrays 210a or 210b is configured to store a corresponding first set of data or a second set of data, at least in response to the word-line signal group WL'.

[0090] The word line decoder circuit group 244a or 244b is configured to receive one of the local pre-decoder signal groups PREDEC1_LOCAL, PREDEC2_LOCAL, and the corresponding clock signal group ICKD_TOP[0:3] or ICKD_BOT[0:3]. The word line decoder circuit group 244a or 244b is configured to generate a word line signal group WL' in response to one of the local pre-decoder signal groups PREDEC1_LOCAL, PREDEC2_LOCAL, and the corresponding clock signal group ICKD_TOP[0:3] or ICKD_BOT[0:3].

[0091] Word line decoder circuit groups 244a and 244b are configured to output word line signal groups WL' on the corresponding word line WL. Word line decoder circuit groups 244a and 244b are further coupled to corresponding memory cell arrays 210a or 210b via word lines WL. At least one of the memory cell arrays 210a or 210b is configured to store a corresponding first set of data or a second set of data, at least in response to the word line signal group WL'.

[0092] The word line decoder circuit group 246a or 246b is configured to receive one of the local pre-decoder signal groups PREDEC1_LOCAL, PREDEC2_LOCAL, and the corresponding clock signal group ICKD_TOP[0:3] or ICKD_BOT[0:3]. The word line decoder circuit group 246a or 246b is configured to generate a word line signal group WL' in response to one of the local pre-decoder signal groups PREDEC1_LOCAL, PREDEC2_LOCAL, and the corresponding clock signal group ICKD_TOP[0:3] or ICKD_BOT[0:3].

[0093] Word line decoder circuit groups 246a and 246b are configured to output word line signal groups WL' on the corresponding word line WL. Word line decoder circuit groups 246a and 246b are further coupled to the corresponding memory cell arrays 210a or 210b via the word line WL. At least one of the memory cell arrays 210a or 210b is configured to store a corresponding first set of data or a second set of data, at least in response to the word line signal group WL'.

[0094] In some embodiments, for ease of illustration, clock pre-decoder circuit group 220, repeater circuit group 230, word-line post-decoder circuit groups 240, 242, 244 and 246, wires 260, 262 and 264, and wire groups 250 and 252 are shown configured for the left-hand portion of memory circuit 200. However, in some embodiments, memory circuit 200 is configured such that circuitry similar to the corresponding clock pre-decoder circuit group 220, repeater circuit group 230, word-line post-decoder circuit groups 240, 242, 244 and 246, wires 260, 262 and 264, and wire groups 250 and 252 is included in the right-hand portion of memory circuit 200, which is not shown for ease of illustration, and therefore similar detailed descriptions are omitted.

[0095] In some embodiments, the memory circuit 200 is configured such that clock pre-decoder circuit group 220, repeater circuit group 230, word line post-decoder circuit groups 240, 242, 244 and 246, wires 260, 262 and 264 and wire groups 250 and 252 are configured for the left side portion of the memory circuit 200, and thus similar detailed descriptions are omitted.

[0096] In some embodiments, by configuring each of the repeater circuit groups 230a, 230b, 230c, or 230d in the corresponding local control circuit 214a, the word-line decoder circuit groups 240, 242, 244, and 246 are configured to receive local pre-decoder signals (e.g., local pre-decoder signal groups PREDEC1_LOCAL and PREDEC2_LOCAL) compared to other methods of receiving global pre-decoder signals. In some embodiments, by configuring the word-line decoder circuit groups 240, 242, 244, and 246 to receive local pre-decoder signals (e.g., local pre-decoder signal groups PREDEC1_LOCAL and PREDEC2_LOCAL), the drive strength of the local pre-decoder signal group PREDEC1_LOCAL or the local pre-decoder signal group PREDEC2_LOCAL from each of the repeater circuit groups 230a, 230b, 230c, or 230d is increased compared to other methods, resulting in a timing improvement in at least the address setting time of the memory circuit 200.

[0097] Other configurations of the memory circuitry 200 are within the scope of this disclosure.

[0098] Figure 3 This is a circuit diagram of a memory circuit 300 according to some embodiments.

[0099] Memory circuit 300 is Figure 1 Memory circuit 100 or Figures 2A-2B An embodiment of memory circuit 200 is shown, and therefore a similar detailed description is omitted. For example, memory circuit 300 is shown. Figure 3 The inverter groups 330 and 332 are Figures 2A-2B Non-limiting examples of embodiments of repeater groups 230a, 230b, 230c, or 230d are provided, and therefore similar detailed descriptions are omitted. In other words, memory circuitry 300 is shown in which... Figures 2A-2B Non-limiting examples of repeater groups 230a, 230b, 230c or 230d including inverter groups 330 and 332.

[0100] The memory circuit 300 includes a local control circuit 302, inverter groups 330 and 332, and wires 260, 262, 350, and 352. The local control circuit 302 includes inverter groups 330 and 332.

[0101] and Figures 2A-2B Compared to memory circuit 200, local control circuit 302 is an embodiment of local control circuit 214a, inverter groups 330 and 332 are embodiments of at least one of repeater groups 230a, 230b, 230c or 230d, wire 350 is an embodiment of wire 250, wire 352 is an embodiment of wire 252, and therefore similar detailed descriptions are omitted.

[0102] and Figures 2A-2B Compared to memory circuit 200, inverter groups 330 and 332 can be used as at least one of repeater circuit groups 230a, 230b, 230c or 230d, and therefore similar detailed descriptions are omitted.

[0103] Inverter group 330 is configured to receive global predecoder signal group PREDEC1_GLOBAL[0:7]. Inverter group 330 is configured to generate local predecoder signal group PREDEC1_LOCAL[0:7] in response to global predecoder signal group PREDEC1_GLOBAL[0:7]. In some embodiments, local predecoder signal group PREDEC1_LOCAL[0:7] is inverted from global predecoder signal group PREDEC1_GLOBAL[0:7]. Inverter group 330 is located between conductor 260 and conductor 350.

[0104] Inverter group 330 includes at least one of inverters 330a, 330b, ..., 330g or 330h. Each inverter 330a, 330b, ..., 330g or 330h in inverter group 330 is configured to receive a corresponding global predecoder signal of global predecoder signal group PREDEC1_GLOBAL[0:7] from wire 260.

[0105] Each inverter 330a, 330b, ..., 330g or 330h in inverter group 330 is configured to generate a corresponding local predecoder signal in local predecoder signal group PREDEC1_LOCAL[0:7] in response to the corresponding global predecoder signal in global predecoder signal group PREDEC1_GLOBAL[0:7]. In some embodiments, each local predecoder signal in local predecoder signal group PREDEC1_LOCAL[0:7] is inverted with the corresponding global predecoder signal in global predecoder signal group PREDEC1_GLOBAL[0:7].

[0106] Each inverter 330a, 330b, ..., 330g or 330h in inverter group 330 is configured to output the corresponding local pre-decoder signal in local pre-decoder signal group PREDEC1_LOCAL[0:7] on wire 350.

[0107] Inverter group 332 is configured to receive the global predecoder signal group PREDEC2_GLOBAL[0:7]. Inverter group 332 is configured to generate a local predecoder signal group PREDEC2_LOCAL[0:7] in response to the global predecoder signal group PREDEC2_GLOBAL[0:7]. In some embodiments, the local predecoder signal group PREDEC2_LOCAL[0:7] is inverted from the global predecoder signal group PREDEC2_GLOBAL[0:7]. Inverter group 332 is located between conductor 262 and conductor 352.

[0108] Inverter group 332 includes at least one of inverters 332a, 332b, ..., 332g or 332h. Each inverter 332a, 332b, ..., 332g or 332h in inverter group 332 is configured to receive a corresponding global predecoder signal from global predecoder signal group PREDEC2_GLOBAL[0:7] from wire 262.

[0109] Each inverter 332a, 332b, ..., 332g or 332h in inverter group 332 is configured to generate a corresponding local predecoder signal in local predecoder signal group PREDEC2_LOCAL[0:7] in response to the corresponding global predecoder signal in global predecoder signal group PREDEC2_GLOBAL[0:7]. In some embodiments, each local predecoder signal in local predecoder signal group PREDEC2_LOCAL[0:7] is inverted with the corresponding global predecoder signal in global predecoder signal group PREDEC2_GLOBAL[0:7].

[0110] Each inverter 332a, 332b, ..., 332g or 332h in inverter group 332 is configured to output the corresponding local pre-decoder signal in local pre-decoder signal group PREDEC2_LOCAL[0:7] on wire 352.

[0111] In some embodiments, inverter groups 330 and 332 are replaced by corresponding buffer circuit groups. In these embodiments, the local predecoder signal group PREDEC1_LOCAL[0:7] is not inverted with the global predecoder signal group PREDEC1_GLOBAL[0:7], and the local predecoder signal group PREDEC2_LOCAL[0:7] is not inverted with the global predecoder signal group PREDEC2_GLOBAL[0:7].

[0112] In some embodiments, memory circuitry 300 operates to achieve one or more of the benefits described herein, including the details discussed above with respect to memory circuitry 200.

[0113] Other configurations of the memory circuit 300 are within the scope of this disclosure.

[0114] Figure 4 This is a circuit diagram of a memory circuit 400 according to some embodiments.

[0115] Memory circuit 400 is Figure 3Variations of the memory circuit 300 are shown, and therefore similar detailed descriptions are omitted. For example, a non-limiting example of the memory circuit 300 is shown, wherein the WL driver circuit 404a includes four inverter groups (e.g., inverter groups 440, 442, 444, 446) and the WL driver circuit 404b includes four inverter groups (e.g., inverters 450, 452, 454, 456) in each corresponding path between the global predecoder line group and the local predecoder line group. In some embodiments, by means of four inverter groups (e.g., inverter groups 440, 442, 444, 446) included in the corresponding first path between the global predecoder line and the local predecoder line by WL driver circuit 404a, and by means of four inverter groups (e.g., inverter groups 450, 452, 454, 456) included in the corresponding second path between the global predecoder line and the local predecoder line by WL driver circuit 404b, compared with other methods, the drive strength of the local predecoder signal group PREDEC1_LOCAL or the local predecoder signal group PREDEC2_LOCAL from each of the inverter groups 442, 446, 452, and 456 is increased, resulting in a timing improvement of at least the address setting time of the memory circuit 400.

[0116] Memory circuit 400 is Figure 1 Memory circuit 100 or Figures 2A-2B An embodiment of the memory circuit 200 is described, and therefore a similar detailed description is omitted.

[0117] The memory circuit 400 includes a local control circuit 402, a WL driver circuit 404a, a WL driver circuit 404b, and wires 260, 262, 350a, 350b, 352a, 352b, 460, and 462.

[0118] In some embodiments, wires 350a and 350b are similar to Figure 3 Wires 350, 352a, and 352b are similar to Figure 3 The wire 352, and therefore a similar detailed description is omitted.

[0119] and Figures 2A-2B Compared to memory circuit 200, local control circuit 402 is an embodiment of local control circuit 214a, inverter groups 430 and 432 are embodiments of at least one of repeater groups 230a, 230b, 230c or 230d, WL driver circuit 404a is an embodiment of WL driver circuit 212a, WL driver circuit 404b is an embodiment of WL driver circuit 212b, wires 350a-350b are embodiments of wire 250, and wires 352a-352b are embodiments of wire 252, and therefore similar detailed descriptions are omitted.

[0120] The local control circuit group 402 includes inverter groups 430 and 432. Figures 2A-2B Compared to memory circuit 200, inverter groups 430 and 432 can be used as at least one of repeater circuit groups 230a, 230b, 230c or 230d, and therefore a similar detailed description is omitted.

[0121] Inverter groups 430 and 432 are Figure 3 Variations of the corresponding inverter groups 330 and 332 are described below, and therefore similar detailed descriptions are omitted. Figure 3 Compared to inverter group 330, inverter group 430 is configured to generate intermediate signals (e.g., local intermediate pre-decoder signal group PREDEC1_LOCAL_I[0:7]) and is not directly coupled to wires 350a-350b. Figure 3 Compared to inverter group 332, inverter group 432 is configured to generate intermediate signals (e.g., local intermediate pre-decoder signal group PREDEC2_LOCAL_I[0:7]) and is not directly coupled to wires 352a-352b.

[0122] Inverter group 430 is configured to receive global predecoder signal group PREDEC1_GLOBAL[0:7]. Inverter group 430 is configured to generate local intermediate predecoder signal group PREDEC1_LOCAL_I[0:7] in response to global predecoder signal group PREDEC1_GLOBAL[0:7]. In some embodiments, local intermediate predecoder signal group PREDEC1_LOCAL_I[0:7] is inverted from global predecoder signal group PREDEC1_GLOBAL[0:7]. Inverter group 430 is located between conductor 260 and conductor 460.

[0123] Inverter group 430 includes at least one of inverters 430a, 430b, ..., 430g or 430h. Each inverter 430a, 430b, ..., 430g or 430h in inverter group 430 is configured to receive a corresponding global predecoder signal of global predecoder signal group PREDEC1_GLOBAL[0:7] from wire 260.

[0124] Each inverter 430a, 430b, ..., 430g or 430h in inverter group 430 is configured to generate a corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC1_LOCAL_I[0:7] in response to the corresponding global predecoder signal in global predecoder signal group PREDEC1_GLOBAL_I[0:7]. In some embodiments, each local intermediate predecoder signal in local intermediate predecoder signal group PREDEC1_LOCAL_I[0:7] is inverted with the corresponding global predecoder signal in global predecoder signal group PREDEC1_GLOBAL[0].

[0125] Each inverter 430a, 430b, ..., 430g or 430h in inverter group 430 is configured to output the corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC1_LOCAL_I[0:7] via wire 460 to the corresponding inverter 440a, 440b, ..., 440g or 440h in inverter group 440 and the corresponding inverter 450a, 450b, ..., 450g or 450h in inverter group 450.

[0126] Inverter group 432 is configured to receive the global predecoder signal group PREDEC2_GLOBAL[0:7]. Inverter group 432 is configured to generate a local intermediate predecoder signal group PREDEC2_LOCAL_I[0:7] in response to the global predecoder signal group PREDEC2_GLOBAL[0:7]. In some embodiments, the local intermediate predecoder signal group PREDEC2_LOCAL_I[0:7] is inverted from the global predecoder signal group PREDEC2_GLOBAL[0:7]. Inverter group 432 is located between conductor 260 and conductor 462.

[0127] Inverter group 432 includes at least one of inverters 432a, 432b, ..., 432g or 432h. Each inverter 432a, 432b, ..., 432g or 432h in inverter group 432 is configured to receive the corresponding global predecoder signal of global predecoder signal group PREDEC2_GLOBAL[0:7] from wire 262.

[0128] Each inverter 432a, 432b, ..., 432g or 432h in inverter group 432 is configured to generate a corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC2_LOCAL_I[0:7] in response to a corresponding global predecoder signal in global predecoder signal group PREDEC2_GLOBAL_I[0:7]. In some embodiments, each local intermediate predecoder signal in local intermediate predecoder signal group PREDEC2_LOCAL_I[0:7] is inverted with the corresponding global predecoder signal in global predecoder signal group PREDEC2_GLOBAL[0:7].

[0129] Each inverter 432a, 432b, ..., 432g or 432h in inverter group 432 is configured to output the corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC2_LOCAL_I[0:7] via wire 462 to the corresponding inverter 444a, 444b, ..., 444g or 444h in inverter group 444 and the corresponding inverter 454a, 454b, ..., 454g or 454h in inverter group 454.

[0130] WL circuit group 404a includes inverter groups 440, 442, 444 and 446.

[0131] Inverter group 440 is configured to receive intermediate local pre-decoder signal group PREDEC1_LOCAL_I[0:7]. Inverter group 440 is configured to generate local intermediate pre-decoder signal group PREDEC1_LOCAL_IB[0:7] in response to intermediate local pre-decoder signal group PREDEC1_LOCAL_I[0:7]. In some embodiments, local intermediate pre-decoder signal group PREDEC1_LOCAL_IB[0:7] is inverted from intermediate local pre-decoder signal group PREDEC1_LOCAL_I[0:7]. Inverter group 440 is located between conductor 460 and inverter group 442.

[0132] Inverter group 440 includes at least one of inverters 440a, 440b, ..., 440g or 440h. Each inverter 440a, 440b, ..., 440g or 440h in inverter group 440 is configured to receive a corresponding intermediate local predecoder signal from intermediate local predecoder signal group PREDEC1_LOCAL_I[0:7] from wire 460.

[0133] Each inverter 440a, 440b, ..., 440g or 440h in inverter group 440 is configured to generate a corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC1_LOCAL_I[0:7] in response to a corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC1_LOCAL_I[0:7]. In some embodiments, each local intermediate predecoder signal in local intermediate predecoder signal group PREDEC1_LOCAL_I[0:7] is inverted with the corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC1_LOCAL_I[0:7].

[0134] Each inverter 440a, 440b, ..., 440g or 440h in inverter group 440 is configured to output the corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC1_LOCAL_IB[0:7] to the corresponding inverter 442a, 442b, ..., 442g or 442h in inverter group 442.

[0135] Inverter group 442 is configured to receive intermediate local pre-decoder signal group PREDEC1_LOCAL_IB[0:7]. Inverter group 442 is configured to generate local pre-decoder signal group PREDEC1_LOCAL_[0:7] in response to intermediate local pre-decoder signal group PREDEC1_LOCAL_IB[0:7]. In some embodiments, the local intermediate pre-decoder signal group PREDEC1_LOCAL_IB[0:7] is inverted with the local pre-decoder signal group PREDEC1_LOCAL[0:7]. Inverter group 442 is located between inverter group 440 and conductor 350a.

[0136] Inverter group 442 includes at least one of inverters 442a, 442b, ..., 442g or 442h. Each inverter 442a, 442b, ..., 442g or 442h in inverter group 442 is configured to receive a corresponding intermediate local predecoder signal from the intermediate local predecoder signal group PREDEC1_LOCAL_IB[0:7] from the corresponding inverter 440a, 440b, ..., 440g or 440h in inverter group 440.

[0137] Each inverter 442a, 442b, ..., 442g or 442h in inverter group 442 is configured to generate a corresponding local predecoder signal in local predecoder signal group PREDEC1_LOCAL_IB[0:7] in response to a corresponding intermediate local predecoder signal in intermediate local predecoder signal group PREDEC1_LOCAL_IB[0:7]. In some embodiments, each local intermediate predecoder signal in local intermediate predecoder signal group PREDEC1_LOCAL_IB[0:7] is inverted with the corresponding local predecoder signal in local predecoder signal group PREDEC1_LOCAL[0:7].

[0138] Each inverter 442a, 442b, ..., 442g or 442h in inverter group 442 is configured to output the corresponding local predecoder signal in local predecoder signal group PREDEC1_LOCAL[0:7] to wire 350a.

[0139] Inverter group 444 is configured to receive intermediate local pre-decoder signal group PREDEC2_LOCAL_I[0:7]. Inverter group 444 is configured to generate local intermediate pre-decoder signal group PREDEC2_LOCAL_IB[0:7] in response to intermediate local pre-decoder signal group PREDEC2_LOCAL_I[0:7]. In some embodiments, local intermediate pre-decoder signal group PREDEC2_LOCAL_IB[0:7] is inverted from intermediate local pre-decoder signal group PREDEC2_LOCAL_I[0:7]. Inverter group 444 is located between conductor 462 and inverter group 446.

[0140] Inverter group 444 includes at least one of inverters 444a, 444b, ..., 444g or 444h. Each inverter 444a, 444b, ..., 444g or 444h in inverter group 444 is configured to receive a corresponding intermediate local predecoder signal from intermediate local predecoder signal group PREDEC2_LOCAL_I[0:7] from wire 462.

[0141] Each inverter 444a, 444b, ..., 444g or 444h in inverter group 444 is configured to generate a corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC2_LOCAL_IB[0:7] in response to a corresponding intermediate local predecoder signal in intermediate local predecoder signal group PREDEC2_LOCAL_I[0:7]. In some embodiments, each local intermediate predecoder signal in local intermediate predecoder signal group PREDEC2_LOCAL_IB[0:7] is inverted with the corresponding intermediate local predecoder signal in intermediate local predecoder signal group PREDEC2_LOCAL_I[0:7].

[0142] Each inverter 444a, 444b, ..., 444g or 444h in inverter group 444 is configured to output the corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC2_LOCAL_IB[0:7] to the corresponding inverter 446a, 446b, ..., 446g or 446h in inverter group 446.

[0143] Inverter group 446 is configured to receive intermediate local pre-decoder signal group PREDEC2_LOCAL_IB[0:7]. Inverter group 446 is configured to generate local pre-decoder signal group PREDEC2_LOCAL_[0:7] in response to intermediate local pre-decoder signal group PREDEC2_LOCAL_IB[0:7]. In some embodiments, the local intermediate pre-decoder signal group PREDEC2_LOCAL_IB[0:7] is inverted with the local pre-decoder signal group PREDEC2_LOCAL[0:7]. Inverter group 446 is located between inverter group 444 and wire 352b.

[0144] Inverter group 446 includes at least one of inverters 446a, 446b, ..., 446g or 446h. Each inverter 446a, 446b, ..., 446g or 446h in inverter group 446 is configured to receive a corresponding intermediate local predecoder signal from the intermediate local predecoder signal group PREDEC2_LOCAL_IB[0:7] from the corresponding inverter 444a, 444b, ..., 444g or 444h in inverter group 444.

[0145] Each inverter 446a, 446b, ..., 446g or 446h in inverter group 446 is configured to generate a corresponding local predecoder signal in local predecoder signal PREDEC2_LOCAL_IB[0:7] in response to a corresponding intermediate local predecoder signal in intermediate local predecoder signal group PREDEC2_LOCAL_IB[0:7]. In some embodiments, each local intermediate predecoder signal in local intermediate predecoder signal group PREDEC2_LOCAL_IB[0:7] is inverted with the corresponding local predecoder signal in local predecoder signal group PREDEC2_LOCAL[0:7].

[0146] Each inverter 446a, 446b, ..., 446g or 446h in inverter group 446 is configured to output the corresponding local predecoder signal in local predecoder signal group PREDEC2_LOCAL[0:7] to wire 352b.

[0147] Inverter group 450 is configured to receive intermediate local pre-decoder signal group PREDEC1_LOCAL_I[0:7]. Inverter group 450 is configured to generate local intermediate pre-decoder signal group PREDEC1_LOCAL_IB[0:7] in response to intermediate local pre-decoder signal group PREDEC1_LOCAL_I[0:7]. In some embodiments, local intermediate pre-decoder signal group PREDEC1_LOCAL_IB[0:7] is inverted from intermediate local pre-decoder signal group PREDEC1_LOCAL_I[0:7]. Inverter group 450 is located between conductor 460 and inverter group 452.

[0148] WL circuit group 404b includes inverter groups 450, 452, 454 and 456.

[0149] Inverter group 450 includes at least one of inverters 450a, 450b, ..., 450g or 450h. Each inverter 450a, 450b, ..., 450g or 450h in inverter group 450 is configured to receive a corresponding intermediate local predecoder signal from intermediate local predecoder signal group PREDEC1_LOCAL_I[0:7] from wire 460.

[0150] Each inverter 450a, 450b, ..., 450g or 450h in inverter group 450 is configured to generate a corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC1_LOCAL_I[0:7] in response to a corresponding intermediate local predecoder signal in intermediate local predecoder signal group PREDEC1_LOCAL_I[0:7]. In some embodiments, each local intermediate predecoder signal in local intermediate predecoder signal group PREDEC1_LOCAL_I[0:7] is inverted with the corresponding intermediate local predecoder signal in intermediate local predecoder signal group PREDEC1_LOCAL_I[0:7].

[0151] Each inverter 450a, 450b, ..., 450g or 450h in inverter group 450 is configured to output the corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC1_LOCAL_IB[0:7] to the corresponding inverter 452a, 452b, ..., 452g or 452h in inverter group 452.

[0152] Inverter group 452 is configured to receive intermediate local pre-decoder signal group PREDEC1_LOCAL_IB[0:7]. Inverter group 452 is configured to generate local pre-decoder signal group PREDEC1_LOCAL_IB[0:7] in response to the intermediate local pre-decoder signal group PREDEC1_LOCAL_IB[0:7]. In some embodiments, the local intermediate pre-decoder signal group PREDEC1_LOCAL_IB[0:7] is inverted with the local pre-decoder signal group PREDEC1_LOCAL[0:7]. Inverter group 452 is located between inverter group 450 and conductor 350b.

[0153] Inverter group 452 includes at least one of inverters 452a, 452b, ..., 452g or 452h. Each inverter 452a, 452b, ..., 452g or 452h in inverter group 452 is configured to receive a corresponding intermediate local predecoder signal from the intermediate local predecoder signal group PREDEC1_LOCAL_IB[0:7] from the corresponding inverter 450a, 450b, ..., 450g or 450h in inverter group 450.

[0154] Each inverter 452a, 452b, ..., 452g or 452h in inverter group 452 is configured to generate a corresponding local predecoder signal in local predecoder signal group PREDEC1_LOCAL_IB[0:7] in response to a corresponding intermediate local predecoder signal in intermediate local predecoder signal group PREDEC1_LOCAL_IB[0:7]. In some embodiments, each local intermediate predecoder signal in local intermediate predecoder signal group PREDEC1_LOCAL_IB[0:7] is inverted with the corresponding local predecoder signal in local predecoder signal group PREDEC1_LOCAL[0:7].

[0155] Each inverter 452a, 452b, ..., 452g or 452h in inverter group 452 is configured to output the corresponding local predecoder signal in local predecoder signal group PREDEC1_LOCAL[0:7] to wire 350b.

[0156] Inverter group 454 is configured to receive intermediate local pre-decoder signal group PREDEC2_LOCAL_I[0:7]. Inverter group 454 is configured to generate local intermediate pre-decoder signal group PREDEC2_LOCAL_IB[0:7] in response to intermediate local pre-decoder signal group PREDEC2_LOCAL_I[0:7]. In some embodiments, local intermediate pre-decoder signal group PREDEC2_LOCAL_IB[0:7] is inverted from intermediate local pre-decoder signal group PREDEC2_LOCAL_I[0:7]. Inverter group 454 is located between conductor 462 and inverter group 456.

[0157] Inverter group 454 includes at least one of inverters 454a, 454b, ..., 454g or 454h. Each inverter 454a, 454b, ..., 454g or 454h in inverter group 454 is configured to receive a corresponding intermediate local predecoder signal from intermediate local predecoder signal group PREDEC2_LOCAL_I[0:7] from wire 462.

[0158] Each inverter 454a, 454b, ..., 454g or 454h in inverter group 454 is configured to generate a corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC2_LOCAL_I[0:7] in response to a corresponding intermediate local predecoder signal in intermediate local predecoder signal group PREDEC2_LOCAL_I[0:7]. In some embodiments, each local intermediate predecoder signal in local intermediate predecoder signal group PREDEC2_LOCAL_I[0:7] is inverted with the corresponding intermediate local predecoder signal in intermediate local predecoder signal group PREDEC2_LOCAL_I[0:7].

[0159] Each inverter 454a, 454b, ..., 454g or 454h in inverter group 454 is configured to output the corresponding local intermediate predecoder signal in local intermediate predecoder signal group PREDEC2_LOCAL_IB[0:7] to the corresponding inverter 456a, 456b, ..., 456g or 456h in inverter group 456.

[0160] Inverter group 456 is configured to receive intermediate local pre-decoder signal group PREDEC2_LOCAL_IB[0:7]. Inverter group 456 is configured to generate local pre-decoder signal group PREDEC2_LOCAL_IB[0:7] in response to the intermediate local pre-decoder signal group PREDEC2_LOCAL_IB[0:7]. In some embodiments, the local intermediate pre-decoder signal group PREDEC2_LOCAL_IB[0:7] is inverted from the local pre-decoder signal group PREDEC2_LOCAL[0:7]. Inverter group 456 is located between inverter group 454 and wire 352b.

[0161] Inverter group 456 includes at least one of inverters 456a, 456b, ..., 456g or 456h. Each inverter 456a, 456b, ..., 456g or 456h in inverter group 456 is configured to receive a corresponding intermediate local predecoder signal from the intermediate local predecoder signal group PREDEC2_LOCAL_IB[0:7] from the corresponding inverter 454a, 454b, ..., 454g or 454h of inverter group 454.

[0162] Each inverter 456a, 456b, ..., 456g or 456h in inverter group 456 is configured to generate a corresponding local predecoder signal in local predecoder signal group PREDEC2_LOCAL_IB[0:7] in response to a corresponding intermediate local predecoder signal in intermediate local predecoder signal group PREDEC2_LOCAL_IB[0:7]. In some embodiments, each local intermediate predecoder signal in local intermediate predecoder signal group PREDEC2_LOCAL_IB[0:7] is inverted with the corresponding local predecoder signal in local predecoder signal group PREDEC2_LOCAL[0:7].

[0163] Each inverter 456a, 456b, ..., 456g or 456h in inverter group 456 is configured to output the corresponding local predecoder signal in local predecoder signal group PREDEC2_LOCAL[0:7] to wire 352b.

[0164] In some embodiments, other numbers of inverter groups for at least one of inverter groups 430, 432, 440, 442, 444, 446, 450, 452, 454, or 456 are within the scope of this disclosure. In some embodiments, other numbers of inverters within at least one or more of inverter groups 430, 432, 440, 442, 444, 446, 450, 452, 454, or 456 are within the scope of this disclosure.

[0165] In some embodiments, inverter groups 430, 432, 440, 442, 444, 446, 450, 452, 454, or 456 are replaced by corresponding buffer circuit groups. In these embodiments, the local predecoder signal group PREDEC1_LOCAL[0:7] is not inverted with the global predecoder signal group PREDEC1_GLOBAL[0:7], and the local predecoder signal group PREDEC2_LOCAL[0:7] is not inverted with the global predecoder signal group PREDEC2_GLOBAL[0:7].

[0166] In some embodiments, by including two additional inverter groups (e.g., inverter groups 440 and 442) in the path between conductor 260 (e.g., global predecoder line) and conductor 350a (e.g., local predecoder line) by WL driver circuit 404a, and by including two additional inverter groups (e.g., inverter groups 450 and 452) in the path between conductor 260 (e.g., global predecoder line) and conductor 350b (e.g., local predecoder line), the drive strength of the local predecoder signal group PREDEC1_LOCAL from each of inverter group 442 is increased compared to other methods, resulting in a timing improvement of at least the address setting time of memory circuit 400.

[0167] In some embodiments, by including two additional inverter groups (e.g., inverter groups 444 and 446) in the path between wire 260 (e.g., global predecoder line) and wire 352a (e.g., local predecoder line) by WL driver circuit 404a, and by including two additional inverter groups (e.g., inverter groups 454 and 456) in the path between wire 262 (e.g., global predecoder line) and wire 352b (e.g., local predecoder line), by WL driver circuit 404b, the drive strength of the local predecoder signal group PREDEC2_LOCAL from each of inverter group 456 is increased compared to other methods, resulting in a timing improvement of at least the address setting time of memory circuit 400.

[0168] Other configurations of the memory circuit 400 are within the scope of this disclosure.

[0169] Figure 5 This is a circuit diagram of a memory circuit 500 according to some embodiments.

[0170] Memory circuit 500 is Figure 4 Variations of the memory circuit 400 are shown, and therefore similar detailed descriptions are omitted. For example, a non-limiting example of the memory circuit 400 is shown, wherein the local control circuit 502 does not include repeater circuit groups or inverter groups between each corresponding path between the global predecoder line and the local predecoder line, but the WL driver circuit 504a includes two inverter groups (e.g., inverter groups 540 and 542), and the WL driver circuit 504b includes two inverter groups (e.g., inverter groups 550 and 552) located within each corresponding path between the global predecoder line and the local predecoder line.

[0171] In some embodiments, by means of two inverter groups (e.g., inverter groups 540 and 550) included in the memory circuit 500 within a corresponding first path between the global predecoder line and the local predecoder line, and by means of two inverter groups (e.g., inverter groups 542 and 552) included in the memory circuit 500 within a corresponding second path between the global predecoder line and the local predecoder line, compared to other methods, the drive strength of the local predecoder signal group PREDEC1_LOCAL or the local predecoder signal group PREDEC2_LOCAL from each of the inverter groups 540, 542, 550 and 552 is increased, resulting in a timing improvement in at least the address setting time of the memory circuit 500.

[0172] Memory circuit 500 is Figure 1 Memory circuit 100 or Figures 2A-2B An embodiment of the memory circuit 200 is described, and therefore a similar detailed description is omitted.

[0173] The memory circuit 500 includes a local control circuit 502, a WL driver circuit 504a, a WL driver circuit 504b, and wires 260, 262, 350, and 352.

[0174] and Figure 4 Compared to the memory circuit 400, the local control circuit 502 replaces... Figure 4 The local control circuit 402 and the WL driver circuit 504a replace the local control circuit 402. Figure 4 The WL driver circuit 404a and WL driver circuit 504b replace Figure 4 The WL driver circuit 404b, wire 350 is replaced Figure 4 Wires 350a and 350b, wire 352 replaced Figure 4 The wires 352a and 352b are used, and therefore similar detailed descriptions are omitted.

[0175] WL circuit group 504a includes inverter groups 540 and 542.

[0176] Inverter group 540 is configured to receive global predecoder signal group PREDEC1_GLOBAL[0:7]. Inverter group 540 is configured to generate local predecoder signal group PREDEC1_LOCAL[0:7] in response to global predecoder signal group PREDEC1_GLOBAL[0:7]. In some embodiments, local predecoder signal group PREDEC1_LOCAL[0:7] is inverted from global predecoder signal group PREDEC1_GLOBAL[0:7]. Inverter group 540 is located between conductor 260 and conductor 350.

[0177] Inverter group 540 includes at least one of inverters 540a, 540b, ..., 540g or 540h. Each inverter 540a, 540b, ..., 540g or 540h in inverter group 540 is configured to receive a corresponding global predecoder signal from global predecoder signal group PREDEC1_GLOBAL[0:7] from wire 260.

[0178] Each inverter 540a, 540b, ..., 540g or 540h in inverter group 540 is configured to generate a corresponding local predecoder signal in local predecoder signal group PREDEC1_GLOBAL[0:7] in response to a corresponding global predecoder signal in global predecoder signal group PREDEC1_GLOBAL[0:7]. In some embodiments, each local predecoder signal in local predecoder signal group PREDEC1_GLOBAL[0:7] is inverted with the corresponding global predecoder signal in global predecoder signal group PREDEC1_GLOBAL[0:7].

[0179] Each inverter 540a, 540b, ..., 540g or 540h in inverter group 540 is configured to output the corresponding local predecoder signal in local predecoder signal group PREDEC1_LOCAL[0:7] on wire 350.

[0180] Inverter group 542 is configured to receive global predecoder signal group PREDEC2_GLOBAL[0:7]. Inverter group 542 is configured to generate local predecoder signal group PREDEC2_LOCAL[0:7] in response to global predecoder signal group PREDEC2_GLOBAL[0:7]. In some embodiments, local predecoder signal group PREDEC2_LOCAL[0:7] is inverted from global predecoder signal group PREDEC2_GLOBAL[0:7]. Inverter group 542 is located between conductor 262 and conductor 352.

[0181] Inverter group 542 includes at least one of inverters 542a, 542b, ..., 542g or 542h. Each inverter 542a, 542b, ..., 542g or 542h in inverter group 542 is configured to receive the corresponding global predecoder signal of global predecoder signal group PREDEC2_GLOBAL[0:7] from wire 262.

[0182] Each inverter 542a, 542b, ..., 542g or 542h in inverter group 542 is configured to generate a corresponding local predecoder signal in local predecoder signal group PREDEC2_LOCAL[0:7] in response to the corresponding global predecoder signal in global predecoder signal group PREDEC2_GLOBAL[0:7]. In some embodiments, each local predecoder signal in local predecoder signal group PREDEC2_LOCAL[0:7] is inverted with the corresponding global predecoder signal in global predecoder signal group PREDEC2_GLOBAL[0:7].

[0183] Each inverter 542a, 542b, ..., 542g or 542h in inverter group 542 is configured to output the corresponding local predecoder signal in local predecoder signal group PREDEC2_LOCAL[0:7] on wire 352.

[0184] WL circuit group 504b includes inverter groups 550 and 552.

[0185] Inverter group 550 is configured to receive global predecoder signal group PREDEC1_GLOBAL[0:7]. Inverter group 550 is configured to generate local predecoder signal group PREDEC1_LOCAL[0:7] in response to global predecoder signal group PREDEC1_GLOBAL[0:7]. In some embodiments, local predecoder signal group PREDEC1_LOCAL[0:7] is inverted from global predecoder signal group PREDEC1_GLOBAL[0:7]. Inverter group 550 is located between conductor 260 and conductor 350.

[0186] Inverter group 550 includes at least one of inverters 550a, 550b, ..., 550g or 550h. Each inverter 550a, 550b, ..., 550g or 550h in inverter group 550 is configured to receive a corresponding global predecoder signal from global predecoder signal group PREDEC1_GLOBAL[0:7] from wire 260.

[0187] Each inverter 550a, 550b, ..., 550g or 550h in inverter group 550 is configured to generate a corresponding local predecoder signal in local predecoder signal group PREDEC1_GLOBAL[0:7] in response to a corresponding global predecoder signal in global predecoder signal group PREDEC1_GLOBAL[0:7]. In some embodiments, each local predecoder signal in local predecoder signal group PREDEC1_GLOBAL[0:7] is inverted with its corresponding global predecoder signal in global predecoder signal group PREDEC1_GLOBAL[0:7].

[0188] Each inverter 550a, 550b, ..., 550g or 550h in inverter group 550 is configured to output the corresponding local predecoder signal in local predecoder signal group PREDEC1_LOCAL[0:7] on wire 350.

[0189] Inverter group 552 is configured to receive the global predecoder signal group PREDEC2_GLOBAL[0:7]. Inverter group 552 is configured to generate a local predecoder signal group PREDEC2_LOCAL[0:7] in response to the global predecoder signal group PREDEC2_GLOBAL[0:7]. In some embodiments, the local predecoder signal group PREDEC2_LOCAL[0:7] is inverted from the global predecoder signal group PREDEC2_GLOBAL[0:7]. Inverter group 552 is located between conductor 262 and conductor 352.

[0190] Inverter group 552 includes at least one of inverters 552a, 552b, ..., 552g or 552h. Each inverter 552a, 552b, ..., 552g or 552h in inverter group 552 is configured to receive a corresponding global predecoder signal from global predecoder signal group PREDEC2_GLOBAL[0:7] from wire 262.

[0191] Each inverter 552a, 552b, ..., 552g or 552h in inverter group 552 is configured to generate a corresponding local predecoder signal in local predecoder signal group PREDEC2_LOCAL[0:7] in response to a corresponding global predecoder signal in global predecoder signal group PREDEC2_GLOBAL[0:7]. In some embodiments, each local predecoder signal in local predecoder signal group PREDEC2_LOCAL[0:7] is inverted with the corresponding global predecoder signal in global predecoder signal group PREDEC2_GLOBAL[0:7].

[0192] Each inverter 552a, 552b, ..., 552g or 552h in inverter group 552 is configured to output the corresponding local predecoder signal in local predecoder signal group PREDEC2_LOCAL[0:7] on wire 352.

[0193] In some embodiments, the wire 350 is made of, for example Figure 4 The wires 350a and 350b shown are replaced, and wire 352 is replaced by, as shown Figure 4 The wires 352a and 352b shown are substituted, and therefore similar detailed descriptions are omitted.

[0194] In some embodiments, other numbers of inverter groups for at least one of inverter groups 540, 542, 550, or 552 are within the scope of this disclosure. In some embodiments, other numbers of inverters within at least one or more of inverter groups 540, 542, 550, or 552 are within the scope of this disclosure.

[0195] In some embodiments, inverter groups 540, 542, 550, or 552 are replaced by corresponding buffer circuit groups. In these embodiments, the local predecoder signal group PREDEC1_LOCAL[0:7] is not inverted with the global predecoder signal group PREDEC1_GLOBAL[0:7], and the local predecoder signal group PREDEC2_LOCAL[0:7] is not inverted with the global predecoder signal group PREDEC2_GLOBAL[0:7].

[0196] In some embodiments, memory circuit 500 operates to achieve one or more of the benefits described herein, including the details discussed above with respect to at least one of memory circuits 300, 400, or 600.

[0197] Other configurations of the memory circuit 500 are within the scope of this disclosure.

[0198] Figure 6 This is a circuit diagram of a memory circuit 600 according to some embodiments.

[0199] Memory circuit 600 is Figures 2A-2B Memory circuit 200, Figure 3 Memory circuit 300, Figure 4 The memory circuit 400 and Figure 5 A variation of the memory circuit 500 is described, and therefore a similar detailed description is omitted.

[0200] For example, memory circuit 600 shows a non-limiting example in which the width W1 of wire 640 and the width W2 of wire 650 are shown.

[0201] In some embodiments, wire 640 may be used as at least one of wires 260 or 262, and wire 650 may be used as at least one of wires 250a and 252a, wires 250b and 252b, wires 250c and 252c, wires 250d and 252d, wire 350, wire 352, wires 350a and 350b, or wires 352a and 352b, and thus similar detailed descriptions are omitted.

[0202] Memory circuit 600 is Figures 2A-2B Memory circuit 200, Figure 3 Memory circuit 300, Figure 4 The memory circuit 400 and Figure 5 An embodiment of the memory circuit 500 is described, and therefore a similar detailed description is omitted.

[0203] The memory circuit 600 includes wires 640 and 650 and an inverter group 630.

[0204] In some embodiments, wire 640 is an embodiment of at least one of wires 260 or 262, wire 650 is an embodiment of at least one of wires 250a and 252a, wires 250b and 252b, wires 250c and 252c, wires 250d and 252d, wire 350, wire 352, wires 350a and 350b, or wires 352a and 352b, and inverter group 630 is an embodiment of at least one of inverter groups 330, 332, 430, 432, 440, 442, 444, 446, 450, 452, 454, 456, 540, 542, 550, or 552, and thus similar detailed descriptions are omitted.

[0205] Each of wires 640 and 650 extends in a second direction Y. Wires 640 and 650 are separated from each other in a first direction X. Wire 640 has a width W1 extending in the first direction. Wire 650 has a width W2 extending in the first direction. In some embodiments, width W1 is greater than width W2. In some embodiments, the ratio between width W2 and width W1 is between about 0.60 and 0.80. In some embodiments, if the ratio between width W2 and width W1 is less than the range of about 0.60 to 0.80, the resistance of wire 650 increases, thereby reducing the speed of address setting time of memory circuit 600 by other methods, and thus reducing the manufacturing yield of wire 650 compared to other methods.

[0206] In some embodiments, if the ratio between width W2 and width W1 is greater than the range of about 0.60 to 0.80, the resistance of wire 640 increases, thereby reducing the speed of address setting time of memory circuitry compared to other methods, and thus reducing the manufacturing yield of wire 650 compared to other methods.

[0207] Other widths W1 or W2, lengths, or shapes used for at least one of conductors 640 or 650 are within the scope of this disclosure.

[0208] The conductor 640 is on a first metal layer. The conductor 640 is on a second metal layer different from the first metal layer. In some embodiments, the first metal layer corresponds to a metal 4 (M4) layer memory circuit 600, and the second metal layer corresponds to a metal 2 (M2) layer memory circuit 600 located below the M4 metal layer. In these embodiments, the ratio between width W2 and width W1 is in the range of about 0.75 to about 0.8.

[0209] In some embodiments, the first metal layer corresponds to a metal 6 (M6) layer memory circuit 600, and the second metal layer corresponds to an M4 layer memory circuit 600 located below the M6 ​​metal layer. In these embodiments, the ratio between width W2 and width W1 is in the range of about 0.55 to about 0.65.

[0210] Other configurations of at least one of conductors 640 or 650, arrangements on other metal layers, or the number of conductors are within the scope of this disclosure.

[0211] In some embodiments, the resistance of wire 650 is reduced by the wire 640 having a width W1 and the wire 650 having a width W2, thereby resulting in a timing improvement in at least the address settling time of the memory circuit 600. In some embodiments, the capacitance of at least wire 640 or wire 650 is reduced by the wire 640 on the first metal layer and the wire 650 on the second metal layer, thereby resulting in a timing improvement in at least the address settling time of the memory circuit 600.

[0212] Other configurations of the memory circuitry 600 are within the scope of this disclosure.

[0213] Address latch and pre-decoder circuit

[0214] Figure 7 This is a circuit diagram of circuit 700 according to some embodiments.

[0215] Circuit 700 is Figures 2A-2B The embodiment of the address latch and pre-decoder circuit 204 is described, and therefore a similar detailed description is omitted.

[0216] Circuit 700 is configured to generate address signal group LADR[0:10], global predecoder signal group PREDEC1_GLOBAL and global predecoder signal group PREDEC2_GLOBAL in response to memory address signal ADR[10:0] and clock signal ICLK.

[0217] Circuit 700 is configured to latch the memory address signals ADR[10:0], thereby generating the address signal group LADR[0:10] and outputting the address signal group LADR[0:4].

[0218] Circuit 700 is configured to pre-decode a portion of the address signal group LADR[0:10] (e.g., the second group of address signals LADR[5:7]) to generate the global predecoder signal group PREDEC1_GLOBAL[0:7].

[0219] Circuit 700 is configured as another part of the pre-decode address signal group LADR[0:10] (e.g., the third group of address signals LADR[8:10]) to generate the global pre-decode signal group PREDEC2_GLOBAL[0:7].

[0220] Other number or bitline positions of bitlines used for at least one of the memory address signals ADR, address signal group LADR[0:10], first group address signals LADR[0:4], second group address signals LADR[5:7], third group address signals LADR[8:10], global predecoder signal group PREDEC1_GLOBAL[0:7] or global predecoder signal group PREDEC2_GLOBAL[0:7] are within the scope of this disclosure.

[0221] Other configurations of the memory circuit 700 are within the scope of this disclosure.

[0222] Figure 8 This is a circuit diagram of circuit 800 according to some embodiments.

[0223] Circuit 800 is Figures 2A-2B Address latch and pre-decoder circuit 204 or Figure 7 An embodiment of at least one of the circuits 700 is described, and therefore a similar detailed description is omitted.

[0224] Circuit 800 is configured to generate address signal group LADR[0:10], global predecoder signal group PREDEC1_GLOBAL and global predecoder signal group PREDEC2_GLOBAL in response to memory address signal ADR[10:0] and clock signal ICLK.

[0225] Circuit 800 includes address latch circuit 802, pre-decoder circuit 804 and pre-decoder circuit 802.

[0226] Address latch circuit 802 is coupled to pre-decoder circuit 804 and pre-decoder circuit 806. Address latch circuit 806 is configured to generate address signal group LADR[0:10] in response to memory address signal ADR[10:0] and clock signal ICLK.

[0227] Address latch circuit 802 is coupled to address signal group LADR[0:10] and configured to output address signal group LADR[0:10] to latch circuit 1002. Figure 10 (As shown in the diagram). The address latch circuit 802 is configured to output the second set of address signals LADR[5:7] to the pre-decoder circuit 804. The address latch circuit 802 is configured to output the third set of address signals LADR[8:10] to the pre-decoder circuit 806.

[0228] The predecoder circuit 804 is configured to receive a second set of local address signals (LADR[5:7]). The predecoder circuit 804 is configured to generate a global predecoder signal group PREDEC1_GLOBAL in response to at least the second set of local address signals (LADR[5:7]). In some embodiments, the predecoder circuit 804 is configured to generate the global predecoder signal group PREDEC1_GLOBAL in response to at least the second set of local address signals (LADR[5:7]) or an inverted second set of local address signals (LADRB[5:7]).

[0229] In some embodiments, the pre-decoder circuit 804 is a 3-input, 8-output pre-decoder circuit. Other numbers of inputs or outputs for the pre-decoder circuit 804 are within the scope of this disclosure.

[0230] The predecoder circuit 806 is configured to receive a third set of local address signals (LADR[8:10]). The predecoder circuit 806 is configured to generate a global predecoder signal group PREDEC2_GLOBAL in response to at least the third set of local address signals (LADR[8:10]). In some embodiments, the predecoder circuit 806 is configured to generate the global predecoder signal group PREDEC2_GLOBAL in response to at least the third set of local address signals (LADR[8:10]) or an inverted third set of local address signals (LADRB[8:10]).

[0231] In some embodiments, the pre-decoder circuit 806 is a 3-input, 8-output pre-decoder circuit. Other numbers of inputs or outputs for the pre-decoder circuit 806 are within the scope of this disclosure.

[0232] Other configurations of the memory circuit 800 are within the scope of this disclosure.

[0233] Pre-decoder circuit

[0234] Figure 9A This is a circuit diagram of a pre-decoder circuit 900A according to some embodiments.

[0235] The 900A pre-decoder circuit is Figure 8 An embodiment of the pre-decoder circuit 804 is described, and therefore a similar detailed description is omitted.

[0236] The pre-decoder circuit 900A includes an inverter group 901, which is coupled to AND logic gates 902, 904, 906, 908, 910, 912, 914, and 916. For ease of explanation, Figure 9A Inverter group 901 is not shown as coupled to AND logic gates 902, 904, 906, 908, 910, 912, 914 and 916.

[0237] Inverter group 901 is configured to receive a second set of address signals LADR[5:7]. Inverter group 901 is configured to generate an inverted second set of address signals LADRB[5:7] in response to the second set of address signals LADR[5:7]. In some embodiments, the inverted second set of address signals LADRB[5:7] is inverted compared to the second set of address signals LADR[5:7].

[0238] Inverter group 901 includes at least one of inverters 901a, 901b, or 901c. Each inverter 901a, 901b, or 901c in inverter group 901 is configured to receive a corresponding address signal in the second set of address signals LADR[5:7].

[0239] Each inverter 901a, 901b or 901c in inverter group 901 is configured to generate a corresponding inverted address signal in the second set of address signals LADRB[5:7] in response to a corresponding address signal in the second set of address signals LADR[5:7].

[0240] In some embodiments, each address signal in the second set of address signals LADR[5:7] is inverted with the corresponding inverted address signal in the inverted second set of address signals LADRB[5:7].

[0241] Each inverter 901a, 901b or 901c in inverter group 901 is configured to output the corresponding inverted address signal in the second set of address signals LADRB[5:7].

[0242] AND gate 902 is configured to generate the local predecoder signal PREDEC1[0] in response to the inverted address signal LADRB[5], the inverted address signal LADRB[6] and the inverted address signal LADRB[7] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0243] The first input terminal of AND logic gate 902 is coupled to the output terminal of inverter 901a, the second input terminal of AND logic gate 902 is coupled to the output terminal of inverter 901b, and the third input terminal of AND logic gate 902 is coupled to the output terminal of inverter 901c.

[0244] The first input terminal of the AND logic gate 902 is configured to receive the inverted address signal LADRB[5]. The second input terminal of the AND logic gate 902 is configured to receive the inverted address signal LADRB[6]. The third input terminal of the AND logic gate 902 is configured to receive the inverted address signal LADRB[7].

[0245] The output terminal of AND logic gate 902 is configured to output the local predecoder signal PREDEC1[0] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0246] The AND logic gate 904 is configured to generate the local predecoder signal PREDEC1[1] in response to the address signal LADR[5], the inverted address signal LADRB[6] and the inverted address signal LADRB[7] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0247] The first input terminal of the AND logic gate 904 is coupled to the input terminal of the inverter 901a, the second input terminal of the AND logic gate 904 is coupled to the output terminal of the inverter 901b, and the third input terminal of the AND logic gate 904 is coupled to the output terminal of the inverter 901c.

[0248] The first input terminal of the AND logic gate 904 is configured to receive the address signal LADR[5]. The second input terminal of the AND logic gate 904 is configured to receive the inverted address signal LADRB[6]. The third input terminal of the AND logic gate 904 is configured to receive the inverted address signal LADRB[7].

[0249] The output terminal of the AND logic gate 904 is configured to output the local predecoder signal PREDEC1[1] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0250] AND logic gate 906 is configured to generate the local predecoder signal PREDEC1[2] in response to the inverted address signal LADRB[5], address signal LADR[6] and the inverted address signal LADRB[7] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0251] The first input terminal of the AND logic gate 906 is coupled to the output terminal of the inverter 901a, the second input terminal of the AND logic gate 906 is coupled to the input terminal of the inverter 901b, and the third input terminal of the AND logic gate 906 is coupled to the output terminal of the inverter 901c.

[0252] The first input terminal of the AND logic gate 906 is configured to receive the inverted address signal LADRB[5]. The second input terminal of the AND logic gate 906 is configured to receive the address signal LADR[6]. The third input terminal of the AND logic gate 906 is configured to receive the inverted address signal LADRB[7].

[0253] The output terminal of the AND logic gate 906 is configured to output the local predecoder signal PREDEC1[2] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0254] The AND logic gate 908 is configured to generate the local predecoder signal PREDEC1[3] in response to the address signal LADR[5], the address signal LADR[6] and the inverted address signal LADRB[7] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0255] The first input terminal of the AND logic gate 908 is coupled to the input terminal of the inverter 901a, the second input terminal of the AND logic gate 908 is coupled to the input terminal of the inverter 901b, and the third input terminal of the AND logic gate 908 is coupled to the output terminal of the inverter 901c.

[0256] The first input terminal of the AND logic gate 908 is configured to receive the address signal LADR[5]. The second input terminal of the AND logic gate 908 is configured to receive the address signal LADR[6]. The third input terminal of the AND logic gate 908 is configured to receive the inverted address signal LADRB[7].

[0257] The output terminal of the AND logic gate 908 is configured to output the local predecoder signal PREDEC1[3] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0258] AND logic gate 910 is configured to generate the local predecoder signal PREDEC1[4] in response to the inverted address signal LADRB[5], the inverted address signal LADRB[6] and the address signal LADR[7] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0259] The first input terminal of the AND logic gate 910 is coupled to the output terminal of the inverter 901a, the second input terminal of the AND logic gate 910 is coupled to the output terminal of the inverter 901b, and the third input terminal of the AND logic gate 910 is coupled to the input terminal of the inverter 901c.

[0260] The first input terminal of the AND logic gate 910 is configured to receive the inverted address signal LADRB[5]. The second input terminal of the AND logic gate 910 is configured to receive the inverted address signal LADRB[6]. The third input terminal of the AND logic gate 910 is configured to receive the address signal LADR[7].

[0261] The output terminal of AND logic gate 910 is configured to output the local predecoder signal PREDEC1[4] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0262] AND logic gate 912 is configured to generate the local predecoder signal PREDEC1[5] in response to address signal LADR[5], inverted address signal LADRB[6] and address signal LADR[7], in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0263] The first input terminal of AND logic gate 912 is coupled to the input terminal of inverter 901a, the second input terminal of AND logic gate 912 is coupled to the output terminal of inverter 901b, and the third input terminal of AND logic gate 912 is coupled to the input terminal of inverter 901c.

[0264] The first input terminal of the AND logic gate 912 is configured to receive the address signal LADR[5]. The second input terminal of the AND logic gate 912 is configured to receive the inverted address signal LADRB[6]. The third input terminal of the AND logic gate 912 is configured to receive the address signal LADR[7].

[0265] The output terminal of AND logic gate 912 is configured to output the local predecoder signal PREDEC1[5] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0266] AND logic gate 914 is configured to generate the local predecoder signal PREDEC1[6] in response to the inverted address signals LADRB[5], LADR[6], and LADR[7] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0267] The first input terminal of the AND logic gate 914 is coupled to the output terminal of the inverter 901a, the second input terminal of the AND logic gate 914 is coupled to the input terminal of the inverter 901b, and the third input terminal of the AND logic gate 914 is coupled to the input terminal of the inverter 901c.

[0268] The first input terminal of the AND logic gate 914 is configured to receive the inverted address signal LADRB[5]. The second input terminal of the AND logic gate 914 is configured to receive the address signal LADR[6]. The third input terminal of the AND logic gate 914 is configured to receive the address signal LADR[7].

[0269] The output terminal of AND logic gate 914 is configured to output the local predecoder signal PREDEC1[6] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0270] AND logic gate 916 is configured to generate the local predecoder signal PREDEC1[7] in response to address signals LADRB[5], LADR[6] and LADR[7] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0271] The first input terminal of AND logic gate 916 is coupled to the input terminal of inverter 901a, the second input terminal of AND logic gate 916 is coupled to the input terminal of inverter 901b, and the third input terminal of AND logic gate 916 is coupled to the input terminal of inverter 901c.

[0272] The first input terminal of the AND logic gate 916 is configured to receive the address signal LADR[5]. The second input terminal of the AND logic gate 916 is configured to receive the address signal LADR[6]. The third input terminal of the AND logic gate 916 is configured to receive the address signal LADR[7].

[0273] The output terminal of AND logic gate 916 is configured to output the local predecoder signal PREDEC1[7] in the local predecoder signal group PREDEC1_LOCAL[0:7].

[0274] Other configurations, number of circuit elements, or types of circuit elements in the pre-decoder circuit 900A are within the scope of this disclosure.

[0275] Figure 9B This is a circuit diagram of a pre-decoder circuit 900B according to some embodiments.

[0276] The 900B pre-decoder circuit is Figure 8 An embodiment of the pre-decoder circuit 806 is described, and therefore a similar detailed description is omitted.

[0277] The pre-decoder circuit 900B includes an inverter group 921, which is coupled to AND logic gates 922, 924, 926, 928, 930, 932, 934, and 936. For ease of explanation, Figure 9B The inverter group 921 is not shown as coupled to AND logic gates 922, 924, 926, 928, 930, 932, 934 and 936.

[0278] The pre-decoder circuit 900B is a variant of the pre-decoder circuit 900A, and therefore similar detailed descriptions are omitted. Compared to the pre-decoder circuit 900A, inverter group 921 replaces inverter group 901, and AND logic gates 922, 924, 926, 928, 930, 932, 934, and 936 replace the corresponding AND logic gates 902, 904, 906, 908, 910, 912, 914, and 916, and therefore similar detailed descriptions are omitted. Compared to the pre-decoder circuit 900A, inverters 921a, 921b, or 921c replace inverters 901a, 901b, or 901c, and therefore similar detailed descriptions are omitted.

[0279] Inverter group 921 includes at least one of inverters 921a, 921b, or 921c. Each inverter 921a, 921b, or 921c in inverter group 921 is configured to receive a corresponding address signal in the second set of address signals LADR[8:10].

[0280] Each inverter 921a, 921b or 921c in inverter group 921 is configured to generate a corresponding inverted address signal in the second set of address signals LADRB[8:10] in response to a corresponding address signal in the second set of address signals LADR[8:10].

[0281] In some embodiments, each address signal in the second set of address signals LADR[8:10] is inverted with the corresponding inverted address signal in the inverted second set of address signals LADRB[8:10].

[0282] Each inverter 921a, 921b or 921c in inverter group 921 is configured to output the corresponding inverted address signal in the second set of address signals LADRB[8:10].

[0283] Figure 9B The description is similar to Figure 9A For the sake of brevity, Figure 9B Every detail will no longer be described.

[0284] For example, Figure 9A Inverters 901a, 901b, or 901c in inverter group 901 can replace the corresponding inverters 921a, 921b, or 921c in inverter group 921. AND logic gates 902, 904, 906, 908, 910, 912, 914, and 916 can replace the corresponding AND logic gates 922, 924, 926, 928, 930, 932, 934, and 936. Figure 9A The local predecoder signal group PREDEC1_LOCAL[0:7] can replace the corresponding local predecoder signal group PREDEC2_LOCAL[0:7], the local predecoder signal PREDEC1[0] can be replaced with the corresponding local predecoder signal PREDEC2[0], the local predecoder signal PREDEC1[1] can be replaced with the corresponding local predecoder signal PREDEC2[1], the local predecoder signal PREDEC1[2] can be replaced with the corresponding local predecoder signal PREDEC2[2], the local predecoder signal PREDEC1[3] can be replaced with the corresponding local predecoder signal PREDEC2[3], the local predecoder signal PREDEC1[4] can be replaced with the corresponding local predecoder signal PREDEC2[4], and the local predecoder signal PREDEC1[5] can be replaced with the corresponding local predecoder signal PREDEC2[4]. The local predecoder signal PREDEC2[5] can be replaced with the corresponding local predecoder signal PREDEC1[6], the local predecoder signal PREDEC1[7] can be replaced with the corresponding local predecoder signal PREDEC2[7], the address signal LADR[5], the address signal LADR[6], the address signal LADR[7], the inverted address signal LADRB[5], the inverted address signal LADRB[6] and the inverted address signal LADRB[7] can be replaced with the corresponding address signal LADR[8], the address signal LADR[9], the address signal LADR

[10] , the inverted address signal LADRB[8], the inverted address signal LADRB[9] and the inverted address signal LADRB

[10] , and thus similar detailed descriptions are omitted.

[0285] Other configurations, number of circuit elements, or types of circuit elements in the pre-decoder circuit 900B are within the scope of this disclosure.

[0286] Address latch circuit

[0287] Figure 10 This is a circuit diagram of an address latch circuit 1000 according to some embodiments.

[0288] Address latch circuit 1000 is Figure 8 An embodiment of the address latch circuit 802 is described, and therefore a similar detailed description is omitted.

[0289] Address latch circuit 1000 includes inverter 1002, inverter 1004, p-type metal-oxide-semiconductor (PMOS) transistors MP1, MP2, MP3 and MP4, and n-type metal-oxide-semiconductor (NMOS) transistors MN1, MN2, MN3 and MN4.

[0290] The input terminal of inverter 1002 is configured to receive a clock signal ICLK. Inverter 1002 is configured to generate an inverted clock signal ICLKB in response to the clock signal ICLK. In some embodiments, the inverted clock signal ICLKB is the inverse of the clock signal ICLK. The output terminal of inverter 1002 is used to output the inverted clock signal ICLKB.

[0291] Inverter 1002 is coupled to NMOS transistors MN2 and MN4, and PMOS transistors MP2 and MP4. For ease of explanation, Figure 10 Inverter 1002 is not shown as coupled to NMOS transistors MN2 and MN4 and PMOS transistors MP2 and MP4.

[0292] Although Figure 10 The address latch circuit 1000 is shown as generating address signals (e.g., local address signals LADR[0]) of the address signal group LADR[0:10] in response to the memory address signal ADR[0] of the memory address signal ADR[0:10]. However, the corresponding local address signals LADR[1], LADR[2], ..., LADR

[10] of the address signal group LADR[0:10] can be generated by a circuit similar to the address latch circuit 1000 in response to the corresponding memory address signals ADR[1], ADR[2], ..., ADR

[10] of the memory address signal ADR[0:10], and therefore a similar detailed description is omitted.

[0293] PMOS transistors MP1 and MP2 and NMOS transistors MN2 and MN1 are configured to generate an inverted address signal ADRB[0] in response to at least the address signal ADR[0], the clock signal ICLK, or the inverted clock signal ICLKB.

[0294] In some embodiments, if the inverted clock signal ICLKB is logic high and the clock signal ICLK is logic low, then PMOS transistors MP1 and MP2 and NMOS transistors MN2 and MN1 are configured as inverters.

[0295] The gate terminal of PMOS transistor MP1 is coupled to at least the gate terminal of NMOS transistor MN1. The gate terminals of PMOS transistor MP1 and NMOS transistor MN1 are configured to receive the address signal ADR[0]. PMOS transistor MP1 and NMOS transistor MN1 are turned on or off based on the address signal ADR[0]. The source terminal of PMOS transistor MP1 is coupled to the supply voltage VDD. The drain terminal of PMOS transistor MP1 is coupled to the source terminal of PMOS transistor MP2.

[0296] The gate terminal of PMOS transistor MP2 is coupled to the input terminal of inverter 1002 and is configured to receive clock signal ICLK. PMOS transistor MP2 is turned on or off based on clock signal ICLK.

[0297] The drain terminals of PMOS transistor MP2, NMOS transistor MN2, the input terminal of inverter 1004, PMOS transistor MP4, and NMOS transistor MN4 are each coupled to each other. In some embodiments, the drain terminals of PMOS transistor MP2 and NMOS transistor MN2 are configured to generate an inverted address signal ADRB[0]. In some embodiments, the drain terminals of PMOS transistor MP4 and NMOS transistor MN4 are configured to generate an inverted address signal ADRB[0]. In some embodiments, the address signal ADR[0] is inverted compared to the inverted address signal ADRB[0].

[0298] The gate terminal of NMOS transistor MN2 is coupled to the output terminal of inverter 1002 and is configured to receive an inverted clock signal ICLKB. NMOS transistor MN2 is turned on or off based on the inverted clock signal ICLKB. The source terminal of NMOS transistor MN2 and the drain terminal of NMOS transistor MN1 are coupled to each other.

[0299] The source terminal of the NMOS transistor MN1 is coupled to at least the reference power node VSS.

[0300] Inverter 1004 is configured to generate address signal LADR[0] in response to at least the inverted address signal ADRB[0]. In some embodiments, the inverted address signal ADRB[0] is the inverse of the address signal LADR[0]. The input terminal of inverter 1004 receives the inverted address signal ADRB[0]. The output terminal of inverter 1004 is used to output the address signal LADR[0].

[0301] In some embodiments, if the inverted clock signal ICLKB is logic low and the clock signal ICLK is logic high, then PMOS transistors MP3 and MP4 and NMOS transistors MN4 and MN3 are configured as inverters.

[0302] Each of the gate terminals of PMOS transistor MP3, NMOS transistor MN3, and inverter 1004 is coupled to each other. In some embodiments, the address signal LADR[0] is fed back to inverter 1004, thereby latching the address signal LADR[0]. In other words, the address signal LADR[0] is latched by inverter 1004, PMOS transistors MP3 and MP4, and NMOS transistors MN4 and MN3.

[0303] The gate terminals of PMOS transistor MP3 and NMOS transistor MN3 are configured to receive the address signal LADR[0]. PMOS transistor MP3 and NMOS transistor MN3 are turned on or off based on the address signal LADR[0]. The source terminal of PMOS transistor MP3 is coupled to the supply voltage VDD. The drain terminal of PMOS transistor MP3 is coupled to the source terminal of PMOS transistor MP4.

[0304] The gate terminal of the PMOS transistor MP4 is coupled to the output terminal of the inverter 1002 and is configured to receive an inverted clock signal ICLKB. The PMOS transistor MP4 is turned on or off based on the inverted clock signal ICLKB.

[0305] The gate terminal of NMOS transistor MN4 is coupled to the input terminal of inverter 1002 and is configured to receive clock signal ICLK. NMOS transistor MN4 is turned on or off based on clock signal ICLK. The source terminal of NMOS transistor MN4 and the drain terminal of NMOS transistor MN3 are coupled to each other.

[0306] The source terminal of NMOS transistor MN3 is coupled to at least the reference power node VSS.

[0307] The address latch circuit 1000 is configured to operate in standby mode and latch mode. In some embodiments, during standby mode, the clock signal CLK (e.g., ...) is used. Figures 2A-2B(As shown) is logic low, the clock signal ICLK is logic low, thus turning on the PMOS transistor MP2, and the inverted clock signal ICLKB is logic high, thus turning on the NMOS transistor MN2. In response to the PMOS transistor MP2 and the NMOS transistor MN2 being turned on, the PMOS transistors MP1 and MP2 and the NMOS transistors MN2 and MN1 are configured as inverters, the inverted address signal ADRB[0] is inverted with the address signal ADR[0], and the inverter 1004 is configured to invert the inverted address signal ADRB[0], thereby generating the address signal LADR[0].

[0308] In some embodiments, during latching mode, a read / write operation is performed on at least one of the memory cell arrays 210a or 210b, and inverter 1004, PMOS transistors MP3 and MP4, and NMOS transistors MN4 and MN3 are configured to latch the address signal LADR[0] or the inverted address signal ADRB[0]. For example, in these embodiments, the clock signal CLK (such as...) Figures 2A-2B (As shown) is logic high, the clock signal ICLK is logic high, thus turning off PMOS transistor MP2, and the inverted clock signal ICLKB is logic low, thus turning off NMOS transistor MN2. In response to PMOS transistor MP2 and NMOS transistor MN2 being turned off, the address signal ADR[0] is not set by PMOS transistor MP2 and NMOS transistor MN2. In these embodiments, the clock signal ICLK is logic high, thus turning on NMOS transistor MN4, and the inverted clock signal ICLKB is logic low, thus turning on PMOS transistor MP4. In response to PMOS transistor MP4 and NMOS transistor MN4 being turned on, PMOS transistors MP3 and MP4 and NMOS transistors MN4 and MN3 are configured as inverters and are configured to set or latch the inverted address signal ADRB[0] by the inverted address signal LADR[0].

[0309] Other configurations of the address latch circuit 1000, the number of circuit elements, or the type of circuit elements are within the scope of this disclosure.

[0310] Clock pre-decoder circuit

[0311] Figure 11 This is a circuit diagram of a clock pre-decoder circuit 1100 according to some embodiments.

[0312] Clock pre-decoder circuit 1100 is Figures 2A-2B Embodiments of at least one clock predecoder circuit 220a, 220b, 220c or 220d in the clock predecoder circuit group 220, and therefore similar detailed descriptions are omitted.

[0313] The clock pre-decoder circuit 1100 includes an inverter group 1121, an AND logic gate group 1102, an AND logic gate group 1104, an AND logic gate group 1106, an AND logic gate group 1108, and an AND logic gate group 1110. The inverter group 1101 is coupled to each of the AND logic gate groups 1102, 1104, 1106, 1108, and 1110. For ease of illustration, Figure 11 Inverter group 1121 is not shown as coupled to each of the AND logic gate groups 1102, 1104, 1106, 1108 and 1110.

[0314] Inverter group 1121 is configured to receive a first set of address signals LADR[0:4]. Inverter group 1121 is configured to generate an inverted first set of address signals LADRB[0:4] in response to the first set of address signals LADR[0:4]. In some embodiments, the inverted first set of address signals LADRB[0:4] is inverted from the first set of address signals LADR[0:4].

[0315] Inverter group 1121 includes at least one of inverters 1121a, 1121b, 1121c, 1121d, or 1121e. Each inverter 1121a, 1121b, 1121c, 1121d, or 1121e in inverter group 1121 is configured to receive a corresponding address signal in a first set of address signals LADR[0:4].

[0316] Each inverter 1121a, 1121b, 1121c, 1121d or 1121e in inverter group 1121 is configured to generate a corresponding inverted address signal in the first set of address signals LADRB[0:4] in response to a corresponding address signal in the first set of address signals LADR[0:4].

[0317] In some embodiments, each address signal in the first set of address signals LADR[0:4] is inverted with the corresponding inverted address signal in the inverted first set of address signals LADRB[0:4].

[0318] Each inverter 1121a, 1121b or 1121c in inverter group 1121 is configured to output the corresponding inverted address signal in the first set of address signals LADRB[0:4].

[0319] AND logic gate group 1102 is configured to generate a portion of signal group TOP[0:3] in response to at least a portion or an inverted portion of the first set of address signals LADRB[0:4] of the first set of address signals LADR[0:4]. AND logic gate group 1102 includes at least one of AND logic gates 1102a, 1102b, 1102c or 1102d.

[0320] In some embodiments, at least one of the signal groups TOP[0:3] comprises 4 bits, and these 4 bits are located at bit positions 0:3 in the corresponding signal group TOP[0:3]. Other numbers or bit positions used for at least one of the signal groups TOP[0:3] are within the scope of this disclosure.

[0321] AND logic gate 1102a is configured to generate signal TOP[0] in signal group TOP[0:3] in response to address signal LADR[4], inverted address signal LADRB[0] and inverted address signal LADRB[1].

[0322] The first input terminal of AND logic gate 1102a is coupled to the input terminal of inverter 1121a, the second input terminal of AND logic gate 1102a is coupled to the output terminal of inverter 1121b, and the third input terminal of AND logic gate 1102a is coupled to the output terminal of inverter 1121e.

[0323] The first input terminal of the AND logic gate 1102a is configured to receive the address signal LADR[4]. The second input terminal of the AND logic gate 1102a is configured to receive the inverted address signal LADRB[0]. The third input terminal of the AND logic gate 1102a is configured to receive the inverted address signal LADRB[1].

[0324] The output terminal of AND logic gate 1102a is configured as signal TOP[0] in the output signal group TOP[0:3].

[0325] The AND logic gate 1102b is configured to generate the signal TOP[1] in the signal group TOP[0:3] in response to the address signal LADR[4], the address signal LADR[0] and the inverted address signal LADRB[1].

[0326] The first input terminal of AND logic gate 1102b is coupled to the input terminal of inverter 1121a, the second input terminal of AND logic gate 1102b is coupled to the input terminal of inverter 1121b, and the third input terminal of AND logic gate 1102b is coupled to the output terminal of inverter 1121e.

[0327] The first input terminal of the AND logic gate 1102b is configured to receive the address signal LADR[4]. The second input terminal of the AND logic gate 1102b is configured to receive the address signal LADR[0]. The third input terminal of the AND logic gate 1102b is configured to receive the inverted address signal LADRB[1].

[0328] The output terminal of AND logic gate 1102b is configured as signal TOP[1] in the output signal group TOP[0:3].

[0329] The AND logic gate 1102c is configured to generate signal TOP[2] in the signal group TOP[0:3] in response to address signal LADR[4], inverted address signal LADRB[0] and address signal LADR[1].

[0330] The first input terminal of AND logic gate 1102c is coupled to the input terminal of inverter 1121a, the second input terminal of AND logic gate 1102c is coupled to the output terminal of inverter 1121b, and the third input terminal of AND logic gate 1102c is coupled to the input terminal of inverter 1121e.

[0331] The first input terminal of the AND logic gate 1102c is configured to receive the address signal LADR[4]. The second input terminal of the AND logic gate 1102c is configured to receive the inverted address signal LADRB[0]. The third input terminal of the AND logic gate 1102c is configured to receive the address signal LADR[1].

[0332] The output terminal of AND logic gate 1102c is configured as signal TOP[2] in the output signal group TOP[0:3].

[0333] AND logic gate 1102d is configured to generate signal TOP[3] in the signal group TOP[0:3] in response to address signals LADR[4], LADR[0] and LADR[1].

[0334] The first input terminal of AND logic gate 1102d is coupled to the input terminal of inverter 1121a, the second input terminal of AND logic gate 1102d is coupled to the input terminal of inverter 1121b, and the third input terminal of AND logic gate 1102d is coupled to the input terminal of inverter 1121e.

[0335] The first input terminal of the AND logic gate 1102d is configured to receive the address signal LADR[4]. The second input terminal of the AND logic gate 1102d is configured to receive the address signal LADR[0]. The third input terminal of the AND logic gate 1102d is configured to receive the address signal LADR[1].

[0336] The output terminal of AND logic gate 1102d is configured as signal TOP[3] in the output signal group TOP[0:3].

[0337] AND logic gate group 1104 is configured to generate signal group BOT[0:3] in response to at least a portion of the first group address signals LADR[0:4] or a portion of the inverted first group address signals LADRB[0:4]. AND logic gate group 1104 includes at least one of AND logic gates 1104a, 1104b, 1104c or 1104d.

[0338] In some embodiments, at least one of the signal groups BOT[0:3] comprises 4 bits, and these 4 bits are located at bit positions 0:3 in the corresponding signal group BOT[0:3]. Other numbers or bit positions used for at least one of the signal groups BOT[0:3] are within the scope of this disclosure.

[0339] AND logic gate 1104a is configured to generate signal BOT[0] in signal group BOT[0:3] in response to inverted address signal LADRB[4], inverted address signal LADRB[0] and inverted address signal LADRB[1].

[0340] The first input terminal of AND logic gate 1104a is coupled to the output terminal of inverter 1121a, the second input terminal of AND logic gate 1104a is coupled to the output terminal of inverter 1121b, and the third input terminal of AND logic gate 1104a is coupled to the output terminal of inverter 1121e.

[0341] The first input terminal of the AND logic gate 1104a is configured to receive the inverted address signal LADRB[4]. The second input terminal of the AND logic gate 1104a is configured to receive the inverted address signal LADRB[0]. The third input terminal of the AND logic gate 1104a is configured to receive the inverted address signal LADRB[1].

[0342] The output terminal of AND logic gate 1104a is configured as signal BOT[0] in the output signal group BOT[0:3].

[0343] The AND logic gate 1104b is configured to generate the signal BOT[1] in the signal group BOT[0:3] in response to the inverted address signal LADRB[4], the address signal LADR[0] and the inverted address signal LADRB[1].

[0344] The first input terminal of AND logic gate 1104b is coupled to the output terminal of inverter 1121a, the second input terminal of AND logic gate 1104b is coupled to the input terminal of inverter 1121b, and the third input terminal of AND logic gate 1104b is coupled to the output terminal of inverter 1121e.

[0345] The first input terminal of the AND logic gate 1104b is configured to receive the inverted address signal LADRB[4]. The second input terminal of the AND logic gate 1104b is configured to receive the address signal LADR[0]. The third input terminal of the AND logic gate 1104b is configured to receive the inverted address signal LADRB[1].

[0346] The output terminal of AND logic gate 1104b is configured as signal BOT[1] in the output signal group BOT[0:3].

[0347] The AND logic gate 1104c is configured to generate signal BOT[2] in the signal group BOT[0:3] in response to the inverted address signal LADRB[4], the inverted address signal LADRB[0], and the address signal LADR[1].

[0348] The first input terminal of AND logic gate 1104c is coupled to the output terminal of inverter 1121a, the second input terminal of AND logic gate 1104c is coupled to the output terminal of inverter 1121b, and the third input terminal of AND logic gate 1104c is coupled to the input terminal of inverter 1121e.

[0349] The first input terminal of the AND logic gate 1104c is configured to receive the inverted address signal LADRB[4]. The second input terminal of the AND logic gate 1104c is configured to receive the inverted address signal LADRB[0]. The third input terminal of the AND logic gate 1104c is configured to receive the address signal LADR[1].

[0350] The output terminal of the AND logic gate 1104c is configured as the signal BOT[2] in the output signal group BOT[0:3].

[0351] The AND logic gate 1104d is configured to generate the signal BOT[3] in the signal group BOT[0:3] in response to the inverted address signals LADRB[4], LADR[0] and LADR[1].

[0352] The first input terminal of AND logic gate 1104d is coupled to the output terminal of inverter 1121a, the second input terminal of AND logic gate 1104d is coupled to the input terminal of inverter 1121b, and the third input terminal of AND logic gate 1104d is coupled to the input terminal of inverter 1121e.

[0353] The first input terminal of the AND logic gate 1104d is configured to receive the inverted address signal LADRB[4]. The second input terminal of the AND logic gate 1104d is configured to receive the address signal LADR[0]. The third input terminal of the AND logic gate 1104d is configured to receive the address signal LADR[1].

[0354] The output terminal of AND logic gate 1104d is configured as signal BOT[3] in the output signal group BOT[0:3].

[0355] AND logic gate group 1106 is configured to generate a partial body selection signal BS[0:3] in response to at least a portion or an inverted portion of the first set of address signals LADRB[0:4]. AND logic gate group 1106 includes at least one of AND logic gates 1106a, 1106b, 1106c or 1106d.

[0356] In some embodiments, at least one of the body select signals BS[0:3] comprises four bits, and the four bits are located at bit positions 0:3 in the respective body select signal BS[0:3]. Other numbers or bit positions for at least one of the memory body select signal groups BS[0:3] are within the scope of this disclosure.

[0357] The AND logic gate 1106a is configured to generate the body selection signal BS[0] in response to the inverted address signal LADRB[2] and the inverted address signal LADRB[3].

[0358] The first input terminal of AND logic gate 1106a is coupled to the output terminal of inverter 1121c, and the second input terminal of AND logic gate 1106a is coupled to the output terminal of inverter 1121d.

[0359] The first input terminal of the AND logic gate 1106a is configured to receive the inverted address signal LADRB[2]. The second input terminal of the AND logic gate 1106a is configured to receive the inverted address signal LADRB[3].

[0360] The output terminal of AND logic gate 1106a is configured to output the body selection signal BS[0] in the body selection signal BS[0:3].

[0361] The AND logic gate 1106b is configured to generate the body selection signal BS[1] in response to the address signal LADR[2] and the inverted address signal LADRB[3] in the body selection signal BS[0:3].

[0362] The first input terminal of AND logic gate 1106b is coupled to the input terminal of inverter 1121c, and the second input terminal of AND logic gate 1106b is coupled to the output terminal of inverter 1121d.

[0363] The first input terminal of the AND logic gate 1106b is configured to receive the address signal LADR[2]. The second input terminal of the AND logic gate 1106b is configured to receive the inverted address signal LADRB[3].

[0364] The output terminal of the AND logic gate 1106b is configured to output the body selection signal BS[1] in the body selection signal BS[0:3].

[0365] The AND logic gate 1106c is configured to generate the body selection signal BS[2] in response to the inverted address signal LADRB[2] and the address signal LADR[3] in the body selection signal BS[0:3].

[0366] The first input terminal of AND logic gate 1106c is coupled to the output terminal of inverter 1121c, and the second input terminal of AND logic gate 1106c is coupled to the input terminal of inverter 1121d.

[0367] The first input terminal of the AND logic gate 1106c is configured to receive the inverted address signal LADRB[2]. The second input terminal of the AND logic gate 1106c is configured to receive the address signal LADR[3].

[0368] The output terminal of the AND logic gate 1106c is configured to output the body selection signal BS[2] in the body selection signal BS[0:3].

[0369] AND logic gate 1106d is configured to generate the body selection signal BS[3] in response to address signals LADR[2] and LADR[3].

[0370] The first input terminal of AND logic gate 1106d is coupled to the input terminal of inverter 1121c, and the second input terminal of AND logic gate 1106d is coupled to the input terminal of inverter 1121d.

[0371] The first input terminal of the AND logic gate 1106d is configured to receive the address signal LADR[2]. The second input terminal of the AND logic gate 1106d is configured to receive the address signal LADR[3].

[0372] The output terminal of AND logic gate 1106d is configured to output the body selection signal BS[3] in the body selection signal BS[0:3].

[0373] AND logic gate group 1108 is configured to generate clock signal group ICKD_TOP[0:3] in response to at least clock signal ICLK, body select enable signal BS_EN, and signal group TOP[0:3]. AND logic gate group 1108 includes at least one of AND logic gates 1108a, 1108b, 1108c, or 1108d.

[0374] In some embodiments, the body selection enable signal BS_EN corresponds to one body selection signal in the body selection signal group BS[0:3]. For example, in some embodiments, if the body selection is selected... Figure 1 and Figures 2A-2B The volume[1] array of memory partition 102D, then the volume selection enable signal BS_EN corresponds to the volume selection signal BS[0]. In some embodiments, if the selection Figure 1 and Figures 2A-2B The volume[2] array of the memory partition 102D, then the volume selection enable signal BS_EN corresponds to the volume selection signal BS[1]. In some embodiments, if the selection Figure 1 and Figures 2A-2B The volume[3] array of the memory partition 102D, then the volume selection enable signal BS_EN corresponds to the volume selection signal BS[2]. In some embodiments, if the selection Figure 1 and Figures 2A-2B If the memory partition 102D is a volume array[4], then the volume selection enable signal BS_EN corresponds to the volume selection signal BS[3].

[0375] AND logic gate 1108a is configured to generate clock signal ICKD_TOP[0] in clock signal group ICKD_TOP[0:3] in response to clock signal ICLK, body select enable signal BS_EN and signal TOP[0].

[0376] The first input terminal of AND logic gate 1108a is coupled to the output terminal of clock gate circuit 202, the second input terminal of AND logic gate 1108a is coupled to the output terminal of at least one of AND logic gates 1106a, 1106b, 1106c or 1106d based on the volume array of selected memory partitions 102A-102D, and the third input terminal of AND logic gate 1108a is coupled to the output terminal of AND logic gate 1102a.

[0377] The first input terminal of the AND logic gate 1108a is configured to receive the clock signal ICLK. The second input terminal of the AND logic gate 1108a is configured to receive the receiver selection enable signal BS_EN. The third input terminal of the AND logic gate 1108a is configured to receive the signal TOP[0].

[0378] The output terminal of AND logic gate 1108a is configured to output the clock signal ICKD_TOP[0] in the clock signal group ICKD_TOP[0:3].

[0379] The AND logic gate 1108b is configured to generate the clock signal ICKD_TOP[1] in the clock signal group ICKD_TOP[0:3] in response to the clock signal ICLK, the body selection enable signal BS_EN and the signal TOP[1].

[0380] The first input terminal of AND logic gate 1108b is coupled to the output terminal of clock gate circuit 202, the second input terminal of AND logic gate 1108b is coupled to the output terminal of at least one of AND logic gates 1106a, 1106b, 1106c or 1106d based on the volume array of selected memory partitions 102A-102D, and the third input terminal of AND logic gate 1108b is coupled to the output terminal of AND logic gate 1102b.

[0381] The first input terminal of the AND logic gate 1108b is configured to receive the clock signal ICLK. The second input terminal of the AND logic gate 1108b is configured to receive the receiver selection enable signal BS_EN. The third input terminal of the AND logic gate 1108b is configured to receive the signal TOP[1].

[0382] The output terminal of the AND logic gate 1108b is configured to output the clock signal ICKD_TOP[1] in the clock signal group ICKD_TOP[0:3].

[0383] The AND logic gate 1108c is configured to generate the clock signal ICKD_TOP[2] in the clock signal group ICKD_TOP[0:3] in response to the clock signal ICLK, the body selection enable signal BS_EN and the signal TOP[2].

[0384] The first input terminal of AND logic gate 1108c is coupled to the output terminal of clock gate circuit 202, the second input terminal of AND logic gate 1108c is coupled to the output terminal of at least one of AND logic gates 1106a, 1106b, 1106c or 1106d based on the volume array of selected memory partitions 102A-102D, and the third input terminal of AND logic gate 1108c is coupled to the output terminal of AND logic gate 1102c.

[0385] The first input terminal of the AND logic gate 1108c is configured to receive the clock signal ICLK. The second input terminal of the AND logic gate 1108c is configured to receive the receiver selection enable signal BS_EN. The third input terminal of the AND logic gate 1108c is configured to receive the signal TOP[2].

[0386] The output terminal of the AND logic gate 1108c is configured to output the clock signal ICKD_TOP[2] in the clock signal group ICKD_TOP[0:3].

[0387] The AND logic gate 1108d is configured to generate the clock signal ICKD_TOP[3] in the clock signal group ICKD_TOP[0:3] in response to the clock signal ICLK, the body selection enable signal BS_EN and the signal TOP[3].

[0388] The first input terminal of AND logic gate 1108d is coupled to the output terminal of clock gate circuit 202, the second input terminal of AND logic gate 1108d is coupled to the output terminal of at least one of AND logic gates 1106a, 1106b, 1106c or 1106d based on the volume array of selected memory partitions 102A-102D, and the third input terminal of AND logic gate 1108d is coupled to the output terminal of AND logic gate 1102d.

[0389] The first input terminal of the AND logic gate 1108d is configured to receive the clock signal ICLK. The second input terminal of the AND logic gate 1108d is configured to receive the receiver selection enable signal BS_EN. The third input terminal of the AND logic gate 1108d is configured to receive the signal TOP[3].

[0390] The output terminal of AND logic gate 1108d is configured to output the clock signal ICKD_TOP[3] in the clock signal group ICKD_TOP[0:3].

[0391] AND logic gate group 1110 is configured to generate clock signal group ICKD_BOT[0:3] in response to at least clock signal ICLK, body select enable signal BS_EN, and signal group BOT[0:3]. AND logic gate group 1110 includes at least one of AND logic gates 1110a, 1110b, 1110c, or 1110d.

[0392] AND logic gate 1110a is configured to generate the clock signal ICKD_BOT[0] in the clock signal group ICKD_BOT[0:3] in response to the clock signal ICLK, the body selection enable signal BS_EN and the signal BOT[0].

[0393] The first input terminal of AND logic gate 1110a is coupled to the output of clock gate circuit 202, the second input terminal of AND logic gate 1110a is coupled to the output terminal of at least one of AND logic gates 1106a, 1106b, 1106c or 1106d based on the volume array of selected memory partitions 102A-102D, and the third input terminal of AND logic gate 1110a is coupled to the output terminal of AND logic gate 1104a.

[0394] The first input terminal of the AND logic gate 1110a is configured to receive the clock signal ICLK. The second input terminal of the AND logic gate 1110a is configured to receive the receiver selection enable signal BS_EN. The third input terminal of the AND logic gate 1110a is configured to receive the signal BOT[0].

[0395] The output terminal of AND logic gate 1110a is configured to output the clock signal ICKD_BOT[0] in the clock signal group ICKD_BOT[0:3].

[0396] AND logic gate 1110b is configured to generate clock signal ICKD_BOT[1] in clock signal group ICKD_BOT[0:3] in response to clock signal ICLK, body select enable signal BS_EN and signal BOT[1].

[0397] The first input terminal of AND logic gate 1110b is coupled to the output of clock gate circuit 202, the second input terminal of AND logic gate 1110b is coupled to the output terminal of at least one of AND logic gates 1106a, 1106b, 1106c or 1106d based on the volume array of the selected memory partitions 102A-102D, and the third input terminal of AND logic gate 1110b is coupled to the output terminal of AND logic gate 1104b.

[0398] The first input terminal of the AND logic gate 1110b is configured to receive the clock signal ICLK. The second input terminal of the AND logic gate 1110b is configured to receive the receiver selection enable signal BS_EN. The third input terminal of the AND logic gate 1110b is configured to receive the signal BOT[1].

[0399] The output terminal of AND logic gate 1110b is configured to output the clock signal ICKD_BOT[1] in the clock signal group ICKD_BOT[0:3].

[0400] AND logic gate 1110c is configured to generate clock signal ICKD_BOT[2] in clock signal group ICKD_BOT[0:3] in response to clock signal ICLK, body select enable signal BS_EN and signal BOT[2].

[0401] The first input terminal of AND logic gate 1110c is coupled to the output of clock gate circuit 202, the second input terminal of AND logic gate 1110c is coupled to the output terminal of at least one of AND logic gates 1106a, 1106b, 1106c or 1106d based on the volume array of selected memory partitions 102A-102D, and the third input terminal of AND logic gate 1110c is coupled to the output terminal of AND logic gate 1104c.

[0402] The first input terminal of the AND logic gate 1110c is configured to receive the clock signal ICLK. The second input terminal of the AND logic gate 1110c is configured to receive the receiver selection enable signal BS_EN. The third input terminal of the AND logic gate 1110c is configured to receive the signal BOT[2].

[0403] The output terminal of AND logic gate 1110c is configured to output the clock signal ICKD_BOT[2] in the clock signal group ICKD_BOT[0:3].

[0404] AND logic gate 1110d is configured to generate clock signal ICKD_BOT[3] in response to clock signal ICLK, body select enable signal BS_EN and signal BOT[3] in clock signal group ICKD_BOT[0:3].

[0405] The first input terminal of AND logic gate 1110d is coupled to the output of clock gate circuit 202, the second input terminal of AND logic gate 1110d is coupled to the output terminal of at least one of AND logic gates 1106a, 1106b, 1106c or 1106d based on the volume array of selected memory partitions 102A-102D, and the third input terminal of AND logic gate 1110d is coupled to the output terminal of AND logic gate 1104d.

[0406] The first input terminal of the AND logic gate 1110d is configured to receive the clock signal ICLK. The second input terminal of the AND logic gate 1110d is configured to receive the receiver selection enable signal BS_EN. The third input terminal of the AND logic gate 1110d is configured to receive the signal BOT[3].

[0407] The output terminal of AND logic gate 1110d is configured to output the clock signal ICKD_BOT[3] in the clock signal group ICKD_BOT[0:3].

[0408] Other configurations, number of circuit elements, or types of circuit elements in the clock pre-decoder circuit 1100 are within the scope of this disclosure.

[0409] Post-word decoder circuit group

[0410] Figure 12 This is a circuit diagram of a word-line post-decoder circuit group 1200 according to some embodiments.

[0411] The decoder circuit group 1200 after the word line is Figures 2A-2B An embodiment of at least one of the word line decoder circuit groups 240a, 240b, 242a, 242b, 244a, 244b, 246a or 246b, and therefore similar detailed descriptions are omitted.

[0412] In some embodiments, the post-word line decoder circuit group 1200 is configured to generate word line signal group WL[0:63]. The number of other bits used for word line signal group WL[0:63] is within the scope of this disclosure.

[0413] The post-word line decoder circuit group 1200 includes at least one of post-word line decoder circuits 1202a, 1202b, 1202c, 1202d, 1202e, 1202f, 1202g, or 1202h. In some embodiments, the plurality of post-word line decoder circuits in the post-word line decoder circuit group 1202 correspond to the number of signals in at least one of the local pre-decoder signal groups PREDEC1_LOCAL[0:7] or PREDEC2_LOCAL[0:7].

[0414] The word-line decoder circuit group 1202a includes an AND logic gate group 1204a coupled to an inverter group 1206a. The output of the AND logic gate group 1204a is coupled to the corresponding input of the inverter group 1206a. The word-line decoder circuit group 1202a is configured to generate word line signal groups WL[0]-WL[7] in response to the local pre-decoder signal group PREDEC1[0:7], the local pre-decoder signal PREDEC2[0], and the clock signal group ICKD[0:3].

[0415] AND logic gate group 1204a is configured to generate signal group WLB in response to a local predecoder signal group PREDEC1_LOCAL[0:7], a local predecoder signal (e.g., PREDEC2_LOCAL[0]) of the second group of local predecoder signals PREDEC2_LOCAL[0:7], and clock signal group ICKD[0:3]. For simplicity, the local predecoder signals PREDEC1_LOCAL[0]-PREDEC1_LOCAL[7] are... Figure 12 The signal is shown as “PREDEC1[0]-PREDEC1_LOCAL[7]”. For simplicity, the local pre-decoder signal PREDEC2_LOCAL[0]-PREDEC2_LOCAL[7] is... Figure 12 It is shown as “PREDEC2[0]-PREDEC2_LOCAL[7]”.

[0416] In some embodiments, the post-word-line decoder circuit group 1200 corresponds to Figures 2A-2B The upper region of the WL driver circuit group 212a (e.g., post-word line decoder circuits 240a, 242a, 244a, or 246a) or Figures 2A-2B The lower region of the WL driver circuit group 212a (e.g. Figures 2A-2B The decoder circuit after the word line is 240b, 242b, 244b or 246b), and the clock signal group ICKD[0:3] corresponds to the clock signal group ICKD_TOP[0:3] or the clock signal group ICKD_BOT[0:3].

[0417] AND logic gate group 1204a includes AND logic gates 1204a0, 1204a1, 1204a2, 1204a3, 1204a4, 1204a5, 1204a6 and 1204a7.

[0418] The AND logic gate 1204a0 is configured to generate the signal WLB[0] in response to the local predecoder signal PREDEC2[0], the clock signal ICKD[0], and the local predecoder signal PREDEC1[0].

[0419] The first input terminals of each of the AND logic gates 1204a0-1204h0 are coupled together and receive the local pre-decoder signal PREDEC2_LOCAL[0].

[0420] The first input terminal of the AND logic gate 1204a0 is configured to receive the local pre-decoder signal PREDEC2[0]. The second input terminal of the AND logic gate 1204a0 is configured to receive the clock signal ICKD[0]. The third input terminal of the AND logic gate 1204a0 is configured to receive the local pre-decoder signal PREDEC1[0].

[0421] The output terminal of AND logic gate 1204a0 is configured to output the signal WLB[0] to the input terminal of the corresponding inverter 1206a0.

[0422] The AND logic gate 1204a1 is configured to generate signal WLB[1] in response to the local predecoder signal PREDEC2[0], the clock signal ICKD[1], and the local predecoder signal PREDEC1[1].

[0423] The first input terminal of the AND logic gate 1204a1 is configured to receive the local pre-decoder signal PREDEC2[0]. The second input terminal of the AND logic gate 1204a1 is configured to receive the clock signal ICKD[1]. The third input terminal of the AND logic gate 1204a1 is configured to receive the local pre-decoder signal PREDEC1[1].

[0424] The output terminal of AND logic gate 1204a1 is configured to output signal WLB[1] to the input terminal of the corresponding inverter 1206a1.

[0425] AND logic gate 1204a2 is configured to generate signal WLB[2] in response to local predecoder signal PREDEC2[0], clock signal ICKD[2] and local predecoder signal PREDEC1[2].

[0426] The first input terminal of the AND logic gate 1204a2 is configured to receive the local pre-decoder signal PREDEC2[0]. The second input terminal of the AND logic gate 1204a2 is configured to receive the clock signal ICKD[2]. The third input terminal of the AND logic gate 1204a2 is configured to receive the local pre-decoder signal PREDEC1[2].

[0427] The output terminal of AND logic gate 1204a2 is configured to output signal WLB[2] to the input terminal of the corresponding inverter 1206a2.

[0428] AND logic gate 1204a3 is configured to generate signal WLB[3] in response to local predecoder signal PREDEC2[0], clock signal ICKD[3] and local predecoder signal PREDEC1[3].

[0429] The first input terminal of the AND logic gate 1204a3 is configured to receive the local pre-decoder signal PREDEC2[0]. The second input terminal of the AND logic gate 1204a3 is configured to receive the clock signal ICKD[3]. The third input terminal of the AND logic gate 1204a3 is configured to receive the local pre-decoder signal PREDEC1[3].

[0430] The output terminal of AND logic gate 1204a3 is configured to output signal WLB[3] to the input terminal of the corresponding inverter 1206a3.

[0431] AND logic gate 1204a4 is configured to generate signal WLB[4] in response to local predecoder signal PREDEC2[0], clock signal ICKD[0] and local predecoder signal PREDEC1[4].

[0432] The first input terminal of the AND logic gate 1204a4 is configured to receive the local pre-decoder signal PREDEC2[0]. The second input terminal of the AND logic gate 1204a4 is configured to receive the clock signal ICKD[0]. The third input terminal of the AND logic gate 1204a4 is configured to receive the local pre-decoder signal PREDEC1[4].

[0433] The output terminal of AND logic gate 1204a4 is configured to output signal WLB[4] to the input terminal of the corresponding inverter 1206a4.

[0434] The AND logic gate 1204a5 is configured to generate the signal WLB[5] in response to the local predecoder signal PREDEC2[0], the clock signal ICKD[1], and the local predecoder signal PREDEC1[5].

[0435] The first input terminal of the AND logic gate 1204a5 is configured to receive the local pre-decoder signal PREDEC2[0]. The second input terminal of the AND logic gate 1204a5 is configured to receive the clock signal ICKD[1]. The third input terminal of the AND logic gate 1204a5 is configured to receive the local pre-decoder signal PREDEC1[5].

[0436] The output terminal of AND logic gate 1204a5 is configured to output signal WLB[5] to the input terminal of the corresponding inverter 1206a5.

[0437] The AND logic gate 1204a6 is configured to generate the signal WLB[6] in response to the local predecoder signal PREDEC2[0], the clock signal ICKD[2], and the local predecoder signal PREDEC1[6].

[0438] The first input terminal of the AND logic gate 1204a6 is configured to receive the local pre-decoder signal PREDEC2[0]. The second input terminal of the AND logic gate 1204a6 is configured to receive the clock signal ICKD[2]. The third input terminal of the AND logic gate 1204a6 is configured to receive the local pre-decoder signal PREDEC1[6].

[0439] The output terminal of the AND logic gate 1204a6 is configured to output the signal WLB[6] to the input terminal of the corresponding inverter 1206a6.

[0440] AND logic gate 1204a7 is configured to generate signal WLB[7] in response to local predecoder signal PREDEC2[0], clock signal ICKD[3] and local predecoder signal PREDEC1[7].

[0441] The first input terminal of the AND logic gate 1204a7 is configured to receive the local pre-decoder signal PREDEC2[0]. The second input terminal of the AND logic gate 1204a7 is configured to receive the clock signal ICKD[3]. The third input terminal of the AND logic gate 1204a7 is configured to receive the local pre-decoder signal PREDEC1[7].

[0442] The output terminal of AND logic gate 1204a7 is configured to output signal WLB[7] to the input terminal of the corresponding inverter 1206a7.

[0443] Inverter group 1206a is configured to generate word line signal group WL in response to signal group WLB. In some embodiments, signal group WLB is inverted with word line signal group WL.

[0444] The inverter group 1206a includes inverters 1206a0, 1206a1, 1206a2, 1206a3, 1206a4, 1206a5, 1206a6 and 1206a7.

[0445] Each inverter 1206a0, 1206a1, 1206a2, 1206a3, 1206a4, 1206a5, 1206a6 and 1206a7 in inverter group 1206 is configured to generate corresponding word line signals WL[0], WL[1], WL[2], WL[3], WLB[4], WLB[5], WLB[6] and WLB[7] in response to corresponding signals WLB[0], WL[1], WL[2], WL[3], WL[4], WL[5], WL[6] and WL[7].

[0446] Each inverter 1206a0, 1206a1, 1206a2, 1206a3, 1206a4, 1206a5, 1206a6 and 1206a7 in inverter group 1206 is configured to output corresponding word line signals WL[0], WL[1], WL[2], WL[3], WL[4], WL[5], WL[6] and WL[7].

[0447] The description of each of the post-word-line decoder circuit groups 1202b, 1202c, 1202d, 1202e, 1202f, 1202g, or 1202h is similar to that of post-word-line decoder circuit group 1202a, and details will be omitted for brevity. However, the local pre-decoder signal PREDEC2[0] of the word-line decoder circuit 1202a and the AND logic gate group 1204a are replaced by the local pre-decoder signals PREDEC2[1], PREDEC2[2], PREDEC2[3], PREDEC2[4], PREDEC2[5], PREDEC2[6] or PREDEC2[7] of the corresponding word-line decoder circuits 1202b, 1202c, 1202d, 1202e, 1202f, 1202g or 1202h and the corresponding AND logic gate groups 1204b, 1204c, 1204d, 1204e, 1204f, 1204g or 1204h.

[0448] The word line decoder circuit group 1202b includes an AND logic gate group 1204b coupled to the inverter group 1206b. The output of the AND logic gate group 1204b is coupled to the corresponding input of the inverter group 1206b. The word line decoder circuit group 1202b is configured to generate word line signal groups WL[8]-WL

[15] in response to the local pre-decoder signal group PREDEC1[0:7], the local pre-decoder signal PREDEC2[1], and the clock signal group ICKD[0:3].

[0449] AND logic gate group 1204b includes AND logic gates 1204b0, 1204b1, 1204b2, 1204b3, 1204b4, 1204b5, 1204b6 and 1204b7.

[0450] The inverter group 1206b includes inverters 1206b0, 1206b1, 1206b2, 1206b3, 1206b4, 1206b5, 1206b6 and 1206b7.

[0451] Each inverter 1206b0, 1206b1, 1206b2, 1206b3, 1206b4, 1206b5, 1206b6 and 1206b7 in inverter group 1206 is configured to generate corresponding word line signals WL[8], WL[9], WL

[10] , WL

[11] , WL

[12] , WL

[13] , WL

[14] and WL

[15] in response to corresponding signals WLB[8], WL[9], WL

[10] , WL

[11] , WL

[12] , WL

[13] , WL

[14] and WL

[15] .

[0452] Each inverter 1206b0, 1206b1, 1206b2, 1206b3, 1206b4, 1206b5, 1206b6 and 1206b7 in inverter group 1206 is configured to output the corresponding word line signals WL[8], WL[9], WL

[10] , WL

[11] , WL

[12] , WL

[13] , WL

[14] and WL

[15] .

[0453] The word-line decoder circuit group 1202c includes an AND logic gate group 1204c coupled to an inverter group 1206c. The output of the AND logic gate group 1204c is coupled to the corresponding input of the inverter group 1206c. The word-line decoder circuit group 1202c is configured to generate a word line signal WL in response to the local pre-decoder signal group PREDEC1[0:7], the local pre-decoder signal PREDEC2[2], and the clock signal group ICKD[0:3].

[0454] The AND logic gate group 1204c includes AND logic gates 1204c0, 1204c1, 1204c2, 1204c3, 1204c4, 1204c5, 1204c6 and 1204c7.

[0455] The inverter group 1206c includes inverters 1206c0, 1206c1, 1206c2, 1206c3, 1206c4, 1206c5, 1206c6 and 1206c7.

[0456] Each inverter 1206c0, 1206c1, 1206c2, 1206c3, 1206c4, 1206c5, 1206c6 and 1206c7 in inverter group 1206 is configured to generate corresponding word line signals WL

[16] , WL

[17] , WL

[18] , WL

[19] , WL

[20] , WL

[21] , WL

[22] and WL

[23] in response to corresponding signals WLB

[16] , WL

[17] , WL

[18] , WL

[19] , WL

[20] , WL

[21] , WL

[22] and WL

[23] .

[0457] Each inverter 1206c0, 1206c1, 1206c2, 1206c3, 1206c4, 1206c5, 1206c6 and 1206c7 in inverter group 1206 is configured to output the corresponding word line signals WL

[16] , WL

[17] , WL

[18] , WL

[19] , WL

[20] , WL

[21] , WL

[22] and WL

[23] .

[0458] The word line decoder circuit group 1202d includes an AND logic gate group 1204d coupled to the inverter group 1206d. The output of the AND logic gate group 1204d is coupled to the corresponding input of the inverter group 1206d. The word line decoder circuit group 1202d is configured to generate word line signal groups WL

[24] -WL

[31] in response to the local pre-decoder signal group PREDEC1[0:7], the local pre-decoder signal PREDEC2[3], and the clock signal group ICKD[0:3].

[0459] AND logic gate group 1204d includes AND logic gates 1204d0, 1204d1, 1204d2, 1204d3, 1204d4, 1204d5, 1204d6 and 1204d7.

[0460] The inverter group 1206d includes inverters 1206d0, 1206d1, 1206d2, 1206d3, 1206d4, 1206d5, 1206d6 and 1206d7.

[0461] Each inverter 1206d0, 1206d1, 1206d2, 1206d3, 1206d4, 1206d5, 1206d6 and 1206d7 in inverter group 1206 is configured to generate corresponding word line signals WL

[24] , WL

[25] , WL

[26] , WL

[27] , WL

[28] , WL

[29] , WL

[30] and WL

[31] in response to corresponding signals WLB

[24] , WL

[25] , WL

[26] , WL

[27] , WL

[28] , WL

[29] , WL

[30] and WL

[31] .

[0462] Each inverter 1206d0, 1206d1, 1206d2, 1206d3, 1206d4, 1206d5, 1206d6 and 1206d7 in inverter group 1206 is configured to output the corresponding word line signals WL

[24] , WL

[25] , WL

[26] , WL

[27] , WL

[28] , WL

[29] , WL

[30] and WL

[31] .

[0463] The word-line decoder circuit group 1202e includes an AND logic gate group 1204e coupled to the inverter group 1206e. The output of the AND logic gate group 1204e is coupled to the corresponding input of the inverter group 1206e. The word-line decoder circuit group 1202e is configured to generate the word line signal WL in response to the local pre-decoder signal group PREDEC1[0:7], the local pre-decoder signal PREDEC2[4], and the clock signal group ICKD[0:3].

[0464] AND logic gate group 1204e includes AND logic gates 1204e0, 1204e1, 1204e2, 1204e3, 1204e4, 1204e5, 1204e6 and 1204e7.

[0465] The inverter group 1206e includes inverters 1206e0, 1206e1, 1206e2, 1206e3, 1206e4, 1206e5, 1206e6 and 1206e7.

[0466] Each inverter 1206e0, 1206e1, 1206e2, 1206e3, 1206e4, 1206e5, 1206e6 and 1206e7 in inverter group 1206 is configured to generate corresponding word line signals WL

[32] , WL

[33] , WL

[34] , WL

[35] , WL

[36] , WL

[37] , WL

[38] and WL

[39] in response to corresponding signals WLB

[32] , WL

[33] , WL

[34] , WL

[35] , WL

[36] , WL

[37] , WL

[38] and WL

[39] .

[0467] Each inverter 1206e0, 1206e1, 1206e2, 1206e3, 1206e4, 1206e5, 1206e6 and 1206e7 in inverter group 1206 is configured to output the corresponding word line signals WL

[32] , WL

[33] , WL

[34] , WL

[35] , WL

[36] , WL

[37] , WL

[38] and WL

[39] .

[0468] The word-line decoder circuit group 1202f includes an AND logic gate group 1204f coupled to an inverter group 1206f. The output of the AND logic gate group 1204f is coupled to the corresponding input of the inverter group 1206f. The word-line decoder circuit group 1202f is configured to generate the word line signal WL in response to the local pre-decoder signal group PREDEC1[0:7], the local pre-decoder signal PREDEC2[5], and the clock signal group ICKD[0:3].

[0469] AND logic gate group 1204f includes AND logic gates 1204f0, 1204f1, 1204f2, 1204f3, 1204f4, 1204f5, 1204f6 and 1204f7.

[0470] The inverter group 1206f includes inverters 1206f0, 1206f1, 1206f2, 1206f3, 1206f4, 1206f5, 1206f6 and 1206f7.

[0471] Each inverter 1206f0, 1206f1, 1206f2, 1206f3, 1206f4, 1206f5, 1206f6 and 1206f7 in inverter group 1206 is configured to generate corresponding word line signals WL

[40] , WL

[41] , WL

[42] , WL

[43] , WL

[44] , WL

[45] , WL

[46] and WL

[47] in response to corresponding signals WLB

[40] , WL

[41] , WL

[42] , WL

[43] , WL

[44] , WL

[45] , WL

[46] and WL

[47] .

[0472] Each inverter 1206f0, 1206f1, 1206f2, 1206f3, 1206f4, 1206f5, 1206f6 and 1206f7 in inverter group 1206 is configured to output the corresponding word line signals WL

[40] , WL

[41] , WL

[42] , WL

[43] , WL

[44] , WL

[45] , WL

[46] and WL

[47] .

[0473] The word line decoder circuit group 1202g includes an AND logic gate group 1204g coupled to the inverter group 1206g. The output of the AND logic gate group 1204g is coupled to the corresponding input of the inverter group 1206g. The word line decoder circuit group 1202g is configured to generate word line signal groups WL

[48] -WL

[55] in response to the local pre-decoder signal group PREDEC1[0:7], the local pre-decoder signal PREDEC2[6], and the clock signal group ICKD[0:3].

[0474] The AND logic gate group 1204g includes AND logic gates 1204g0, 1204g1, 1204g2, 1204g3, 1204g4, 1204g5, 1204g6 and 1204g7.

[0475] The inverter group 1206g includes inverters 1206g0, 1206g1, 1206g2, 1206g3, 1206g4, 1206g5, 1206g6 and 1206g7.

[0476] Each inverter 1206g0, 1206g1, 1206g2, 1206g3, 1206g4, 1206g5, 1206g6 and 1206g7 in inverter group 1206 is configured to generate corresponding word line signals WL

[48] , WL

[49] , WL

[50] , WL

[51] , WL

[52] , WL

[53] , WL

[54] and WL

[55] in response to corresponding signals WLB

[48] , WL

[49] , WL

[50] , WL

[51] , WL

[52] , WL

[53] , WL

[54] and WL

[55] .

[0477] Each inverter 1206g0, 1206g1, 1206g2, 1206g3, 1206g4, 1206g5, 1206g6 and 1206g7 in inverter group 1206 is configured to output the corresponding word line signals WL

[48] , WL

[49] , WL

[50] , WL

[51] , WL

[52] , WL

[53] , WL

[54] and WL

[55] .

[0478] The word line decoder circuit group 1202h includes an AND logic gate group 1204h coupled to the inverter group 1206h. The output of the AND logic gate group 1204h is coupled to the corresponding input of the inverter group 1206h. The word line decoder circuit group 1202h is configured to generate the word line signal WL in response to the local pre-decoder signal group PREDEC1[0:7], the local pre-decoder signal PREDEC2[7], and the clock signal group ICKD[0:3].

[0479] AND logic gate group 1204h includes AND logic gates 1204h0, 1204h1, 1204h2, 1204h3, 1204h4, 1204h5, 1204h6 and 1204h7.

[0480] The inverter group 1206h includes inverters 1206h0, 1206h1, 1206h2, 1206h3, 1206h4, 1206h5, 1206h6 and 1206h7.

[0481] Each inverter 1206h0, 1206h1, 1206h2, 1206h3, 1206h4, 1206h5, 1206h6 and 1206h7 in inverter group 1206 is configured to generate corresponding word line signals WL

[56] , WL

[57] , WL

[58] , WL

[59] , WL

[60] , WL

[61] , WL

[62] and WL

[63] in response to corresponding signals WLB

[56] , WL

[57] , WL

[58] , WL

[59] , WL

[60] , WL

[61] , WL

[62] and WL

[63] .

[0482] Each inverter 1206h0, 1206h1, 1206h2, 1206h3, 1206h4, 1206h5, 1206h6 and 1206h7 in inverter group 1206 is configured to output the corresponding word line signals WL

[56] , WL

[57] , WL

[58] , WL

[59] , WL

[60] , WL

[61] , WL

[62] and WL

[63] .

[0483] Other configurations, number of circuit elements, or types of circuit elements in the post-word decoder circuit group 1200 are within the scope of this disclosure.

[0484] memory unit

[0485] Figure 13 It is available according to some embodiments. Figure 1 and Figures 2A-2B The circuit diagram of memory cell 1300.

[0486] Memory unit 1300 can be used as Figure 1 Memory cell array 110AR, Figure 1 Memory device 112, Figure 2A Memory cell array 210a or Figure 2A One or more memory cells MCB in at least one of the memory cell arrays 210b.

[0487] Memory cell 1300 is a six-transistor (6T) single-port (SP) SRAM memory cell for illustration. In some embodiments, memory cell 1300 employs multiple transistors in addition to six. Other types of memory are within the scope of various embodiments.

[0488] Memory cell 1300 includes two P-type metal-oxide-semiconductor (PMOS) transistors P1 and P2, and four N-type metal-oxide-semiconductor (NMOS) transistors N1, N2, N3, and N4. Transistors P1, P2, N1, and N2 form a cross-latched or cross-coupled inverter pair. For example, PMOS transistor P1 and NMOS transistor N1 form a first inverter, while PMOS transistor P2 and NMOS transistor N2 form a second inverter.

[0489] The source terminal of each of PMOS transistors P1 and P2 is configured as a supply voltage node _1. Each supply voltage node _1 is coupled to a first voltage source VDDI. The drain terminal of PMOS transistor P1 is coupled to the drain terminal of NMOS transistor N1, the gate terminal of PMOS transistor P2, the gate terminal of NMOS transistor N2, and the source terminal of NMOS transistor N3, and is configured as a storage node ND.

[0490] The drain terminal of PMOS transistor P2 is coupled to the drain terminal of NMOS transistor N2, the gate terminal of PMOS transistor P1, the gate terminal of NMOS transistor N1, and the source terminal of NMOS transistor N4, and is configured as a storage node NDB. The source terminal of each of NMOS transistors N1 and N2 is configured as a supply reference voltage node (unlabeled) with a supply reference voltage VSS. The source terminal of each of NMOS transistors N1 and N2 is also coupled to the supply reference voltage VSS.

[0491] Word line WL is coupled to the gate terminal of each of NMOS transistors N3 and N4. Word line WL is also referred to as the write control line because NMOS transistors N3 and N4 are configured to be controlled by signals on word line WL to transfer data between bit lines BL, BLB and the corresponding nodes ND, NDB.

[0492] The drain terminal of NMOS transistor N3 is coupled to bit line BL. The drain terminal of NMOS transistor N4 is coupled to bit line BLB. Bit lines BL and BLB are configured as data inputs and outputs for memory cell 1300. In some embodiments, during a write operation, a logic value is applied to the first bit line BL and an inverted logic value is applied to the other bit line BLB, enabling the writing of logic values ​​on bit lines BL and BLB to memory cell 1300. Each of bit lines BL and BLB is referred to as a data line because the data carried on bit lines BL and BLB is written to and read from the corresponding nodes ND and NDB.

[0493] The word line WL corresponds to Figure 2A One or more word lines WL in the code. Bit line BL corresponds to... Figure 2A One or more bit lines BL in the array. Bit line BLB corresponds to... Figure 2A One or more inverted bit lines (BLBs) in the middle.

[0494] Other configurations of the memory unit 1300 are within the scope of this invention.

[0495] method

[0496] Figure 14 This is a flowchart of a method 1400 for operating circuits according to some embodiments.

[0497] In some embodiments, Figure 14 It is an operation Figure 1 Memory circuit 100 Figures 2A-2B Memory circuit 200, Figures 3-8 Circuits 300, 400, 500, 600, 700 or 800, Figures 9A-9B Pre-decoder circuits 900A-900B Figure 10 Address latch circuit 1000 Figure 11 Clock pre-decoder circuit 1100 Figure 12 The word line after the decoder circuit group 1200 and Figure 13 A flowchart of a method for at least one of the memory units 1300.

[0498] It should be understood that it is possible Figure 14 Additional operations are performed before, during, and / or after method 1400 as described in the text. (See reference...) Figure 14Other operations are only briefly described here. It should be understood that method 1400 utilizes features of one or more of the following: memory circuits 100-200, circuits 300-800, pre-decoder circuits 900A-900B, address latch circuit 1000, clock pre-decoder circuit 1100, word line decoder circuit group 1200, or memory cell 1300; similar detailed descriptions are omitted for brevity.

[0499] In some embodiments, the order of other operations of method 1400 is within the scope of this disclosure. Method 1400 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, substituted, rearranged, and / or eliminated in accordance with the spirit and scope of the disclosed embodiments. In some embodiments, one or more operations of method 1400 are not performed.

[0500] In operation 1402 of method 1400, a first clock signal is generated by clock gating circuit 202 in response to a second clock signal (CLK) and a chip enable signal (CE).

[0501] In some embodiments, the first clock signal of method 1400 includes clock signal ICLK. In some embodiments, the second clock signal of method 1400 includes clock signal CLK. In some embodiments, the chip enable signal of method 1400 includes chip enable signal CEB.

[0502] In operation 1404 of method 1400, a first set of global predecoder signals, a second set of global predecoder signals, and a first set of local address signals are generated in response to a memory address signal and a first clock. In some embodiments, the first set of global predecoder signals, the second set of global predecoder signals, and the first set of local address signals are generated by global control circuit 201.

[0503] In some embodiments, the first set of global predecoder signals of method 1400 includes the global predecoder signal group PREDEC1_GLOBAL. In some embodiments, the second set of global predecoder signals of method 1400 includes the global predecoder signal group PREDEC2_GLOBAL. In some embodiments, the first set of local address signals of method 1400 includes the first set of address signals LADR[0:4]. In some embodiments, the memory address signals of method 1400 include the memory address signal ADR.

[0504] In operation 1406 of method 1400, a first set of clock signals and a second set of clock signals are generated in response to a first set of local address signals and a first clock signal. In some embodiments, the first set of clock signals and the second set of clock signals of method 1400 are generated by a first clock pre-decoder circuit. In some embodiments, the first clock pre-decoder circuit is coupled to a global control circuit. In some embodiments, the first clock pre-decoder circuit of method 1400 includes at least one of clock pre-decoder circuits 220a, 220b, 220c, or 220d or clock pre-decoder circuit 1100 in clock pre-decoder circuit group 220.

[0505] In some embodiments, the first set of clock signals in method 1400 includes clock signal group ICKD_TOP. In some embodiments, the second set of clock signals in method 1400 includes clock signal group ICKD_BOT.

[0506] In operation 1408 of method 1400, a first set of local predecoder signals is generated in response to a first set of global predecoder signals, and a second set of local predecoder signals is generated in response to a second set of global predecoder signals.

[0507] In some embodiments, the first set of local predecoder signals of method 1400 includes the local predecoder signal group PREDEC1_LOCAL[0:7]. In some embodiments, the second set of local predecoder signals of method 1400 includes the local predecoder signal group PREDEC2_LOCAL[0:7].

[0508] In some embodiments, the first set of local pre-decoder signals and the second set of local pre-decoder signals of method 1400 are generated by a first set of repeater circuits (e.g., repeater groups 230a, 230b, 230c, or 230d). In some embodiments, the first set of local pre-decoder signals of method 1400 is generated by at least one of inverter groups 330, 430, 440, 442, 450, 452, 540, 550, or 630. The second set of local pre-decoder signals of method 1400 is generated by at least one of inverter groups 332, 432, 444, 446, 454, 456, 542, 552, or 630.

[0509] In operation 1410 of method 1400, a first set of word line signals is generated in response to a first set of clock signals, a first set of local pre-decoder signals, and a second set of local pre-decoder signals.

[0510] In some embodiments, the first set of word line signals in method 1400 is generated by a first set of word line post-decoder circuit. In some embodiments, the first set of word line post-decoder circuit is coupled to a first clock pre-decoder circuit and a first set of repeater circuits.

[0511] In some embodiments, the first set of word line decoder circuits of method 1400 includes at least one of word line decoder circuit groups 240a, 242a, 244a or 246a or word line decoder group 1200. In some embodiments, the first set of word line signals of method 1400 includes word line group WL.

[0512] In operation 1412 of method 1400, at least in response to a first set of word line signals, a first set of data is stored in a first set of memory cells. In some embodiments, the first set of memory cells in method 1400 includes a memory cell array 210a. In some embodiments, the first set of memory cells is coupled to a first set of word line decoder circuitry. In some embodiments, the first set of data in method 1400 includes a series of data, including at least one logic low or logic high.

[0513] In operation 1414 of method 1400, a second set of word line signals (WL2) are generated in response to the second set of clock signals, the first set of local pre-decoder signals, and the second set of local pre-decoder signals.

[0514] In some embodiments, the second set of word line signals in method 1400 is generated by a second set of word line post-decoder circuit. In some embodiments, the second set of word line post-decoder circuit is coupled to a first clock pre-decoder circuit and a first set of repeater circuits.

[0515] In some embodiments, the second set of word line decoder circuitry of method 1400 includes at least one of word line decoder circuit groups 240b, 242b, 244b or 246b or word line decoder group 1200. In some embodiments, the second set of word line signals of method 1400 includes word line group WL.

[0516] In operation 1416 of method 1400, at least in response to a second set of word line signals, a second set of data is stored in a second set of memory cells. In some embodiments, the second set of memory cells in method 1400 includes a memory cell array 210b. In some embodiments, the second set of memory cells is coupled to a second set of word line decoder circuitry. In some embodiments, the second set of data in method 1400 includes another series of data, including at least one logic low or logic high.

[0517] By using operation method 1400, the circuit operation achieves the above-mentioned... Figure 1 Memory circuit 100 Figures 2A-2B Memory circuit 200, Figures 3-8 Circuits 300, 400, 500, 600, 700 or 800, Figures 9A-9B Pre-decoder circuits 900A-900B Figure 10 Address latch circuit 1000 Figure 11 Clock pre-decoder circuit 1100 Figure 12 The word line after the decoder circuit group 1200 and Figure 13 The benefits discussed in at least one of the memory cells 1300.

[0518] In some embodiments, one or more operations of method 1400 are not performed. Furthermore, Figures 1-13 The various PMOS or NMOS transistors shown have specific dopant types (e.g., N-type or P-type) for illustrative purposes. The embodiments of this disclosure are not limited to specific transistor types. Figures 1-13 One or more of the PMOS or NMOS transistors shown can be replaced by corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of the various signals used in the above description are for illustrative purposes only. The embodiments of this disclosure are not limited to specific logic values ​​when signals are activated and / or deactivated. Different logic values ​​are chosen within the range of various embodiments. Figures 3-12 Different numbers of inverters are selected within a range of various embodiments. Figures 3-12 Different numbers of transistors are selected within a range of various embodiments. Figures 3-12 Different numbers of AND logic gates are selected within the range of various embodiments. Figures 3-12 Different types of logic gates are selected within the range of various embodiments.

[0519] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to influence various modifications, substitutions of equivalents, and various other embodiments widely disclosed herein. Therefore, the protection granted herein is intended to be limited only to the definitions contained in this disclosure and its equivalents.

[0520] One aspect of this description relates to a memory circuit. The memory circuit includes a global control circuit configured to generate a first set of global pre-decoder signals, a second set of global pre-decoder signals, and a first set of local address signals in response to a memory address signal and a first clock signal. In some embodiments, the memory circuit further includes a first local control circuit coupled to the global control circuit. In some embodiments, the first local control circuit includes a first set of repeater circuitry configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and to generate a second set of local pre-decoder signals in response to the second set of global pre-decoder signals. In some embodiments, the first local control circuitry further includes a first clock pre-decoder circuitry coupled to the global control circuitry and configured to generate a first set of clock signals and a second set of clock signals in response to the first set of local address signals and the first clock signal. In some embodiments, the memory circuitry further includes a first set of word-line decoder circuitry coupled to the first clock pre-decoder circuitry and the first set of repeater circuitry, and configured to generate a first set of word-line signals in response to the first set of clock signals, the first set of local pre-decoder signals, and the second set of local pre-decoder signals. In some embodiments, the memory circuitry further includes a first set of memory cells coupled to a first set of word-line decoder circuitry and configured to store a first set of data at least in response to a first set of word-line signals. In some embodiments, the memory circuitry further includes a second set of word-line decoder circuitry coupled to a first clock pre-decoder circuitry and a first set of repeater circuitry, and configured to generate a second set of word-line signals in response to a second set of clock signals, a first set of local pre-decoder signals, and a second set of local pre-decoder signals. In some embodiments, the memory circuitry further includes a second set of memory cells coupled to a second set of word-line decoder circuitry and configured to store a second set of data at least in response to a second set of word-line signals. In some embodiments, the memory circuitry further includes a first word-line driver circuitry including the first set of word-line decoder circuitry; and a second set of repeater circuitry coupled between the output of the first set of repeater circuitry and the first set of word-line decoder circuitry. In some embodiments, the memory circuitry further includes a second word-line driver circuitry including the second set of word-line decoder circuitry; and a third set of repeater circuitry coupled between the output of the first set of repeater circuitry and the second set of word-line decoder circuitry. In some embodiments, the first set of repeater circuits includes a first set of buffers, each buffer in the first set of buffers being configured to generate a corresponding signal of a first set of local predecoder signals in response to a corresponding signal of a first set of global predecoder signals; and a second set of buffers, each buffer in the second set of buffers being configured to generate a corresponding signal of a second set of local predecoder signals in response to a corresponding signal of a second set of global predecoder signals.In some embodiments, the first set of repeater circuits includes a first set of inverters, each inverter in the first set of inverters being configured to generate a corresponding signal of a first set of local predecoder signals in response to a corresponding signal of a first set of global predecoder signals; and a second set of inverters, each inverter in the second set of inverters being configured to generate a corresponding signal of a second set of local predecoder signals in response to a corresponding signal of a second set of global predecoder signals. In some embodiments, the memory circuitry further includes a first global predecoder line extending at least in a first direction, overlapping at least with a first local control circuit, coupled to the global control circuit and a first set of repeater circuits, and configured to provide a first set of global predecoder signals; a second global predecoder line extending at least in a first direction, overlapping at least with the first local control circuit, coupled to the global control circuit and the first set of repeater circuits, and configured to provide a second set of global predecoder signals; a first local predecoder line extending at least in a first direction, overlapping at least with the first local control circuit, coupled to the first set of repeater circuits, and configured to provide a first set of local predecoder signals; and a second local predecoder line extending at least in a first direction, overlapping at least with the first local control circuit, coupled to the first set of repeater circuits, and configured to provide a second set of local predecoder signals. In some embodiments, the first global predecoder line is located on a first metal layer; the second global predecoder line is located on the first metal layer; the first local predecoder line is located on a second metal layer different from the first metal layer; and the second local predecoder line is located on the second metal layer. In some embodiments, the first metal layer corresponds to a second metal layer; and the second metal layer corresponds to a fourth metal layer. In some embodiments, the first global predecoder line has a first width in a second direction different from the first direction; the second global predecoder line has a first width in the second direction; the first local predecoder line has a second width in the second direction, the second width being smaller than the first width; and the second local predecoder line has a second width in the second direction.

[0521] Another aspect of this specification relates to memory circuitry. The memory circuitry includes global control circuitry configured to generate a first set of global pre-decoder signals, a second set of global pre-decoder signals, and a first set of local address signals in response to a memory address signal and a first clock signal. In some embodiments, the memory circuitry further includes a first local control circuitry coupled to the global control circuitry. In some embodiments, the first local control circuitry includes a first clock pre-decoder circuitry coupled to the global control circuitry and configured to generate a first set of clock signals and a second set of clock signals in response to the first set of local address signals and the first clock signal. In some embodiments, the memory circuitry also includes a first word line driver circuitry. In some embodiments, the first word line driver circuitry includes a first set of repeater circuitry configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and to generate a second set of local pre-decoder signals in response to the second set of global pre-decoder signals. In some embodiments, the first word line driver circuitry further includes a first set of word line post-decoder circuitry coupled to the first clock pre-decoder circuitry and the first set of repeater circuitry, and configured to generate the first set of word line signals in response to the first set of clock signals, the first set of local pre-decoder signals, and the second set of local pre-decoder signals. In some embodiments, the memory circuitry further includes a first set of memory cells coupled to a first set of word-line decoder circuitry and configured to store a first set of data at least in response to a first set of word-line signals. In some embodiments, the memory circuitry further includes a second set of word-line driver circuitry, comprising a second set of repeater circuitry configured to generate a first set of local pre-decoder signals in response to a first set of global pre-decoder signals and to generate a second set of local pre-decoder signals in response to a second set of global pre-decoder signals; and a second set of word-line decoder circuitry coupled to a first clock pre-decoder circuitry and a second set of repeater circuitry, configured to generate a second set of word-line signals in response to a second set of clock signals, the first set of local pre-decoder signals, and the second set of local pre-decoder signals. In some embodiments, the memory circuitry further includes a second set of memory cells coupled to a second set of word-line decoder circuitry and configured to store a second set of data at least in response to a second set of word-line signals. In some embodiments, at least one of the first set of repeater circuits or the second set of repeater circuits includes a first set of buffers, each buffer in the first set of buffers being configured to generate a corresponding signal of a first set of local pre-decoder signals in response to a corresponding signal of a first set of global pre-decoder signals; and a second set of buffers, each buffer in the second set of buffers being configured to generate a corresponding signal of a second set of local pre-decoder signals in response to a corresponding signal of a second set of global pre-decoder signals.In some embodiments, at least one of the first set of repeater circuits or the second set of repeater circuits includes a first set of inverters, each inverter in the first set of inverters being configured to generate a corresponding signal of a first set of local pre-decoder signals in response to a corresponding signal of a first set of global pre-decoder signals; and a second set of inverters, each inverter in the second set of inverters being configured to generate a corresponding signal of a second set of local pre-decoder signals in response to a corresponding signal of a second set of global pre-decoder signals. In some embodiments, the global control circuit includes a clock gating circuit configured to generate a first clock signal in response to a second clock signal and a chip enable signal; an address latch circuit configured to generate a first set of local address signals, a second set of local address signals, and a third set of local address signals in response to a memory address signal; a first pre-decoder circuit coupled to the address latch circuit and configured to generate a first set of global pre-decoder signals in response to at least a second set of local address signals or an inverted second set of local address signals; and a second pre-decoder circuit coupled to the address latch circuit and configured to generate a second set of global pre-decoder signals in response to at least a third set of local address signals or an inverted third set of local address signals. In some embodiments, the first clock pre-decoder circuit includes: a first set of AND logic gates configured to generate a first set of signals in response to a first set of local address signals and an inverted first set of local address signals; a second set of AND logic gates configured to generate a second set of signals in response to the first set of local address signals and an inverted first set of local address signals; a third set of AND logic gates configured to generate a first set of body selection signals in response to the first set of local address signals and an inverted first set of local address signals; a fourth set of AND logic gates coupled to the first set of AND logic gates and the third set of AND logic gates, and configured to generate the first set of clock signals in response to the first set of signals and the first set of body selection signals; and a fifth set of AND logic gates coupled to the second set of AND logic gates and the third set of AND logic gates, and configured to generate the second set of clock signals in response to the second set of signals and the first set of body selection signals. In some embodiments, each word-line decoder circuit in the first set of word-line decoder circuits includes: a first set of AND logic gates configured to generate a first set of signals in response to a first set of local pre-decoder signals, a second set of local pre-decoder signals, and a first set of clock signals or a second set of clock signals; and a first set of inverters coupled to the first set of AND logic gates and configured to generate a first set of word-line signals in response to the first set of signals, wherein the first set of signals is inverted from the first set of word-line signals.

[0522] Another aspect of this specification relates to a method of operating a memory circuit. The method includes: generating a first set of global pre-decoder signals, a second set of global pre-decoder signals, and a first set of local address signals via a global control circuit in response to a memory address signal and a first clock signal. In some embodiments, the method further includes: generating a first set of clock signals and a second set of clock signals via a first clock pre-decoder circuit in response to the first set of local address signals and the first clock signal, the first clock pre-decoder circuit being coupled to the global control circuit. In some embodiments, the method further includes: generating a first set of local pre-decoder signals via a first set of repeater circuits in response to the first set of global pre-decoder signals, and generating a second set of local pre-decoder signals in response to the second set of global pre-decoder signals. In some embodiments, the method further includes: generating a first set of word line signals via a first set of word-line decoder circuits in response to the first set of clock signals, the first set of local pre-decoder signals, and the second set of local pre-decoder signals, the first set of word-line decoder circuits being coupled to the first clock pre-decoder circuit and the first set of repeater circuits. In some embodiments, the method further includes: storing a first set of data in a first set of memory cells in response to at least the first set of word line signals, the first set of memory cells being coupled to the first set of word-line decoder circuits. In some embodiments, the method further includes: generating a second set of word line signals by a second set of word line decoder circuits in response to a second set of clock signals, a first set of local pre-decoder signals, and a second set of local pre-decoder signals, wherein the second set of word line decoder circuits is coupled to a first clock pre-decoder circuit and a first set of repeater circuits; and storing a second set of data in a second set of memory cells in response to at least the second set of word line signals, wherein the second set of memory cells is coupled to the second set of word line decoder circuits.

[0523] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A memory circuit, comprising: The global control circuit is configured to generate a first set of global pre-decoder signals, a second set of global pre-decoder signals, and a first set of local address signals in response to a memory address signal and a first clock signal. A first local control circuit is coupled to the global control circuit, the first local control circuit comprising: The first set of repeater circuits is configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and to generate a second set of local pre-decoder signals in response to the second set of global pre-decoder signals; and A first clock pre-decoder circuit, coupled to the global control circuit, is configured to generate a first set of clock signals and a second set of clock signals in response to the first set of local address signals and the first clock signal; and The first set of word line decoder circuitry is coupled to the first clock pre-decoder circuitry and the first set of repeater circuitry, and is configured to generate the first set of word line signals in response to the first set of clock signals, the first set of local pre-decoder signals, and the second set of local pre-decoder signals; and The first set of memory cells is coupled to the decoder circuit after the first set of word lines and is configured to store the first set of data in response to at least the first set of word line signals.

2. The memory circuit according to claim 1, further comprising: The second set of word line decoder circuits is coupled to the first clock pre-decoder circuit and the first set of repeater circuits, and is configured to generate the second set of word line signals in response to the second set of clock signals, the first set of local pre-decoder signals and the second set of local pre-decoder signals.

3. The memory circuit according to claim 2 further includes: The second set of memory cells is coupled to the decoder circuit after the second set of word lines and is configured to store the second set of data at least in response to the second set of word line signals.

4. The memory circuit according to claim 3 further includes: A first word line driver circuit, the first word line driver circuit comprising: The decoder circuit after the first group of word lines; and The second set of repeater circuits is coupled between the output of the first set of repeater circuits and the first set of word-line decoder circuits; and The second word line driver circuit includes: The second set of word lines followed by the decoder circuit; and The third set of repeater circuits is coupled between the output of the first set of repeater circuits and the second set of word line decoder circuits.

5. The memory circuit according to claim 1, wherein, The first group of repeater circuits includes: A first set of buffers, each buffer in the first set of buffers being configured to generate a corresponding signal for the first set of local pre-decoder signals in response to a corresponding signal for the first set of global pre-decoder signals; and The second set of buffers, each of which is configured to generate a corresponding signal for the second set of local predecoder signals in response to a corresponding signal for the second set of global predecoder signals.

6. The memory circuit according to claim 1, wherein, The first group of repeater circuits includes: A first set of inverters, each inverter in the first set of inverters being configured to generate a corresponding signal of the first set of local pre-decoder signals in response to a corresponding signal of the first set of global pre-decoder signals; and The second set of inverters, each of which is configured to generate a corresponding signal for the second set of local predecoder signals in response to a corresponding signal for the second set of global predecoder signals.

7. The memory circuit according to claim 1, further comprising: A first global pre-decoder line extends at least in a first direction, overlaps at least with the first local control circuit, is coupled to the global control circuit and the first set of repeater circuits, and is configured to provide the first set of global pre-decoder signals. The second global pre-decoder line extends at least in the first direction, overlaps at least with the first local control circuit, is coupled to the global control circuit and the first set of repeater circuits, and is configured to provide the second set of global pre-decoder signals. A first local pre-decoder line extends at least in the first direction, overlaps at least with the first local control circuit, is coupled to the first set of repeater circuits, and is configured to provide the first set of local pre-decoder signals. as well as The second local pre-decoder line extends at least in the first direction, overlaps at least with the first local control circuit, is coupled to the first set of repeater circuits, and is configured to provide the second set of local pre-decoder signals.

8. The memory circuit according to claim 7, wherein, The first global pre-decoder line is located on the first metal layer; The second global pre-decoder line is located on the first metal layer; The first local pre-decoder line is located on a second metal layer, different from the first metal layer; and The second local pre-decoder line is located on the second metal layer.

9. The memory circuit according to claim 8, wherein, The first metal layer corresponds to the second metal layer; and The second metal layer corresponds to the fourth metal layer.

10. The memory circuit according to claim 7, wherein, The first global predecoder line has a first width in a second direction different from the first direction; The second global predecoder line has a first width in the second direction; The first local pre-decoder line has a second width in the second direction, the second width being smaller than the first width; and The second local pre-decoder line has a second width in the second direction.

11. A memory circuit, comprising: The global control circuit is configured to generate a first set of global pre-decoder signals, a second set of global pre-decoder signals, and a first set of local address signals in response to a memory address signal and a first clock signal. A first local control circuit is coupled to the global control circuit, the first local control circuit comprising: A first clock pre-decoder circuit, coupled to the global control circuit, is configured to generate a first set of clock signals and a second set of clock signals in response to the first set of local address signals and the first clock signal; and A first word line driver circuit, the first word line driver circuit comprising: The first set of repeater circuits is configured to generate a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and to generate a second set of local pre-decoder signals in response to the second set of global pre-decoder signals; and The first set of word line decoder circuitry is coupled to the first clock pre-decoder circuitry and the first set of repeater circuitry, and is configured to generate the first set of word line signals in response to the first set of clock signals, the first set of local pre-decoder signals, and the second set of local pre-decoder signals; and The first set of memory cells is coupled to the decoder circuit after the first set of word lines and is configured to store the first set of data in response to at least the first set of word line signals.

12. The memory circuit according to claim 11, further comprising: The second word line driver circuit includes: The second set of repeater circuits is configured to generate the first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and to generate the second set of local pre-decoder signals in response to the second set of global pre-decoder signals; and The second set of word line decoder circuits is coupled to the first set of clock pre-decoder circuits and the second set of repeater circuits, and is configured to generate the second set of word line signals in response to the second set of clock signals, the first set of local pre-decoder signals and the second set of local pre-decoder signals.

13. The memory circuit according to claim 12, further comprising: The second set of memory cells is coupled to the decoder circuit after the second set of word lines and is configured to store the second set of data at least in response to the second set of word line signals.

14. The memory circuit according to claim 12, wherein, At least one of the first group of repeater circuits or the second group of repeater circuits includes: A first set of buffers, each buffer in the first set of buffers being configured to generate a corresponding signal for the first set of local pre-decoder signals in response to a corresponding signal for the first set of global pre-decoder signals; and The second set of buffers, each of which is configured to generate a corresponding signal for the second set of local predecoder signals in response to a corresponding signal for the second set of global predecoder signals.

15. The memory circuit according to claim 12, wherein, At least one of the first group of repeater circuits or the second group of repeater circuits includes: A first set of inverters, each inverter in the first set of inverters being configured to generate a corresponding signal of the first set of local pre-decoder signals in response to a corresponding signal of the first set of global pre-decoder signals; and The second set of inverters, each of which is configured to generate a corresponding signal for the second set of local predecoder signals in response to a corresponding signal for the second set of global predecoder signals.

16. The memory circuit according to claim 11, wherein, The global control circuit includes: A clock gating circuit is configured to generate the first clock signal in response to a second clock signal and a chip enable signal; The address latch circuit is configured to generate a first set of local address signals, a second set of local address signals, and a third set of local address signals in response to the memory address signal. A first pre-decoder circuit, coupled to the address latch circuit, and configured to generate the first set of global pre-decoder signals at least in response to the second set of local address signals or an inverted second set of local address signals; and The second pre-decoder circuit is coupled to the address latch circuit and is configured to generate the second set of global pre-decoder signals in response to at least the third set of local address signals or the inverted third set of local address signals.

17. The memory circuit according to claim 16, wherein, The first clock pre-decoder circuit includes: The first set of AND logic gates is configured to generate a first set of signals in response to the first set of local address signals and the inverted first set of local address signals. The second set of AND logic gates is configured to generate the second set of signals in response to the first set of local address signals and the inverted first set of local address signals. The third set of AND logic gates is configured to generate a first set of body selection signals in response to the first set of local address signals and the inverted first set of local address signals. A fourth set of AND gates, coupled to the first set of AND gates and the third set of AND gates, and configured to generate the first set of clock signals in response to the first set of signals and the first set of body select signals; and The fifth AND gate is coupled to the second AND gate and the third AND gate, and is configured to generate the second clock signal in response to the second group signal and the first group body select signal.

18. The memory circuit according to claim 16, wherein, Each post-word-line decoder circuit in the first group of post-word-line decoder circuits includes: The first set of AND logic gates is configured to generate a first set of signals in response to one of the first set of local pre-decoder signals, one of the second set of local pre-decoder signals, and one of the first set of clock signals or the second set of clock signals; and The first set of inverters is coupled to the first set of AND logic gates and is configured to generate the first set of word line signals in response to the first set of signals, the first set of signals being inverted from the first set of word line signals.

19. A method of operating a memory circuit, the method comprising: The global control circuit generates a first set of global pre-decoder signals, a second set of global pre-decoder signals, and a first set of local address signals in response to the memory address signal and the first clock signal. The first clock pre-decoder circuit generates a first set of clock signals and a second set of clock signals in response to the first set of local address signals and the first clock signal. The first clock pre-decoder circuit is coupled to the global control circuit. The first set of repeater circuits generates a first set of local pre-decoder signals in response to the first set of global pre-decoder signals, and generates a second set of local pre-decoder signals in response to the second set of global pre-decoder signals. The first set of word line decoder circuit generates the first set of word line signals in response to the first set of clock signals, the first set of local pre-decoder signals and the second set of local pre-decoder signals. The first set of word line decoder circuit is coupled to the first clock pre-decoder circuit and the first set of repeater circuits. as well as At least in response to the first set of word line signals, the first set of data is stored in the first set of memory cells, which are coupled to the decoder circuit after the first set of word lines.

20. The method of claim 19, further comprising: The second set of word line decoder circuit generates a second set of word line signals in response to the second set of clock signals, the first set of local pre-decoder signals, and the second set of local pre-decoder signals. The second set of word line decoder circuit is coupled to the first clock pre-decoder circuit and the first set of repeater circuits. as well as At least in response to the second set of word line signals, the second set of data is stored in the second set of memory cells, which are coupled to the decoder circuit after the second set of word lines.

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