Switching circuit control method, control circuit, and switching circuit

Abstract

The present invention discloses a control method, control circuit, and switching circuit for a switching circuit. The method obtains an upper limit reference signal based on a compensation signal, and obtains a lower limit reference signal for the inductor current based on the compensation signal and a ramp signal. The lower limit reference signal includes a DC voltage portion and a ramp portion, and the ramp portion begins to rise with the DC voltage portion as a starting point. During the off-state of the main switch, a current detection signal representing the inductor current is obtained. When the current detection signal drops to the smaller value of the ramp portion of the lower limit reference signal or the upper limit reference signal, the main switch is controlled to turn on. The present invention can automatically extend the off-state time of the main switch to support small duty cycles and reduce output voltage overshoot during large load transitions.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and in particular to a control method for a switching circuit, a control circuit, and a switching circuit. Background Art

[0002] In existing switching circuit control strategies, upper and lower inductor current reference signals are set. The main switch is controlled by comparing the inductor current detection with the upper and lower reference signals to turn the main switch on and off. In some cases, such as low-duty-cycle applications, if the input voltage is too high, the output voltage will be too high even if the switching circuit is operating at its minimum on-time, resulting in an output voltage that does not meet the required output. Summary of the Invention

[0003] The object of the present invention is to provide a control circuit, a control method and a switch circuit of a switch circuit, which can promptly extend the turn-off time of the main switch tube when the input voltage is large so that the output voltage meets the demand.

[0004] To achieve the above object, the present invention provides a switching circuit and a control method for the switching circuit, wherein the switching circuit includes an inductor and a main switching tube connected to the inductor.

[0005] Obtaining the upper limit reference signal according to the compensation signal;

[0006] obtaining a lower limit reference signal of the inductor current according to the compensation signal and the ramp signal, wherein the lower limit reference signal includes a DC voltage portion and a ramp portion, and the ramp portion starts to rise with the DC voltage portion as a starting point value;

[0007] A current detection signal representing the inductor current is obtained during the off period of the main switch tube. When the current detection signal drops to a smaller value between the slope part of the lower limit reference signal and the upper limit reference signal, the main switch tube is controlled to be turned on.

[0008] Optionally, a smaller value between the lower limit reference signal and the upper limit reference signal is selected, the current detection signal is compared with the smaller value between the lower limit reference signal and the upper limit reference signal, and the main switch tube is controlled to turn on when the current detection signal drops to the smaller value.

[0009] Optionally, when the slope peak value of the lower limit reference signal is greater than or equal to the upper limit reference signal, the slope peak value of the lower limit reference signal is clamped to the upper limit reference signal;

[0010] The current detection signal is compared with the clamped lower limit reference signal, and when the current detection signal falls below the lower limit reference signal, the main switch tube is controlled to be turned on.

[0011] Optionally, the current detection signal is compared with the lower limit reference signal and the upper limit reference signal respectively; when the current detection signal drops to the slope part of the lower limit reference signal and the current detection signal drops to the upper limit reference signal, the main switch tube is controlled to be turned on.

[0012] Optionally, the value of the upper limit reference signal is less than or equal to the slope peak value of the lower limit reference signal.

[0013] Optionally, a DC voltage portion of the lower limit reference signal is obtained according to a difference between the upper limit reference signal and a bias voltage;

[0014] In a switching cycle, when the set clock signal is valid, the ramp signal is generated with a predetermined slope, and the ramp signal rises from the starting value to obtain the ramp portion of the lower limit reference signal.

[0015] Optionally, a first current signal representing the inductor current is obtained during the conduction period of the main switch tube, and the first current signal is compared with the upper limit reference signal. When the first current signal rises to the upper limit reference signal, if the conduction time of the main switch tube is greater than the preset minimum conduction time, the main switch tube is controlled to be turned off.

[0016] The present invention also provides a control circuit for a switch circuit, comprising

[0017] a reference signal obtaining circuit for setting an upper limit reference signal of the inductor current according to the compensation signal, and obtaining a lower limit reference signal according to the compensation signal and the ramp signal, wherein the lower limit reference signal includes a DC voltage portion and a ramp portion, and the ramp portion begins to rise with the DC voltage portion as a starting point value;

[0018] an inductor current acquisition circuit for acquiring a first current signal representing the inductor current during the on-state of the main switch tube and for sampling the inductor current to obtain a current detection signal during the off-state of the main switch tube;

[0019] an on-time control circuit, which compares the first current signal with the upper limit reference signal, and controls the main switch to be turned off when the first current signal rises to the upper limit reference signal and the on-time of the main switch is greater than the minimum on-time;

[0020] The off-time control circuit receives the lower limit reference signal and the upper limit reference signal, and controls the main switch tube to turn on when the current detection signal drops to the smaller value of the slope part of the lower limit reference signal and the upper limit reference signal.

[0021] Optionally, the on-time control circuit includes a timer and a first comparator. When the main switch tube is turned on, the timer starts timing, and the first comparator compares the first current signal with the upper limit reference signal. When the first current signal drops and reaches the upper limit reference signal, if the timing time of the timer is greater than the minimum on-time, the main switch tube is controlled to be turned on.

[0022] Optionally, the turn-off time control circuit includes a second comparator and a third comparator, the second comparator compares the current detection signal with the lower limit reference signal, and the third comparator compares the current detection signal with the upper limit reference signal. When the current detection signal drops to the slope part of the lower limit reference signal and the current detection signal drops to the upper limit reference signal, the main switch tube is controlled to turn on, and the value of the upper limit reference signal is less than or equal to the slope peak value of the lower limit reference signal.

[0023] Optionally, the off-time control circuit includes a comparison selection circuit and a fourth comparator, wherein the comparison selection circuit compares the upper limit reference signal with the lower limit reference signal and selects the smaller value; the fourth comparator compares the current detection signal with the output result of the comparison selection circuit, and when the current detection signal drops to the output result of the comparison selection circuit, controls the main switch tube to turn on.

[0024] Optionally, the turn-off time control circuit includes a fifth comparator and a clamping circuit. When the slope peak value of the lower limit reference signal is greater than or equal to the upper limit reference signal, the clamping circuit clamps the slope peak value of the lower limit reference signal to the upper limit reference signal; the fifth comparator compares the current detection signal with the clamped lower limit reference signal, and when the current detection signal drops to the lower limit reference signal, controls the main switch tube to turn on.

[0025] Optionally, the reference signal acquisition circuit includes an upper limit reference signal acquisition circuit, which obtains the upper limit reference signal based on the compensation signal; and also includes a lower limit reference signal generation circuit, which obtains the DC voltage portion of the lower limit reference signal based on the difference between the upper limit reference signal and the bias voltage. In a switching cycle, when the set clock signal is valid, the ramp signal is generated with a predetermined slope, and the ramp signal rises from the starting value to obtain the slope portion of the lower limit reference signal.

[0026] The present invention also provides a switching circuit, which is an N-phase switching circuit. Each phase switching circuit includes a corresponding inductor and a main switch tube connected to the inductor. For each phase switching circuit, it includes any one of the control circuits described above.

[0027] Compared with the prior art, the technical solution of the present invention has the following advantages: when the compensation voltage is very small and the upper limit reference signal is very small, the main switch tube operates at the minimum on-time and automatically extends the off-time of the main switch tube to support a small duty cycle. At the same time, it can reduce the output voltage overshoot during a large load jump, so that the output voltage can meet the demand. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a working waveform diagram of the switching circuit of the present invention;

[0029] Figure 2 This is another working waveform diagram of the switching circuit of the present invention;

[0030] Figure 3 This is a control block diagram of the switch circuit of the present invention;

[0031] Figure 4 This is a schematic diagram of a circuit for generating a lower limit reference signal according to the present invention;

[0032] Figure 5 This is a schematic diagram of the on-time control circuit of the present invention;

[0033] Figure 6 This is a schematic diagram of a first embodiment of an off-time control circuit of the present invention;

[0034] Figure 7 This is a schematic diagram of a second embodiment of the off-time control circuit of the present invention;

[0035] Figure 8 This is a schematic diagram of a third embodiment of the off-time control circuit of the present invention. DETAILED DESCRIPTION

[0036] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments and covers any substitution, modification, equivalent method and solution made within the spirit and scope of the present invention.

[0037] In order to make the public have a thorough understanding of the present invention, specific details are described in detail in the following preferred embodiments of the present invention, but those skilled in the art can also fully understand the present invention without description of these details.

[0038] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the drawings are simplified and not to exact proportions, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0039] like Figure 1 、 2As shown in the figure, the working waveform of the switching circuit of the present invention is illustrated. The VC1 waveform is the compensation signal waveform. When the main switch tube is turned on, a current detection signal representing the inductor current is obtained. The current detection signal is an inductor current reconstruction signal obtained by reconstructing the inductor current or a current detection signal obtained by sampling the inductor current. The rising slope of the inductor current reconstruction signal is obtained according to the inductor value and the input voltage and / or the output voltage. When the main switch tube is turned off, the inductor current signal is sampled to obtain the inductor current detection signal. Corresponding to the IL waveform in the figure, the compensation signal is set to the upper limit reference signal VC1, wherein the compensation signal is obtained by error amplification of the output voltage feedback signal of the switching circuit and the reference signal representing the output expected value. The lower limit reference signal is set to VC2. VC2 is obtained by subtracting the bias voltage from the compensation signal and superimposing the ramp signal. The compensation signal subtracting the bias voltage is the starting value of the lower limit reference signal. Figure 1 and 2 As shown, the lower limit reference signal includes a DC voltage portion and a ramp portion. When the clock signal CLK is active, the lower limit reference signal VC2 begins to rise from its starting value. Under normal output conditions, when the inductor current reconstruction signal rises to the upper limit reference signal VC1, the main switch is turned off. When the inductor current detection signal falls to the lower limit reference signal VC2, the main switch is turned on. When the output is too high, the compensation signal VC1 becomes very small, which means that the upper limit reference signal VC1 decreases accordingly. The upper limit reference signal may reach the upper limit reference signal immediately after the main switch turns on. In this case, to ensure normal circuit operation, the main switch is controlled to the minimum on-time Ton_min.

[0040] In the embodiment of the present invention, when the inductor current detection signal drops to a smaller value of the slope of the upper limit reference signal VC1 or the slope of the lower limit reference signal VC2 , the main switch is turned on.

[0041] For example, Figure 1 As shown, after the main switch is turned off, the inductor current begins to decrease. The inductor current detection signal is compared with the lower limit reference signal VC2 and the upper limit reference signal VC1, respectively. When the inductor current detection signal reaches the slope portion of the lower limit reference signal VC2 but has not yet reached the upper limit reference signal VC1, the main switch remains off until the inductor current detection signal reaches the upper limit reference signal VC1, at which time the main switch is turned on.

[0042] For example, Figure 2 FIG. 1 shows another operating waveform diagram of the present invention. After the main switch is turned off, the inductor current decreases. The lower limit reference signal VC2 is compared with the upper limit reference signal VC1. When the slope of the lower limit reference signal reaches the upper limit reference signal, the slope peak of the lower limit reference signal is clamped to the upper limit reference signal. When the current detection signal reaches the slope peak of the lower limit reference signal, the main switch is turned on.

[0043] When the upper limit reference signal is small and the main switch is operating at its minimum on-time, the present invention controls the on-time of the main switch not only based on the lower limit reference signal VC2 but also based on the upper limit reference signal VC1. The smaller the upper limit reference signal VC1, the less output compensation is required, the longer the off-time of the main switch is, and the lower the switching frequency is, thereby stabilizing the output of the switching circuit and meeting requirements. After the compensation signal changes, i.e., after the upper limit reference signal changes, the lower limit reference signal also changes accordingly. Since the output voltage remains virtually unchanged, even if ripple is generated in the output voltage during a load change, the percentage of change is very small, and therefore the maximum deviation between the upper limit reference signal and the lower limit reference signal remains virtually unchanged.

[0044] like Figure 3 FIG. 1 shows a control block diagram of a switching circuit according to the present invention, comprising an inductor current acquisition circuit 01, a reference signal generation circuit 02, an on-time control circuit 03, and an off-time control circuit 04. The inductor current acquisition circuit 01 acquires a first current signal representing the inductor current during the on-time period of the main switch, and samples the inductor current to obtain a current detection signal during the off-time period of the main switch. The reference signal generation circuit 02 acquires an upper limit reference signal based on a compensation signal VC1. In one embodiment, the compensation signal VC1 can be used as the upper limit reference signal VC1. The circuit also includes a lower limit reference signal generation circuit that acquires a lower limit reference signal VC2 based on the compensation signal VC1 and a ramp signal. The on-time control circuit 03 compares the first current signal with the upper limit reference signal VC1. When the first current signal is greater than or equal to the upper limit reference signal VC1, the main switch is turned on, and the on-time of the main switch is now greater than the minimum on-time Ton_min. The off-time control circuit 04 receives the lower limit reference signal VC2 and the upper limit reference signal VC1 and compares them with the current detection signal in the manner described above to control the main switch to turn on.

[0045] like Figure 4 As shown, a schematic diagram of a lower limit reference signal generating circuit is shown, which includes a bias voltage generating circuit 201, a subtractor 202, and a ramp signal generating circuit 203. The bias voltage generating circuit obtains a bias voltage according to the inductance value, input voltage or / and output voltage, and switching period of the switching circuit. The subtractor 202 subtracts the compensation signal VC1 from the bias voltage to obtain the initial value of the lower limit reference signal. The ramp signal generating circuit 203 generates a ramp signal when the clock signal is valid. The ramp signal rises from the initial value to obtain the lower limit reference signal VC2. The slope of the ramp signal is obtained according to the inductance value and the input voltage or / and output voltage. The slope of the ramp signal can also be adjusted according to actual needs.

[0046] like Figure 5As shown, a schematic diagram of the conduction time control circuit of the present invention is shown, which includes a timer 301, a first comparator 302 and a drive circuit 303. The first comparator 302 compares the upper limit reference signal with the first current signal. The timer 301 receives the comparison result of the first comparator 302 and starts timing when the main switch tube is turned on. When the comparison result indicates that the first current signal reaches the upper limit reference signal, it is checked whether the reached timing time is greater than the minimum conduction time. If so, the main switch tube is controlled to be turned off through the drive circuit 303. If not, the main switch tube is controlled to be turned off when the minimum conduction time is reached.

[0047] like Figure 6 The figure shows a schematic diagram of a first embodiment of the off-time control circuit of the present invention, comprising a second comparator 401, a third comparator 402, and a driver circuit 403. The second comparator 401 compares the current detection signal with a lower-limit reference signal VC2, while the third comparator compares the current detection signal with an upper-limit reference signal VC1. If the current detection signal reaches the slope of the lower-limit reference signal VC2 but does not reach the upper-limit reference signal VC1, the main switch remains off until the current detection signal reaches the upper-limit reference signal VC1, at which point the main switch is turned on. Specifically, the main switch is turned on when the current detection signal drops to the smaller of the slope of the upper-limit reference signal VC1 and the lower-limit reference signal VC2. This embodiment requires only two comparators, and through direct comparison between the comparators, the off-time of the main switch can be extended when the compensation signal is small.

[0048] like Figure 7 The figure shows a schematic diagram of a second embodiment of the off-time control circuit of the present invention, comprising a comparison and selection circuit 501, a fourth comparator 502, and a drive circuit 503. The comparison and selection circuit 501 compares the upper limit reference signal VC1 with the lower limit reference signal VC2 and selects the smaller value. The fourth comparator 502 compares the current detection signal with the output result of the comparison and selection circuit 501. The drive circuit 503 receives the comparison result of the fourth comparator 502 and controls the main switch to conduct when the current detection signal is less than or equal to the output result of the comparison and selection circuit. This embodiment requires first comparing the upper limit reference signal and the lower limit reference signal through a comparator, and then selecting one of the two signals to compare with the current detection signal. Compared with the first embodiment, this embodiment includes an additional signal selection process.

[0049] like Figure 8The figure shows a schematic diagram of a third embodiment of the off-time control circuit of the present invention, comprising a clamping circuit 601, a fifth comparator 602, and a driving circuit 603. When the lower limit reference signal VC2 is greater than or equal to the upper limit reference signal VC1, the clamping circuit 601 clamps the lower limit reference signal to the upper limit reference signal VC1. The fifth comparator 602 compares the current detection signal with the clamped lower limit reference signal VC2. The driving circuit 603 receives the comparison result of the sixth comparator 603 and controls the main switch to conduct when the current detection signal is less than or equal to the lower limit reference signal VC2. Compared to the first and second embodiments, this embodiment includes an additional clamping circuit. When the compensation signal is small, the peak value of the lower limit reference signal is limited. When the main switch is turned on, the lower limit reference signal is automatically reset to the starting value, preventing the peak value of the slope portion of the lower limit reference signal from rising too much.

[0050] The switching circuit in the present application can be a multi-phase switching circuit, specifically a multi-phase buck circuit, wherein each phase buck switching circuit includes a main switch tube, a freewheeling switch tube, and an inductor, and each phase inductor is connected to a common connection point of the main switch tube and the freewheeling switch tube, and each phase switching circuit includes a Figure 3 The control circuit shown is used to control the corresponding switch tube.

[0051] In addition, although the embodiments are described and illustrated separately above, some common technologies are involved. It is the opinion of ordinary technicians in this field that they can be replaced and integrated between the embodiments. For content that is not clearly recorded in one of the embodiments, reference can be made to another recorded embodiment.

[0052] The above-described embodiments do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the above-described embodiments shall be included in the scope of protection of this technical solution.

Claims

1. A method for controlling a switching circuit, wherein the switching circuit includes an inductor and a main switching transistor connected to the inductor, characterized in that: obtaining an upper limit reference signal according to the compensation signal; obtaining a lower limit reference signal of the inductor current according to the compensation signal and the ramp signal, wherein the lower limit reference signal includes a DC voltage portion and a ramp portion, and the ramp portion starts to rise with the DC voltage portion as a starting value; performing error amplification on an output voltage feedback signal of the switching circuit and a reference signal representing an expected output value to obtain the compensation signal, setting the compensation signal as the upper limit reference signal, subtracting a bias voltage from the compensation signal and then superimposing the ramp signal to obtain the lower limit reference signal, and subtracting the bias voltage from the compensation signal to obtain the starting value; A current detection signal representing the inductor current is obtained during the off period of the main switch tube. When the current detection signal drops to a smaller value between the slope part of the lower limit reference signal and the upper limit reference signal, the main switch tube is controlled to be turned on.

2. The control method according to claim 1, wherein: The smaller value of the limit reference signal and the upper limit reference signal is selected, the current detection signal is compared with the smaller value of the lower limit reference signal and the upper limit reference signal, and the main switch tube is controlled to be turned on when the current detection signal drops to the smaller value.

3. The control method according to claim 1, wherein: When the slope peak value of the lower limit reference signal is greater than or equal to the upper limit reference signal, clamping the slope peak value of the lower limit reference signal to the upper limit reference signal; The current detection signal is compared with the clamped lower limit reference signal, and when the current detection signal falls below the lower limit reference signal, the main switch tube is controlled to be turned on.

4. The control method according to claim 1, wherein: The current detection signal is compared with the lower limit reference signal and the upper limit reference signal respectively. When the current detection signal drops to the slope part of the lower limit reference signal and the current detection signal drops to the upper limit reference signal, the main switch tube is controlled to be turned on.

5. The control method according to claim 4, characterized in that: The value of the upper limit reference signal is less than or equal to the slope peak value of the lower limit reference signal.

6. The control method according to claim 1, wherein: Obtaining a DC voltage portion of the lower limit reference signal according to a difference between the upper limit reference signal and a bias voltage; In a switching cycle, when the set clock signal is valid, the ramp signal is generated with a predetermined slope, and the ramp signal rises from a starting value to obtain the ramp portion of the lower limit reference signal.

7. The control method according to claim 1, wherein: A first current signal representing the inductor current is obtained during the on-time of the main switch, and the first current signal is compared with the upper limit reference signal. When the first current signal rises to the upper limit reference signal, if the on-time of the main switch is greater than a preset minimum on-time, the main switch is controlled to be turned off.

8. A control circuit for a switch circuit, characterized in that: include, a reference signal acquisition circuit, configured to set an upper limit reference signal for the inductor current based on the compensation signal, and to obtain a lower limit reference signal based on the compensation signal and a ramp signal, wherein the lower limit reference signal includes a DC voltage portion and a ramp portion, and the ramp portion begins to rise with the DC voltage portion as a starting value. The compensation signal is obtained by performing error amplification on an output voltage feedback signal of the switching circuit and a reference signal representing an output expected value, and the compensation signal is set as the upper limit reference signal. The lower limit reference signal is obtained by subtracting a bias voltage from the compensation signal and then superimposing the resultant signal on the ramp signal, and the starting value is obtained by subtracting the bias voltage from the compensation signal; an inductor current acquisition circuit for acquiring a first current signal representing the inductor current during the on-state of the main switch tube and for sampling the inductor current to obtain a current detection signal during the off-state of the main switch tube; an on-time control circuit, which compares the first current signal with the upper limit reference signal, and controls the main switch to be turned off when the first current signal rises to the upper limit reference signal and the on-time of the main switch is greater than the minimum on-time; The off-time control circuit receives the lower limit reference signal and the upper limit reference signal, and controls the main switch tube to turn on when the current detection signal drops to the smaller value of the slope part of the lower limit reference signal and the upper limit reference signal.

9. The control circuit according to claim 8, wherein: The on-time control circuit includes a timer and a first comparator. When the main switch tube is turned on, the timer starts timing. The first comparator compares the first current signal with the upper limit reference signal. When the first current signal drops and reaches the upper limit reference signal, if the timing time of the timer is greater than the minimum on-time, the main switch tube is controlled to be turned on.

10. The control circuit according to claim 8, wherein: The off-time control circuit includes a second comparator and a third comparator. The second comparator compares the current detection signal with the lower limit reference signal, and the third comparator compares the current detection signal with the upper limit reference signal. When the current detection signal drops to the slope portion of the lower limit reference signal and the current detection signal drops to the upper limit reference signal, the main switch tube is controlled to be turned on, and the value of the upper limit reference signal is less than or equal to the slope peak value of the lower limit reference signal.

11. The control circuit according to claim 8, wherein: The off-time control circuit includes a comparison and selection circuit and a fourth comparator, wherein the comparison and selection circuit compares the upper limit reference signal and the lower limit reference signal and selects the smaller value thereof; The fourth comparator compares the current detection signal with the output result of the comparison selection circuit, and controls the main switch tube to be turned on when the current detection signal drops below the output result of the comparison selection circuit.

12. The control circuit according to claim 8, wherein: The off-time control circuit includes a fifth comparator and a clamping circuit. When the slope peak value of the lower limit reference signal is greater than or equal to the upper limit reference signal, the clamping circuit clamps the slope peak value of the lower limit reference signal to the upper limit reference signal. The fifth comparator compares the current detection signal with the clamped lower limit reference signal, and controls the main switch to be turned on when the current detection signal drops below the lower limit reference signal.

13. The control circuit according to claim 8, wherein: The reference letter The signal acquisition circuit includes an upper limit reference signal acquisition circuit, which obtains the upper limit reference signal according to the compensation signal; and also includes a lower limit reference signal generation circuit, which obtains the DC voltage portion of the lower limit reference signal according to the difference between the upper limit reference signal and the bias voltage. In a switching cycle, when the set clock signal is valid, the ramp signal is generated with a predetermined slope, and the ramp signal rises from the starting value to obtain the slope portion of the lower limit reference signal.

14. A switching circuit, comprising an N-phase switching circuit, wherein each phase of the switching circuit comprises a corresponding inductor and a main switching tube connected to the inductor, characterized in that: Each phase switching circuit comprises a control circuit according to any one of claims 8 to 13.

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