A duty cycle adjustable programmable frequency divider

Abstract

The application discloses a duty cycle adjustable programmable frequency divider, which comprises a plurality of frequency division units cell1, cell2, cell3-cell n and a programmable logic control module MUX, the frequency division units cell1, cell2 and cell3 are different frequency division units, the frequency division units cell3-cell n are the same frequency division units, the output of the programmable logic control module MUX is connected with the setting number end of the frequency division units cell2-cell n , and the programmable frequency division ratio is realized through the programmable logic control module MUX. The application is improved on the basis of the traditional 2 / 3 frequency division unit cascade, mainly adopts the common flip-flop structure, basic logic gate structure and selector, the interaction between various modules is simple, and the flexibility and reusability of the circuit are ensured.

Description

Technical Field

[0001] This invention relates to the field of frequency divider integrated circuit technology, and more particularly to a programmable frequency divider with adjustable duty cycle. Background Technology

[0002] With the rapid development of modern communication and semiconductor technologies, system operating clock frequencies are increasing, and the requirements for input clock signals in sampling and reference circuits are becoming increasingly stringent. Phase-locked loop (PLL)-based frequency synthesizers, as key modules in RF transceivers, generate high-quality, high-precision, adjustable local oscillator signals to achieve signal modulation and demodulation. Programmable frequency dividers, as important modules of PLL frequency synthesizers, have a significant impact on the entire system's functionality and performance.

[0003] like Figure 2 As shown, Figure 2 This diagram illustrates the structure of a cascaded 2 / 3 divider programmable frequency divider. This structure consists of several cascaded 2 / 3 divider units. The output of each 2 / 3 divider unit serves as the input to the next stage. The mod control signal output of each stage (except the first stage) is fed back to the previous stage. The mod control signal of the last stage is connected to a high level. The output of the mod control signal of each stage is passed to the next stage and back along the divider link, synchronized with the operating clock of the previous stage during transmission. Internally, its structure is uniformly composed of identical 2 / 3 divider modules, exhibiting high modularity and strong reusability.

[0004] The working principle is as follows: when the programmable control bits P and Mod... in When all bits are high, the 2 / 3 divider unit performs a 3-fold frequency division; otherwise, it performs a 2-fold frequency division. When programmable control bits P0~P... n-1 All values ​​are 0. At this point, each 2 / 3 divider unit performs a 2-divide, resulting in a total division ratio of 2. n When only P0 is 1 and all other programmable control bits are 0, the first-stage 2 / 3 divider unit will perform a 3-division operation and swallow a pulse once within the division cycle. Other stages of the 2 / 3 divider unit will perform a 2-division operation. Therefore, the division ratio for this division cycle is 2. n +1; when only P1 is 1, P0 and P2 ~ P n-1 When both are 0, the second-stage 2 / 3 divider will perform a 3-division operation, and only one pulse swallowing operation will occur within this division cycle. Therefore, this pulse swallowing operation by the second-stage 2 / 3 divider is equivalent to one additional 2-division operation for the total input loss. Thus, the division ratio for this division cycle is 2. n +2; and so on, the total frequency division ratio DX achieved by this structure can be obtained as:

[0005] D x =P0+2·P1+2 2 ·P2+…+2n-1 ·P n-1 +2 n

[0006] When P0 and P n-1 When all values ​​are 1, the frequency division ratio is at its maximum, which is 2. n+1 -1; when P0 and P n-1 When all values ​​are 0, the frequency division ratio is at its minimum, which is 2. n Therefore, the frequency division ratio range that this structure can achieve is (2... n ,2 n+1 -1), it can be seen that the frequency division ratio range that this structure can achieve is relatively narrow, and the maximum frequency division ratio that can be achieved is about twice the minimum frequency division ratio.

[0007] like Figure 3 As shown, Figure 3 This is a 2 / 3 divider module with an input terminal f. in Signal output terminal f out Mode control signal input terminal mod in Mode control signal output terminal mod out The upper part is the basic 2 / 3 frequency divider, and the lower part is the frequency divider mode control logic, which contains a total of 4 D latches and 3 two-input AND gates. The working principle is that when mod... in When both the preset input P and the preset input P are high, the output clock signal f is activated. out To achieve the input signal f in Perform three-way frequency division function; when mod in When P is low, the cycle termination logic is masked, and the output f is... out It enables the function of dividing the input signal by two.

[0008] Traditional 2 / 3 programmable frequency dividers can cover small division ratios, and each division unit is the same and independent, with high modularity and good reusability. However, the division ratio range that this type of frequency divider can achieve is narrow, and the maximum division ratio that can be achieved is about twice the minimum division ratio. Summary of the Invention

[0009] The purpose of this invention is to provide a programmable frequency divider with adjustable duty cycle to solve the technical problem that the frequency division ratio range achievable by existing frequency dividers is relatively narrow.

[0010] The objective of this invention is achieved through the following technical solution: a programmable frequency divider with adjustable duty cycle, comprising multiple cascaded frequency divider units cell1, cell2, cell3, and cell4. n And a programmable logic control module (MUX), wherein the frequency division units cell1, cell2, and cell3 are different frequency division units, and the frequency division units cell3 to cell4 are... nUsing the same frequency divider unit, the output of frequency divider unit cell2 is connected to one input terminal of frequency divider unit cell3, and frequency divider units cell3~cell3 n The output of cell2 is logically ANDed with the output of the previous frequency divider unit, and then connected to one input of the next frequency divider unit. n Each of its output terminals is also connected to its other input terminal, from the last stage frequency divider cell. n Starting from the beginning, sequentially divide the frequency division units cell2 to cell3. n The output groups are connected to multiple cascaded three-input AND gates. The output of the last three-input AND gate is connected to one input of each frequency divider unit. The first output of frequency divider unit cell1 is connected to its other input, and the second output is connected to the input of the programmable logic controller (MUX). The output of the MUX is connected to frequency divider units cell2 through cell3. n The preset terminal is connected, and the arbitrary programmable frequency division ratio is realized through the programmable logic control module MUX.

[0011] Furthermore, the input terminals of the frequency division unit cell1, the last stage three-input AND gate, and the programmable logic control module MUX are all connected to the synchronization signal SYNC.

[0012] Furthermore, select the frequency division units cell3 to cell4 based on the required maximum frequency division ratio. n The number of.

[0013] Furthermore, the frequency division ratio is determined by the values ​​of HC and LC, where LC = number of low cycles - 1; HC = number of high cycles - 1, and the values ​​of HC and LC range from [0, 15].

[0014] Furthermore, when the frequency divider is bypassed, the division ratio is 1; otherwise, the division ratio is HC + LC + 2.

[0015] Furthermore, the duty cycle of the output signal of the programmable frequency divider is: (HC+1) / (HC+LC+2).

[0016] Furthermore, the frequency divider cell 1 includes a D flip-flop 1, an XOR gate 1, and a buffer. The input of the D flip-flop 1 is connected to the XOR gate 1, and the input of the D flip-flop 1 is also connected to an external clock CLKin. The output is connected to the input of the buffer, and simultaneously outputs a signal f. out The output of the buffer Q1 is connected to the input of XOR gate 1, and the output of the buffer Q2 is connected to the input of the programmable logic control module MUX. The input of XOR gate 1 is also connected to the synchronization signal SYNC, the initial logic signal SH, and the mode control signal mod.in .

[0017] Furthermore, the frequency divider cell 2 includes a selector MUX2 and a D flip-flop 2. The input of the D flip-flop 2 is connected to the output of the selector MUX2. The input of the D flip-flop 2 is also connected to an external clock CLKin. The first output is connected to the input of the selector MUX2, and the second output outputs f. out The input terminals of the selector MUX2 are also connected to the programmable logic control module MUX and the three-input AND gate, respectively.

[0018] Furthermore, the frequency divider cell 3 includes a D flip-flop 3 and an XOR gate 3. The input of the D flip-flop 3 is connected to the output of the XOR gate 3. The input of the D flip-flop 3 is also connected to an external input clock CLKin, and its output is connected to the input of the XOR gate 3. The input of the XOR gate 3 is also connected to the preceding frequency divider unit and the programmable logic control module MUX, respectively. The input of the XOR gate 3 is also connected to a mode control signal mod. in .

[0019] Furthermore, the programmable logic control module MUX includes multiple selectors MUX3. The input of each selector MUX3 is connected to a frequency divider cell1, and the output is connected to frequency divider cell2 and frequency divider cells3 through 3, respectively. n The inputs of the selector MUX3 are connected to a synchronization signal SYNC and different values ​​of LC, HC and PO.

[0020] The beneficial effects of this invention are as follows: This invention improves upon the traditional cascaded 2 / 3 frequency divider unit, primarily employing commonly used flip-flop structures, basic logic gate structures, and selectors. The interaction between modules is simple, ensuring circuit flexibility and reusability. Furthermore, this invention expands the division ratio range of traditional frequency dividers, enabling a single programmable frequency divider to achieve 1 to 2... n In addition to integer frequency division, this invention also provides a phase delay adjustment function in steps of the input clock cycle; this invention can realize programmable duty cycle control, and by pre-setting the number of high-level and low-level periods of the frequency division ratio, the duty cycle is configured at the same time as setting the frequency division ratio. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of Example 1;

[0023] Figure 2 This is a schematic diagram of a cascaded programmable frequency divider based on existing 2 / 3 frequency divider modules;

[0024] Figure 3 This is a schematic diagram of a 2 / 3 frequency divider module structure in the prior art;

[0025] Figure 4 This is a schematic diagram of the frequency division unit cell1.

[0026] Figure 5 This is a schematic diagram of the frequency division unit cell2.

[0027] Figure 6 This is a schematic diagram of the frequency division unit cell3.

[0028] Figure 7 This is a schematic diagram of the Programmable Logic Controller (MUX) structure.

[0029] Figure 8 This is a timing diagram of the phase delay function in Example 1;

[0030] Figure 9 This is a diagram illustrating a working example of frequency division in Implementation Example 1. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0032] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0033] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0034] Example 1:

[0035] See Figure 1This embodiment can implement frequency division of integers from 1 to 32. The circuit includes a total of 5 frequency division units, specifically: one frequency division unit cell1, one frequency division unit cell2 and 3 identical frequency division units (frequency division unit cell3, frequency division unit cell4 and frequency division unit cell5), 2 three-input AND gates (first three-input AND gate and second three-input AND gate), 2 two-input AND gates (first two-input AND gate and second two-input AND gate) and a programmable logic control module MUX.

[0036] The specific structure of the frequency division unit cell1 can be seen here. Figure 4 The frequency divider unit cell1 includes a D flip-flop 1, a two-input XOR gate 1, and a buffer. The input port D of the D flip-flop 1 is connected to the output port of the two-input XOR gate 1. The D flip-flop 1 is also connected to an external input clock CLKin (the output signal after being divided by the preceding VCO frequency divider). The output terminal of the D flip-flop 1 is connected to the input terminal of the buffer, and simultaneously outputs a signal f. out The output of buffer Q1 is connected to the input (set terminal AP) of two-input XOR gate 1, and the output of buffer Q2 is connected to the input of programmable logic control module MUX; the input (set terminal BP) of two-input XOR gate 1 is connected to the output of the first three-input AND gate, and the input mod in Signal, when mod in When the signal logic fed back by D flip-flop 1 is different, the output is high; otherwise, the output is low. When the frequency division ratio is 2, only the frequency division unit cell1 works.

[0037] Furthermore, the two-input XOR gate 1 is also connected to an initial logic signal SH and a synchronization control signal SYNC. When SH=0, the initial output is low; when SH=1, the initial output is high. The synchronization function ensures that all outputs configured for synchronization are in a preset state before synchronized output begins. This preset state is determined by the SH control bit and phase mismatch of each channel divider. These settings determine the static mode of the output during synchronization and also determine the phase of the next output when the output signal restarts. After output begins, only the phase mismatch setting is active; the SH control bit is no longer active. When using the SYNC function, the programmable divider can implement phase offset through programming. These settings determine the number of cycles (continuous rising edges) of the channel divider input frequency used to delay the rising edge of the divider output. This delay is relative to the output without delay (i.e., the phase offset is zero). The number of delay cycles is determined by adding one bit of the divider's initial high (SH) bit to the n-bit phase offset (PO) register.

[0038] The specific structure of the frequency division unit cell2 can be seen in [the diagram]. Figure 5The frequency divider cell 2 is located in the second stage and serves as the pre-allocation unit of the frequency divider. Cell 2 includes a selector MUX2 and a D flip-flop 2. The input D of the D flip-flop 2 is connected to the output of the selector MUX2, and the D flip-flop 2 is also connected to an external input clock CLKin. The output of the D flip-flop 2 is connected to the input (preset terminal AP) of the selector MUX2, the input of the first three-input AND gate, and the preset terminal BP of the frequency divider cell 3. The input of the selector MUX2 is connected to the output signal P0 of the programmable logic control module MUX, and also to the signal mod from the output of the first three-input AND gate. in When mod in When the signal is high, selector MUX2 selects the pulse from programmable logic control module MUX; mod in When the signal is low, selector MUX2 selects the pulse signal fed back by D flip-flop 2. The output signal P0 of the last programmable logic control module MUX is mainly used to determine the parity of the frequency division value. When the frequency division ratio is odd, the frequency division ratio control logic HC0=0, LC0=1, selector MUX2 performs a pulse swallowing operation, and outputs the odd frequency division. Frequency division unit cell1 and frequency division unit cell2 together realize the 2, 3, and 4 frequency division.

[0039] The specific structure of the frequency division unit cell3 can be seen in [the diagram]. Figure 6 Frequency divider cell3 includes a two-input XOR gate 3 and a D flip-flop 3, frequency divider cell4 includes a two-input XOR gate 4 and a D flip-flop 4, and frequency divider cell5 includes a two-input XOR gate 5 and a D flip-flop 5. The structures of frequency divider cell3, frequency divider cell4 and frequency divider cell5 are completely identical.

[0040] In this configuration, the input of D flip-flop 3 is connected to the output of the two-input XOR gate 3. D flip-flop 3 is also connected to an external input clock CLKin. The output of D flip-flop 3 is connected to the input of the two-input XOR gate 3, the input of the second three-input AND gate, and the input of the first two-input AND gate. The output of the second three-input AND gate is connected to the input of the first three-input AND gate. The input of the first three-input AND gate is also connected to the synchronization control signal SYNC. The input of the first two-input AND gate is also connected to the output of the frequency divider cell 2. The output of the first two-input AND gate is connected to the input of the two-input XOR gate 4, and the input of the two-input XOR gate 4 is also connected to the output of D flip-flop 4. The input of the two-input XOR gate 3 is also connected to the output of the frequency divider cell 2 (accessed by signal f). in The output terminal of the programmable logic control module MUX (connection signal P1) is connected to the output terminal of the second and third input AND gate (connection signal mod). in ), fin is the output signal after ANDing with the previous frequency divider unit, mod is the output signal. inThe mod signal output by the first three-input AND gate is used as the basic frequency divider unit in the example. When the frequency division ratio is even, the signal fed back by the output of the two-input XOR gate 3 and the output of the D flip-flop 3 is based on the Pi (i = 1, 2, 3...) signal output by the programmable logic to achieve frequency division by 2. When the frequency division ratio is odd, the phase adjustment is performed by the step-by-step frequency divider unit to achieve frequency division.

[0041] The connection relationship between frequency divider cell 4 and frequency divider cell 5 is the same as the connection relationship between frequency divider cell 4 and frequency divider cell 3, and will not be repeated here. Furthermore, those skilled in the art can select the number of identical frequency divider cells cascaded according to the required maximum division ratio. That is, the number of frequency divider cells 3 can be set according to actual conditions. Those skilled in the art can achieve different integer divisions (this embodiment can achieve integer divisions from 1 to 32) by changing the number of frequency divider cells 3 based on this application, and all such implementations should fall within the protection scope of this application.

[0042] The specific structure of the programmable logic control module (MUX) can be seen here. Figure 7 The programmable logic control module (MUX) includes four 3-to-1 selectors (MUX3) (adjusted according to the number of frequency divider cells 3). The inputs of each selector MUX3 are connected to the output Q2 of frequency divider cell 1 and the synchronization control signal SYNC. The output of the first selector MUX3 is connected to frequency divider cell 2, and the outputs of the other selectors MUX3 are connected to frequency divider cells 3, 4, and 5 respectively, determining whether the frequency divider cell is operational. Selectors MUX3 determine the division ratio and phase delay period by inputting different values ​​of LC, HC, and PO. The frequency divider generates different division ratios D based on the P0, P1, P2, and P3 signals output by the programmable logic control unit. X The multi-input AND gate is used to perform an AND operation between the output signals of each basic frequency divider unit and the mod signal. When the input signals from different basic frequency dividers are all high, the mod output is selected to be high. When the output of one frequency divider unit is low, the mod output is selected to be low.

[0043] The frequency division ratio D of this invention X It is determined by the values ​​of HC and LC (HC and LC can be programmed to take values ​​between 0 and 15), here: number of low cycles = LC + 1, number of high cycles = HC + 1, when the frequency divider is bypassed D X =1, in other cases, D X= (LC+1)+(HC+1)=HC+LC+2. The duty cycle of the channel output signal is affected by the values ​​of HC and LC of the channel divider and the duty cycle of the input clock. Based on the above analysis, the duty cycle of the output signal can be obtained as (HC+1) / (HC+LC+2).

[0044] Furthermore, the timing of frequency division in this embodiment is as follows: Figure 8 and Figure 9 As shown.

[0045] This invention improves upon the traditional cascaded 2 / 3 frequency divider unit, primarily employing common flip-flop structures, basic logic gate structures, and selectors. The interaction between modules is simple, ensuring circuit flexibility and reusability. This invention further expands the division ratio range of traditional frequency dividers, enabling a single programmable frequency divider to achieve 1 to 2... n In addition to integer frequency division, this invention also provides a phase delay adjustment function in steps of the input clock cycle. This invention enables programmable duty cycle control; by pre-setting the number of high-level and low-level periods of the frequency division ratio, the duty cycle is configured simultaneously with the frequency division ratio.

[0046] It should be noted that, in the foregoing embodiments, the terms "connection" and "setting" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "connection" or "setting" may explicitly or implicitly include one or more of that feature. Furthermore, the terms "connection," "setting," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein.

[0047] The above embodiments describe the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Modifications and variations made by those skilled in the art without departing from the spirit and scope of the invention should be within the protection scope of the appended claims.

Claims

1. A programmable frequency divider with adjustable duty cycle, characterized in that, Includes multiple cascaded frequency division units cell1, cell2, cell3, and so on. n And a programmable logic control module (MUX), wherein the frequency division units cell1, cell2, and cell3 are different frequency division units, and the frequency division units cell3 to cell4 are... n Using the same frequency divider unit, the output of frequency divider unit cell2 is connected to one input terminal of frequency divider unit cell3, and frequency divider units cell3~cell3 n The output of cell2 is logically ANDed with the output of the previous frequency divider unit, and then connected to one input of the next frequency divider unit. n Each of its output terminals is also connected to its other input terminal, from the last stage frequency divider cell. n Starting from the beginning, sequentially divide the frequency division units cell2 to cell3. n The output groups are connected to multiple cascaded three-input AND gates. The output of the last three-input AND gate is connected to one input of each frequency divider unit. The first output of frequency divider unit cell1 is connected to its other input, and the second output is connected to the input of the programmable logic controller (MUX). The output of the MUX is connected to frequency divider units cell2 through cell3. n The preset terminal is connected, and the arbitrary programmable frequency division ratio is realized through the programmable logic control module MUX.

2. The programmable frequency divider with adjustable duty cycle as described in claim 1, characterized in that, The frequency divider cell1, the last stage three-input AND gate, and the input of the programmable logic control module MUX are all connected to the synchronization signal SYNC.

3. A programmable frequency divider with adjustable duty cycle as described in claim 1, characterized in that, Select the frequency division unit cell3 to cell4 based on the required maximum frequency division ratio. n The number of.

4. A programmable frequency divider with adjustable duty cycle as described in claim 1, characterized in that, The frequency division ratio is determined by the values ​​of HC and LC, where LC = number of low cycles - 1; HC = number of high cycles - 1, and the values ​​of HC and LC range from [0, 15].

5. A programmable frequency divider with adjustable duty cycle as described in claim 4, characterized in that, When the frequency divider is bypassed, the division ratio is 1; otherwise, the division ratio = HC + LC + 2.

6. A programmable frequency divider with adjustable duty cycle as described in claim 4, characterized in that, The duty cycle of the output signal of the programmable frequency divider is: (HC+1) / (HC+LC+2).

7. A programmable frequency divider with adjustable duty cycle as described in claim 1, characterized in that, The frequency divider cell 1 includes a D flip-flop 1, an XOR gate 1, and a buffer. The input of the D flip-flop 1 is connected to the XOR gate 1. The input of the D flip-flop 1 is also connected to an external clock CLKin. The output is connected to the input of the buffer, and simultaneously outputs a signal f. out The output of the buffer Q1 is connected to the input of XOR gate 1, and the output of the buffer Q2 is connected to the input of the programmable logic control module MUX. The input of XOR gate 1 is also connected to the synchronization signal SYNC, the initial logic signal SH, and the mode control signal mod. in .

8. A programmable frequency divider with adjustable duty cycle as described in claim 1, characterized in that, The frequency divider cell 2 includes a selector MUX2 and a D flip-flop 2. The input of the D flip-flop 2 is connected to the output of the selector MUX2. An external clock CLKin is also connected to the input of the D flip-flop 2. The first output is connected to the input of the selector MUX2, and the second output outputs f. out The input terminals of the selector MUX2 are also connected to the programmable logic control module MUX and the three-input AND gate, respectively.

9. A programmable frequency divider with adjustable duty cycle as described in claim 1, characterized in that, The frequency divider unit cell3 includes a D flip-flop 3 and an XOR gate 3. The input of the D flip-flop 3 is connected to the output of the XOR gate 3. The input of the D flip-flop 3 is also connected to an external input clock CLKin, and its output is connected to the input of the XOR gate 3. The input of the XOR gate 3 is also connected to the preceding frequency divider unit and the programmable logic control module MUX. The input of the XOR gate 3 is also connected to a mode control signal mod. in .

10. A programmable frequency divider with adjustable duty cycle as described in claim 1, characterized in that, The programmable logic control module (MUX) includes multiple selectors (MUX3). The input of each selector (MUX3) is connected to a frequency divider unit (cell1), and its output is connected to frequency divider units (cell2 and cells3-cell3). n The inputs of the selector MUX3 are connected to a synchronization signal SYNC and different values ​​of LC, HC and PO.

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